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1da177e4 LT |
1 | /* |
2 | ** linux/atarihw.h -- This header defines some macros and pointers for | |
3 | ** the various Atari custom hardware registers. | |
4 | ** | |
1039592d | 5 | ** Copyright 1994 by Björn Brauel |
1da177e4 LT |
6 | ** |
7 | ** 5/1/94 Roman Hodek: | |
8 | ** Added definitions for TT specific chips. | |
9 | ** | |
10 | ** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>: | |
11 | ** Finally added definitions for the matrix/codec and the DSP56001 host | |
12 | ** interface. | |
13 | ** | |
14 | ** This file is subject to the terms and conditions of the GNU General Public | |
15 | ** License. See the file COPYING in the main directory of this archive | |
16 | ** for more details. | |
17 | ** | |
18 | */ | |
19 | ||
20 | #ifndef _LINUX_ATARIHW_H_ | |
21 | #define _LINUX_ATARIHW_H_ | |
22 | ||
23 | #include <linux/types.h> | |
24 | #include <asm/bootinfo.h> | |
25 | #include <asm/raw_io.h> | |
26 | ||
27 | extern u_long atari_mch_cookie; | |
28 | extern u_long atari_mch_type; | |
29 | extern u_long atari_switches; | |
30 | extern int atari_rtc_year_offset; | |
31 | extern int atari_dont_touch_floppy_select; | |
32 | ||
33 | /* convenience macros for testing machine type */ | |
34 | #define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST) | |
35 | #define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ | |
36 | (atari_mch_cookie & 0xffff) == 0) | |
37 | #define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ | |
38 | (atari_mch_cookie & 0xffff) == 0x10) | |
39 | #define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT) | |
40 | #define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON) | |
41 | #define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA) | |
42 | #define MACH_IS_HADES (atari_mch_type == ATARI_MACH_HADES) | |
43 | #define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40) | |
44 | ||
45 | /* values for atari_switches */ | |
46 | #define ATARI_SWITCH_IKBD 0x01 | |
47 | #define ATARI_SWITCH_MIDI 0x02 | |
48 | #define ATARI_SWITCH_SND6 0x04 | |
49 | #define ATARI_SWITCH_SND7 0x08 | |
50 | #define ATARI_SWITCH_OVSC_SHIFT 16 | |
51 | #define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT) | |
52 | #define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT) | |
53 | #define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT) | |
54 | #define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT) | |
55 | #define ATARI_SWITCH_OVSC_MASK 0xffff0000 | |
56 | ||
57 | /* | |
58 | * Define several Hardware-Chips for indication so that for the ATARI we do | |
59 | * no longer decide whether it is a Falcon or other machine . It's just | |
60 | * important what hardware the machine uses | |
61 | */ | |
62 | ||
63 | /* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */ | |
64 | ||
65 | #define ATARIHW_DECLARE(name) unsigned name : 1 | |
66 | #define ATARIHW_SET(name) (atari_hw_present.name = 1) | |
67 | #define ATARIHW_PRESENT(name) (atari_hw_present.name) | |
68 | ||
69 | struct atari_hw_present { | |
70 | /* video hardware */ | |
71 | ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */ | |
72 | ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */ | |
73 | ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */ | |
74 | ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */ | |
75 | /* sound hardware */ | |
76 | ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */ | |
77 | ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */ | |
78 | ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */ | |
79 | /* disk storage interfaces */ | |
80 | ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */ | |
81 | ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */ | |
82 | ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */ | |
83 | ATARIHW_DECLARE(IDE); /* IDE Interface */ | |
84 | ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */ | |
85 | /* other I/O hardware */ | |
86 | ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari | |
87 | without it... but who knows?) */ | |
88 | ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */ | |
89 | ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */ | |
90 | ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */ | |
91 | ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe | |
92 | and Falcon */ | |
93 | ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */ | |
94 | /* DMA */ | |
95 | ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */ | |
96 | ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */ | |
97 | ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */ | |
98 | ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */ | |
99 | /* real time clocks */ | |
100 | ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */ | |
101 | ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */ | |
102 | /* supporting hardware */ | |
103 | ATARIHW_DECLARE(SCU); /* System Control Unit */ | |
104 | ATARIHW_DECLARE(BLITTER); /* Blitter */ | |
105 | ATARIHW_DECLARE(VME); /* VME Bus */ | |
106 | ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */ | |
107 | }; | |
108 | ||
109 | extern struct atari_hw_present atari_hw_present; | |
110 | ||
111 | ||
112 | /* Reading the MFP port register gives a machine independent delay, since the | |
113 | * MFP always has a 8 MHz clock. This avoids problems with the varying length | |
114 | * of nops on various machines. Somebody claimed that the tstb takes 600 ns. | |
115 | */ | |
116 | #define MFPDELAY() \ | |
117 | __asm__ __volatile__ ( "tstb %0" : : "m" (mfp.par_dt_reg) : "cc" ); | |
118 | ||
119 | /* Do cache push/invalidate for DMA read/write. This function obeys the | |
120 | * snooping on some machines (Medusa) and processors: The Medusa itself can | |
121 | * snoop, but only the '040 can source data from its cache to DMA writes i.e., | |
122 | * reads from memory). Both '040 and '060 invalidate cache entries on snooped | |
123 | * DMA reads (i.e., writes to memory). | |
124 | */ | |
125 | ||
126 | ||
127 | #define atari_readb raw_inb | |
128 | #define atari_writeb raw_outb | |
129 | ||
130 | #define atari_inb_p raw_inb | |
131 | #define atari_outb_p raw_outb | |
132 | ||
133 | ||
134 | ||
135 | #include <linux/mm.h> | |
136 | #include <asm/cacheflush.h> | |
137 | ||
138 | static inline void dma_cache_maintenance( unsigned long paddr, | |
139 | unsigned long len, | |
140 | int writeflag ) | |
141 | ||
142 | { | |
143 | if (writeflag) { | |
144 | if (!MACH_IS_MEDUSA || CPU_IS_060) | |
145 | cache_push( paddr, len ); | |
146 | } | |
147 | else { | |
148 | if (!MACH_IS_MEDUSA) | |
149 | cache_clear( paddr, len ); | |
150 | } | |
151 | } | |
152 | ||
153 | ||
154 | /* | |
155 | ** Shifter | |
156 | */ | |
157 | #define ST_LOW 0 | |
158 | #define ST_MID 1 | |
159 | #define ST_HIGH 2 | |
160 | #define TT_LOW 7 | |
161 | #define TT_MID 4 | |
162 | #define TT_HIGH 6 | |
163 | ||
164 | #define SHF_BAS (0xffff8200) | |
165 | struct SHIFTER | |
166 | { | |
167 | u_char pad1; | |
168 | u_char bas_hi; | |
169 | u_char pad2; | |
170 | u_char bas_md; | |
171 | u_char pad3; | |
172 | u_char volatile vcounthi; | |
173 | u_char pad4; | |
174 | u_char volatile vcountmid; | |
175 | u_char pad5; | |
176 | u_char volatile vcountlow; | |
177 | u_char volatile syncmode; | |
178 | u_char pad6; | |
179 | u_char pad7; | |
180 | u_char bas_lo; | |
181 | }; | |
182 | # define shifter ((*(volatile struct SHIFTER *)SHF_BAS)) | |
183 | ||
184 | #define SHF_FBAS (0xffff820e) | |
185 | struct SHIFTER_F030 | |
186 | { | |
187 | u_short off_next; | |
188 | u_short scn_width; | |
189 | }; | |
190 | # define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS)) | |
191 | ||
192 | ||
193 | #define SHF_TBAS (0xffff8200) | |
194 | struct SHIFTER_TT { | |
195 | u_char char_dummy0; | |
196 | u_char bas_hi; /* video mem base addr, high and mid byte */ | |
197 | u_char char_dummy1; | |
198 | u_char bas_md; | |
199 | u_char char_dummy2; | |
200 | u_char vcount_hi; /* pointer to currently displayed byte */ | |
201 | u_char char_dummy3; | |
202 | u_char vcount_md; | |
203 | u_char char_dummy4; | |
204 | u_char vcount_lo; | |
205 | u_short st_sync; /* ST compatible sync mode register, unused */ | |
206 | u_char char_dummy5; | |
207 | u_char bas_lo; /* video mem addr, low byte */ | |
208 | u_char char_dummy6[2+3*16]; | |
209 | /* $ffff8240: */ | |
210 | u_short color_reg[16]; /* 16 color registers */ | |
211 | u_char st_shiftmode; /* ST compatible shift mode register, unused */ | |
212 | u_char char_dummy7; | |
213 | u_short tt_shiftmode; /* TT shift mode register */ | |
214 | ||
215 | ||
216 | }; | |
217 | #define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS)) | |
218 | ||
219 | /* values for shifter_tt->tt_shiftmode */ | |
220 | #define TT_SHIFTER_STLOW 0x0000 | |
221 | #define TT_SHIFTER_STMID 0x0100 | |
222 | #define TT_SHIFTER_STHIGH 0x0200 | |
223 | #define TT_SHIFTER_TTLOW 0x0700 | |
224 | #define TT_SHIFTER_TTMID 0x0400 | |
225 | #define TT_SHIFTER_TTHIGH 0x0600 | |
226 | #define TT_SHIFTER_MODEMASK 0x0700 | |
227 | #define TT_SHIFTER_NUMMODE 0x0008 | |
228 | #define TT_SHIFTER_PALETTE_MASK 0x000f | |
229 | #define TT_SHIFTER_GRAYMODE 0x1000 | |
230 | ||
231 | /* 256 TT palette registers */ | |
232 | #define TT_PALETTE_BASE (0xffff8400) | |
233 | #define tt_palette ((volatile u_short *)TT_PALETTE_BASE) | |
234 | ||
235 | #define TT_PALETTE_RED_MASK 0x0f00 | |
236 | #define TT_PALETTE_GREEN_MASK 0x00f0 | |
237 | #define TT_PALETTE_BLUE_MASK 0x000f | |
238 | ||
239 | /* | |
240 | ** Falcon030 VIDEL Video Controller | |
241 | ** for description see File 'linux\tools\atari\hardware.txt | |
242 | */ | |
243 | #define f030_col ((u_long *) 0xffff9800) | |
244 | #define f030_xreg ((u_short*) 0xffff8282) | |
245 | #define f030_yreg ((u_short*) 0xffff82a2) | |
246 | #define f030_creg ((u_short*) 0xffff82c0) | |
247 | #define f030_sreg ((u_short*) 0xffff8260) | |
248 | #define f030_mreg ((u_short*) 0xffff820a) | |
249 | #define f030_linewidth ((u_short*) 0xffff820e) | |
250 | #define f030_hscroll ((u_char*) 0xffff8265) | |
251 | ||
252 | #define VIDEL_BAS (0xffff8260) | |
253 | struct VIDEL { | |
254 | u_short st_shift; | |
255 | u_short pad1; | |
256 | u_char xoffset_s; | |
257 | u_char xoffset; | |
258 | u_short f_shift; | |
259 | u_char pad2[0x1a]; | |
260 | u_short hht; | |
261 | u_short hbb; | |
262 | u_short hbe; | |
263 | u_short hdb; | |
264 | u_short hde; | |
265 | u_short hss; | |
266 | u_char pad3[0x14]; | |
267 | u_short vft; | |
268 | u_short vbb; | |
269 | u_short vbe; | |
270 | u_short vdb; | |
271 | u_short vde; | |
272 | u_short vss; | |
273 | u_char pad4[0x12]; | |
274 | u_short control; | |
275 | u_short mode; | |
276 | }; | |
277 | #define videl ((*(volatile struct VIDEL *)VIDEL_BAS)) | |
278 | ||
279 | /* | |
280 | ** DMA/WD1772 Disk Controller | |
281 | */ | |
282 | ||
283 | #define FWD_BAS (0xffff8604) | |
284 | struct DMA_WD | |
285 | { | |
286 | u_short fdc_acces_seccount; | |
287 | u_short dma_mode_status; | |
288 | u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */ | |
289 | u_char dma_hi; | |
290 | u_char char_dummy2; | |
291 | u_char dma_md; | |
292 | u_char char_dummy3; | |
293 | u_char dma_lo; | |
294 | u_short fdc_speed; | |
295 | }; | |
296 | # define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS)) | |
297 | /* alias */ | |
298 | #define st_dma dma_wd | |
299 | /* The two highest bytes of an extended DMA as a short; this is a must | |
300 | * for the Medusa. | |
301 | */ | |
302 | #define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608)) | |
303 | ||
304 | /* | |
305 | ** YM2149 Sound Chip | |
306 | ** access in bytes | |
307 | */ | |
308 | ||
309 | #define YM_BAS (0xffff8800) | |
310 | struct SOUND_YM | |
311 | { | |
312 | u_char rd_data_reg_sel; | |
313 | u_char char_dummy1; | |
314 | u_char wd_data; | |
315 | }; | |
316 | #define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS)) | |
317 | ||
318 | /* TT SCSI DMA */ | |
319 | ||
320 | #define TT_SCSI_DMA_BAS (0xffff8700) | |
321 | struct TT_DMA { | |
322 | u_char char_dummy0; | |
323 | u_char dma_addr_hi; | |
324 | u_char char_dummy1; | |
325 | u_char dma_addr_hmd; | |
326 | u_char char_dummy2; | |
327 | u_char dma_addr_lmd; | |
328 | u_char char_dummy3; | |
329 | u_char dma_addr_lo; | |
330 | u_char char_dummy4; | |
331 | u_char dma_cnt_hi; | |
332 | u_char char_dummy5; | |
333 | u_char dma_cnt_hmd; | |
334 | u_char char_dummy6; | |
335 | u_char dma_cnt_lmd; | |
336 | u_char char_dummy7; | |
337 | u_char dma_cnt_lo; | |
338 | u_long dma_restdata; | |
339 | u_short dma_ctrl; | |
340 | }; | |
341 | #define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS)) | |
342 | ||
343 | /* TT SCSI Controller 5380 */ | |
344 | ||
345 | #define TT_5380_BAS (0xffff8781) | |
346 | struct TT_5380 { | |
347 | u_char scsi_data; | |
348 | u_char char_dummy1; | |
349 | u_char scsi_icr; | |
350 | u_char char_dummy2; | |
351 | u_char scsi_mode; | |
352 | u_char char_dummy3; | |
353 | u_char scsi_tcr; | |
354 | u_char char_dummy4; | |
355 | u_char scsi_idstat; | |
356 | u_char char_dummy5; | |
357 | u_char scsi_dmastat; | |
358 | u_char char_dummy6; | |
359 | u_char scsi_targrcv; | |
360 | u_char char_dummy7; | |
361 | u_char scsi_inircv; | |
362 | }; | |
363 | #define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS)) | |
364 | #define tt_scsi_regp ((volatile char *)TT_5380_BAS) | |
365 | ||
366 | ||
367 | /* | |
368 | ** Falcon DMA Sound Subsystem | |
369 | */ | |
370 | ||
371 | #define MATRIX_BASE (0xffff8930) | |
372 | struct MATRIX | |
373 | { | |
374 | u_short source; | |
375 | u_short destination; | |
376 | u_char external_frequency_divider; | |
377 | u_char internal_frequency_divider; | |
378 | }; | |
379 | #define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE) | |
380 | ||
381 | #define CODEC_BASE (0xffff8936) | |
382 | struct CODEC | |
383 | { | |
384 | u_char tracks; | |
385 | u_char input_source; | |
386 | #define CODEC_SOURCE_ADC 1 | |
387 | #define CODEC_SOURCE_MATRIX 2 | |
388 | u_char adc_source; | |
389 | #define ADC_SOURCE_RIGHT_PSG 1 | |
390 | #define ADC_SOURCE_LEFT_PSG 2 | |
391 | u_char gain; | |
392 | #define CODEC_GAIN_RIGHT 0x0f | |
393 | #define CODEC_GAIN_LEFT 0xf0 | |
394 | u_char attenuation; | |
395 | #define CODEC_ATTENUATION_RIGHT 0x0f | |
396 | #define CODEC_ATTENUATION_LEFT 0xf0 | |
397 | u_char unused1; | |
398 | u_char status; | |
399 | #define CODEC_OVERFLOW_RIGHT 1 | |
400 | #define CODEC_OVERFLOW_LEFT 2 | |
401 | u_char unused2, unused3, unused4, unused5; | |
402 | u_char gpio_directions; | |
403 | #define GPIO_IN 0 | |
404 | #define GPIO_OUT 1 | |
405 | u_char unused6; | |
406 | u_char gpio_data; | |
407 | }; | |
408 | #define falcon_codec (*(volatile struct CODEC *)CODEC_BASE) | |
409 | ||
410 | /* | |
411 | ** Falcon Blitter | |
412 | */ | |
413 | ||
414 | #define BLT_BAS (0xffff8a00) | |
415 | ||
416 | struct BLITTER | |
417 | { | |
418 | u_short halftone[16]; | |
419 | u_short src_x_inc; | |
420 | u_short src_y_inc; | |
421 | u_long src_address; | |
422 | u_short endmask1; | |
423 | u_short endmask2; | |
424 | u_short endmask3; | |
425 | u_short dst_x_inc; | |
426 | u_short dst_y_inc; | |
427 | u_long dst_address; | |
428 | u_short wd_per_line; | |
429 | u_short ln_per_bb; | |
430 | u_short hlf_op_reg; | |
431 | u_short log_op_reg; | |
432 | u_short lin_nm_reg; | |
433 | u_short skew_reg; | |
434 | }; | |
435 | # define blitter ((*(volatile struct BLITTER *)BLT_BAS)) | |
436 | ||
437 | ||
438 | /* | |
439 | ** SCC Z8530 | |
440 | */ | |
441 | ||
442 | #define SCC_BAS (0xffff8c81) | |
443 | struct SCC | |
444 | { | |
445 | u_char cha_a_ctrl; | |
446 | u_char char_dummy1; | |
447 | u_char cha_a_data; | |
448 | u_char char_dummy2; | |
449 | u_char cha_b_ctrl; | |
450 | u_char char_dummy3; | |
451 | u_char cha_b_data; | |
452 | }; | |
453 | # define scc ((*(volatile struct SCC*)SCC_BAS)) | |
454 | ||
455 | /* The ESCC (Z85230) in an Atari ST. The channels are reversed! */ | |
456 | # define st_escc ((*(volatile struct SCC*)0xfffffa31)) | |
457 | # define st_escc_dsr ((*(volatile char *)0xfffffa39)) | |
458 | ||
459 | /* TT SCC DMA Controller (same chip as SCSI DMA) */ | |
460 | ||
461 | #define TT_SCC_DMA_BAS (0xffff8c00) | |
462 | #define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS)) | |
463 | ||
464 | /* | |
465 | ** VIDEL Palette Register | |
466 | */ | |
467 | ||
468 | #define FPL_BAS (0xffff9800) | |
469 | struct VIDEL_PALETTE | |
470 | { | |
471 | u_long reg[256]; | |
472 | }; | |
473 | # define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS)) | |
474 | ||
475 | ||
476 | /* | |
477 | ** Falcon DSP Host Interface | |
478 | */ | |
479 | ||
480 | #define DSP56K_HOST_INTERFACE_BASE (0xffffa200) | |
481 | struct DSP56K_HOST_INTERFACE { | |
482 | u_char icr; | |
483 | #define DSP56K_ICR_RREQ 0x01 | |
484 | #define DSP56K_ICR_TREQ 0x02 | |
485 | #define DSP56K_ICR_HF0 0x08 | |
486 | #define DSP56K_ICR_HF1 0x10 | |
487 | #define DSP56K_ICR_HM0 0x20 | |
488 | #define DSP56K_ICR_HM1 0x40 | |
489 | #define DSP56K_ICR_INIT 0x80 | |
490 | ||
491 | u_char cvr; | |
492 | #define DSP56K_CVR_HV_MASK 0x1f | |
493 | #define DSP56K_CVR_HC 0x80 | |
494 | ||
495 | u_char isr; | |
496 | #define DSP56K_ISR_RXDF 0x01 | |
497 | #define DSP56K_ISR_TXDE 0x02 | |
498 | #define DSP56K_ISR_TRDY 0x04 | |
499 | #define DSP56K_ISR_HF2 0x08 | |
500 | #define DSP56K_ISR_HF3 0x10 | |
501 | #define DSP56K_ISR_DMA 0x40 | |
502 | #define DSP56K_ISR_HREQ 0x80 | |
503 | ||
504 | u_char ivr; | |
505 | ||
506 | union { | |
507 | u_char b[4]; | |
508 | u_short w[2]; | |
509 | u_long l; | |
510 | } data; | |
511 | }; | |
512 | #define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE)) | |
513 | ||
514 | /* | |
515 | ** MFP 68901 | |
516 | */ | |
517 | ||
518 | #define MFP_BAS (0xfffffa01) | |
519 | struct MFP | |
520 | { | |
521 | u_char par_dt_reg; | |
522 | u_char char_dummy1; | |
523 | u_char active_edge; | |
524 | u_char char_dummy2; | |
525 | u_char data_dir; | |
526 | u_char char_dummy3; | |
527 | u_char int_en_a; | |
528 | u_char char_dummy4; | |
529 | u_char int_en_b; | |
530 | u_char char_dummy5; | |
531 | u_char int_pn_a; | |
532 | u_char char_dummy6; | |
533 | u_char int_pn_b; | |
534 | u_char char_dummy7; | |
535 | u_char int_sv_a; | |
536 | u_char char_dummy8; | |
537 | u_char int_sv_b; | |
538 | u_char char_dummy9; | |
539 | u_char int_mk_a; | |
540 | u_char char_dummy10; | |
541 | u_char int_mk_b; | |
542 | u_char char_dummy11; | |
543 | u_char vec_adr; | |
544 | u_char char_dummy12; | |
545 | u_char tim_ct_a; | |
546 | u_char char_dummy13; | |
547 | u_char tim_ct_b; | |
548 | u_char char_dummy14; | |
549 | u_char tim_ct_cd; | |
550 | u_char char_dummy15; | |
551 | u_char tim_dt_a; | |
552 | u_char char_dummy16; | |
553 | u_char tim_dt_b; | |
554 | u_char char_dummy17; | |
555 | u_char tim_dt_c; | |
556 | u_char char_dummy18; | |
557 | u_char tim_dt_d; | |
558 | u_char char_dummy19; | |
559 | u_char sync_char; | |
560 | u_char char_dummy20; | |
561 | u_char usart_ctr; | |
562 | u_char char_dummy21; | |
563 | u_char rcv_stat; | |
564 | u_char char_dummy22; | |
565 | u_char trn_stat; | |
566 | u_char char_dummy23; | |
567 | u_char usart_dta; | |
568 | }; | |
569 | # define mfp ((*(volatile struct MFP*)MFP_BAS)) | |
570 | ||
571 | /* TT's second MFP */ | |
572 | ||
573 | #define TT_MFP_BAS (0xfffffa81) | |
574 | # define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS)) | |
575 | ||
576 | ||
577 | /* TT System Control Unit */ | |
578 | ||
579 | #define TT_SCU_BAS (0xffff8e01) | |
580 | struct TT_SCU { | |
581 | u_char sys_mask; | |
582 | u_char char_dummy1; | |
583 | u_char sys_stat; | |
584 | u_char char_dummy2; | |
585 | u_char softint; | |
586 | u_char char_dummy3; | |
587 | u_char vmeint; | |
588 | u_char char_dummy4; | |
589 | u_char gp_reg1; | |
590 | u_char char_dummy5; | |
591 | u_char gp_reg2; | |
592 | u_char char_dummy6; | |
593 | u_char vme_mask; | |
594 | u_char char_dummy7; | |
595 | u_char vme_stat; | |
596 | }; | |
597 | #define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS)) | |
598 | ||
599 | /* TT real time clock */ | |
600 | ||
601 | #define TT_RTC_BAS (0xffff8961) | |
602 | struct TT_RTC { | |
603 | u_char regsel; | |
604 | u_char dummy; | |
605 | u_char data; | |
606 | }; | |
607 | #define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS)) | |
608 | ||
609 | ||
610 | /* | |
611 | ** ACIA 6850 | |
612 | */ | |
613 | /* constants for the ACIA registers */ | |
614 | ||
615 | /* baudrate selection and reset (Baudrate = clock/factor) */ | |
616 | #define ACIA_DIV1 0 | |
617 | #define ACIA_DIV16 1 | |
618 | #define ACIA_DIV64 2 | |
619 | #define ACIA_RESET 3 | |
620 | ||
621 | /* character format */ | |
622 | #define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */ | |
623 | #define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */ | |
624 | #define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */ | |
625 | #define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */ | |
626 | #define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */ | |
627 | #define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */ | |
628 | #define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */ | |
629 | #define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */ | |
630 | ||
631 | /* transmit control */ | |
632 | #define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */ | |
633 | #define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */ | |
634 | #define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */ | |
635 | #define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */ | |
636 | ||
637 | /* receive control */ | |
638 | #define ACIA_RID (0<<7) /* RxINT disabled */ | |
639 | #define ACIA_RIE (1<<7) /* RxINT enabled */ | |
640 | ||
641 | /* status fields of the ACIA */ | |
642 | #define ACIA_RDRF 1 /* Receive Data Register Full */ | |
643 | #define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */ | |
644 | #define ACIA_DCD (1<<2) /* Data Carrier Detect */ | |
645 | #define ACIA_CTS (1<<3) /* Clear To Send */ | |
646 | #define ACIA_FE (1<<4) /* Framing Error */ | |
647 | #define ACIA_OVRN (1<<5) /* Receiver Overrun */ | |
648 | #define ACIA_PE (1<<6) /* Parity Error */ | |
649 | #define ACIA_IRQ (1<<7) /* Interrupt Request */ | |
650 | ||
651 | #define ACIA_BAS (0xfffffc00) | |
652 | struct ACIA | |
653 | { | |
654 | u_char key_ctrl; | |
655 | u_char char_dummy1; | |
656 | u_char key_data; | |
657 | u_char char_dummy2; | |
658 | u_char mid_ctrl; | |
659 | u_char char_dummy3; | |
660 | u_char mid_data; | |
661 | }; | |
662 | # define acia ((*(volatile struct ACIA*)ACIA_BAS)) | |
663 | ||
664 | #define TT_DMASND_BAS (0xffff8900) | |
665 | struct TT_DMASND { | |
666 | u_char int_ctrl; /* Falcon: Interrupt control */ | |
667 | u_char ctrl; | |
668 | u_char pad2; | |
669 | u_char bas_hi; | |
670 | u_char pad3; | |
671 | u_char bas_mid; | |
672 | u_char pad4; | |
673 | u_char bas_low; | |
674 | u_char pad5; | |
675 | u_char addr_hi; | |
676 | u_char pad6; | |
677 | u_char addr_mid; | |
678 | u_char pad7; | |
679 | u_char addr_low; | |
680 | u_char pad8; | |
681 | u_char end_hi; | |
682 | u_char pad9; | |
683 | u_char end_mid; | |
684 | u_char pad10; | |
685 | u_char end_low; | |
686 | u_char pad11[12]; | |
687 | u_char track_select; /* Falcon */ | |
688 | u_char mode; | |
689 | u_char pad12[14]; | |
690 | /* Falcon only: */ | |
691 | u_short cbar_src; | |
692 | u_short cbar_dst; | |
693 | u_char ext_div; | |
694 | u_char int_div; | |
695 | u_char rec_track_select; | |
696 | u_char dac_src; | |
697 | u_char adc_src; | |
698 | u_char input_gain; | |
699 | u_short output_atten; | |
700 | }; | |
701 | # define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS)) | |
702 | ||
703 | #define DMASND_MFP_INT_REPLAY 0x01 | |
704 | #define DMASND_MFP_INT_RECORD 0x02 | |
705 | #define DMASND_TIMERA_INT_REPLAY 0x04 | |
706 | #define DMASND_TIMERA_INT_RECORD 0x08 | |
707 | ||
708 | #define DMASND_CTRL_OFF 0x00 | |
709 | #define DMASND_CTRL_ON 0x01 | |
710 | #define DMASND_CTRL_REPEAT 0x02 | |
711 | #define DMASND_CTRL_RECORD_ON 0x10 | |
712 | #define DMASND_CTRL_RECORD_OFF 0x00 | |
713 | #define DMASND_CTRL_RECORD_REPEAT 0x20 | |
714 | #define DMASND_CTRL_SELECT_REPLAY 0x00 | |
715 | #define DMASND_CTRL_SELECT_RECORD 0x80 | |
716 | #define DMASND_MODE_MONO 0x80 | |
717 | #define DMASND_MODE_STEREO 0x00 | |
718 | #define DMASND_MODE_8BIT 0x00 | |
719 | #define DMASND_MODE_16BIT 0x40 /* Falcon only */ | |
720 | #define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */ | |
721 | #define DMASND_MODE_12KHZ 0x01 | |
722 | #define DMASND_MODE_25KHZ 0x02 | |
723 | #define DMASND_MODE_50KHZ 0x03 | |
724 | ||
725 | ||
726 | #define DMASNDSetBase(bufstart) \ | |
727 | do { \ | |
728 | tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \ | |
729 | tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \ | |
730 | tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \ | |
731 | } while( 0 ) | |
732 | ||
733 | #define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \ | |
734 | (tt_dmasnd.addr_mid << 8) + \ | |
735 | (tt_dmasnd.addr_low)) | |
736 | ||
737 | #define DMASNDSetEnd(bufend) \ | |
738 | do { \ | |
739 | tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \ | |
740 | tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \ | |
741 | tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \ | |
742 | } while( 0 ) | |
743 | ||
744 | ||
745 | #define TT_MICROWIRE_BAS (0xffff8922) | |
746 | struct TT_MICROWIRE { | |
747 | u_short data; | |
748 | u_short mask; | |
749 | }; | |
750 | # define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS)) | |
751 | ||
752 | #define MW_LM1992_ADDR 0x0400 | |
753 | ||
754 | #define MW_LM1992_VOLUME(dB) \ | |
755 | (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2))) | |
756 | #define MW_LM1992_BALLEFT(dB) \ | |
757 | (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) | |
758 | #define MW_LM1992_BALRIGHT(dB) \ | |
759 | (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) | |
760 | #define MW_LM1992_TREBLE(dB) \ | |
761 | (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) | |
762 | #define MW_LM1992_BASS(dB) \ | |
763 | (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) | |
764 | ||
765 | #define MW_LM1992_PSG_LOW 0x000 | |
766 | #define MW_LM1992_PSG_HIGH 0x001 | |
767 | #define MW_LM1992_PSG_OFF 0x002 | |
768 | ||
769 | #define MSTE_RTC_BAS (0xfffffc21) | |
770 | ||
771 | struct MSTE_RTC { | |
772 | u_char sec_ones; | |
773 | u_char dummy1; | |
774 | u_char sec_tens; | |
775 | u_char dummy2; | |
776 | u_char min_ones; | |
777 | u_char dummy3; | |
778 | u_char min_tens; | |
779 | u_char dummy4; | |
780 | u_char hr_ones; | |
781 | u_char dummy5; | |
782 | u_char hr_tens; | |
783 | u_char dummy6; | |
784 | u_char weekday; | |
785 | u_char dummy7; | |
786 | u_char day_ones; | |
787 | u_char dummy8; | |
788 | u_char day_tens; | |
789 | u_char dummy9; | |
790 | u_char mon_ones; | |
791 | u_char dummy10; | |
792 | u_char mon_tens; | |
793 | u_char dummy11; | |
794 | u_char year_ones; | |
795 | u_char dummy12; | |
796 | u_char year_tens; | |
797 | u_char dummy13; | |
798 | u_char mode; | |
799 | u_char dummy14; | |
800 | u_char test; | |
801 | u_char dummy15; | |
802 | u_char reset; | |
803 | }; | |
804 | ||
805 | #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS)) | |
806 | ||
807 | #endif /* linux/atarihw.h */ | |
808 |