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1da177e4 LT |
1 | #ifndef _ASM_M32R_SYSTEM_H |
2 | #define _ASM_M32R_SYSTEM_H | |
3 | ||
4 | /* | |
5 | * This file is subject to the terms and conditions of the GNU General Public | |
6 | * License. See the file "COPYING" in the main directory of this archive | |
7 | * for more details. | |
8 | * | |
4127272c HT |
9 | * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto |
10 | * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org> | |
1da177e4 LT |
11 | */ |
12 | ||
b4e1ded3 | 13 | #include <linux/compiler.h> |
0332db5a | 14 | #include <asm/assembler.h> |
1da177e4 LT |
15 | |
16 | #ifdef __KERNEL__ | |
17 | ||
18 | /* | |
19 | * switch_to(prev, next) should switch from task `prev' to `next' | |
20 | * `prev' will never be the same as `next'. | |
21 | * | |
36c8b586 | 22 | * `next' and `prev' should be struct task_struct, but it isn't always defined |
1da177e4 LT |
23 | */ |
24 | ||
43c09ce7 HT |
25 | #if defined(CONFIG_FRAME_POINTER) || \ |
26 | !defined(CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER) | |
27 | #define M32R_PUSH_FP " push fp\n" | |
28 | #define M32R_POP_FP " pop fp\n" | |
29 | #else | |
30 | #define M32R_PUSH_FP "" | |
31 | #define M32R_POP_FP "" | |
32 | #endif | |
33 | ||
1da177e4 | 34 | #define switch_to(prev, next, last) do { \ |
1da177e4 | 35 | __asm__ __volatile__ ( \ |
4127272c HT |
36 | " seth lr, #high(1f) \n" \ |
37 | " or3 lr, lr, #low(1f) \n" \ | |
38 | " st lr, @%4 ; store old LR \n" \ | |
39 | " ld lr, @%5 ; load new LR \n" \ | |
43c09ce7 | 40 | M32R_PUSH_FP \ |
4127272c HT |
41 | " st sp, @%2 ; store old SP \n" \ |
42 | " ld sp, @%3 ; load new SP \n" \ | |
43 | " push %1 ; store `prev' on new stack \n" \ | |
44 | " jmp lr \n" \ | |
45 | " .fillinsn \n" \ | |
46 | "1: \n" \ | |
47 | " pop %0 ; restore `__last' from new stack \n" \ | |
43c09ce7 | 48 | M32R_POP_FP \ |
4127272c HT |
49 | : "=r" (last) \ |
50 | : "0" (prev), \ | |
51 | "r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \ | |
52 | "r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \ | |
53 | : "memory", "lr" \ | |
1da177e4 | 54 | ); \ |
1da177e4 LT |
55 | } while(0) |
56 | ||
57 | /* Interrupt Control */ | |
9287d95e | 58 | #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) |
1da177e4 LT |
59 | #define local_irq_enable() \ |
60 | __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") | |
61 | #define local_irq_disable() \ | |
62 | __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") | |
9287d95e | 63 | #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ |
1da177e4 LT |
64 | static inline void local_irq_enable(void) |
65 | { | |
66 | unsigned long tmpreg; | |
67 | __asm__ __volatile__( | |
68 | "mvfc %0, psw; \n\t" | |
69 | "or3 %0, %0, #0x0040; \n\t" | |
70 | "mvtc %0, psw; \n\t" | |
71 | : "=&r" (tmpreg) : : "cbit", "memory"); | |
72 | } | |
73 | ||
74 | static inline void local_irq_disable(void) | |
75 | { | |
76 | unsigned long tmpreg0, tmpreg1; | |
77 | __asm__ __volatile__( | |
78 | "ld24 %0, #0 ; Use 32-bit insn. \n\t" | |
79 | "mvfc %1, psw ; No interrupt can be accepted here. \n\t" | |
80 | "mvtc %0, psw \n\t" | |
81 | "and3 %0, %1, #0xffbf \n\t" | |
82 | "mvtc %0, psw \n\t" | |
83 | : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); | |
84 | } | |
9287d95e | 85 | #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ |
1da177e4 LT |
86 | |
87 | #define local_save_flags(x) \ | |
88 | __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) | |
89 | ||
90 | #define local_irq_restore(x) \ | |
91 | __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ | |
92 | : "r" (x) : "cbit", "memory") | |
93 | ||
9287d95e | 94 | #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) |
1da177e4 LT |
95 | #define local_irq_save(x) \ |
96 | __asm__ __volatile__( \ | |
97 | "mvfc %0, psw; \n\t" \ | |
98 | "clrpsw #0x40 -> nop; \n\t" \ | |
99 | : "=r" (x) : /* no input */ : "memory") | |
9287d95e | 100 | #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ |
1da177e4 LT |
101 | #define local_irq_save(x) \ |
102 | ({ \ | |
103 | unsigned long tmpreg; \ | |
104 | __asm__ __volatile__( \ | |
105 | "ld24 %1, #0 \n\t" \ | |
106 | "mvfc %0, psw \n\t" \ | |
107 | "mvtc %1, psw \n\t" \ | |
108 | "and3 %1, %0, #0xffbf \n\t" \ | |
109 | "mvtc %1, psw \n\t" \ | |
110 | : "=r" (x), "=&r" (tmpreg) \ | |
111 | : : "cbit", "memory"); \ | |
112 | }) | |
9287d95e | 113 | #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ |
1da177e4 LT |
114 | |
115 | #define irqs_disabled() \ | |
116 | ({ \ | |
117 | unsigned long flags; \ | |
118 | local_save_flags(flags); \ | |
119 | !(flags & 0x40); \ | |
120 | }) | |
121 | ||
1da177e4 LT |
122 | #define nop() __asm__ __volatile__ ("nop" : : ) |
123 | ||
124 | #define xchg(ptr,x) \ | |
125 | ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | |
126 | ||
1da177e4 LT |
127 | #ifdef CONFIG_SMP |
128 | extern void __xchg_called_with_bad_pointer(void); | |
129 | #endif | |
130 | ||
131 | #ifdef CONFIG_CHIP_M32700_TS1 | |
132 | #define DCACHE_CLEAR(reg0, reg1, addr) \ | |
133 | "seth "reg1", #high(dcache_dummy); \n\t" \ | |
134 | "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \ | |
135 | "lock "reg0", @"reg1"; \n\t" \ | |
136 | "add3 "reg0", "addr", #0x1000; \n\t" \ | |
137 | "ld "reg0", @"reg0"; \n\t" \ | |
138 | "add3 "reg0", "addr", #0x2000; \n\t" \ | |
139 | "ld "reg0", @"reg0"; \n\t" \ | |
140 | "unlock "reg0", @"reg1"; \n\t" | |
beb7dd86 | 141 | /* FIXME: This workaround code cannot handle kernel modules |
1da177e4 LT |
142 | * correctly under SMP environment. |
143 | */ | |
144 | #else /* CONFIG_CHIP_M32700_TS1 */ | |
145 | #define DCACHE_CLEAR(reg0, reg1, addr) | |
146 | #endif /* CONFIG_CHIP_M32700_TS1 */ | |
147 | ||
b4e1ded3 | 148 | static __always_inline unsigned long |
4127272c | 149 | __xchg(unsigned long x, volatile void * ptr, int size) |
1da177e4 LT |
150 | { |
151 | unsigned long flags; | |
152 | unsigned long tmp = 0; | |
153 | ||
154 | local_irq_save(flags); | |
155 | ||
156 | switch (size) { | |
157 | #ifndef CONFIG_SMP | |
158 | case 1: | |
159 | __asm__ __volatile__ ( | |
160 | "ldb %0, @%2 \n\t" | |
161 | "stb %1, @%2 \n\t" | |
162 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); | |
163 | break; | |
164 | case 2: | |
165 | __asm__ __volatile__ ( | |
166 | "ldh %0, @%2 \n\t" | |
167 | "sth %1, @%2 \n\t" | |
168 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); | |
169 | break; | |
170 | case 4: | |
171 | __asm__ __volatile__ ( | |
172 | "ld %0, @%2 \n\t" | |
173 | "st %1, @%2 \n\t" | |
174 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); | |
175 | break; | |
176 | #else /* CONFIG_SMP */ | |
177 | case 4: | |
178 | __asm__ __volatile__ ( | |
179 | DCACHE_CLEAR("%0", "r4", "%2") | |
180 | "lock %0, @%2; \n\t" | |
181 | "unlock %1, @%2; \n\t" | |
182 | : "=&r" (tmp) : "r" (x), "r" (ptr) | |
183 | : "memory" | |
184 | #ifdef CONFIG_CHIP_M32700_TS1 | |
185 | , "r4" | |
186 | #endif /* CONFIG_CHIP_M32700_TS1 */ | |
187 | ); | |
188 | break; | |
189 | default: | |
190 | __xchg_called_with_bad_pointer(); | |
191 | #endif /* CONFIG_SMP */ | |
192 | } | |
193 | ||
194 | local_irq_restore(flags); | |
195 | ||
196 | return (tmp); | |
197 | } | |
198 | ||
0332db5a HT |
199 | #define __HAVE_ARCH_CMPXCHG 1 |
200 | ||
4127272c | 201 | static inline unsigned long |
0332db5a HT |
202 | __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) |
203 | { | |
204 | unsigned long flags; | |
205 | unsigned int retval; | |
206 | ||
207 | local_irq_save(flags); | |
208 | __asm__ __volatile__ ( | |
209 | DCACHE_CLEAR("%0", "r4", "%1") | |
210 | M32R_LOCK" %0, @%1; \n" | |
211 | " bne %0, %2, 1f; \n" | |
212 | M32R_UNLOCK" %3, @%1; \n" | |
213 | " bra 2f; \n" | |
214 | " .fillinsn \n" | |
215 | "1:" | |
b04ec261 | 216 | M32R_UNLOCK" %0, @%1; \n" |
0332db5a HT |
217 | " .fillinsn \n" |
218 | "2:" | |
219 | : "=&r" (retval) | |
220 | : "r" (p), "r" (old), "r" (new) | |
221 | : "cbit", "memory" | |
222 | #ifdef CONFIG_CHIP_M32700_TS1 | |
223 | , "r4" | |
224 | #endif /* CONFIG_CHIP_M32700_TS1 */ | |
225 | ); | |
226 | local_irq_restore(flags); | |
227 | ||
228 | return retval; | |
229 | } | |
230 | ||
231 | /* This function doesn't exist, so you'll get a linker error | |
232 | if something tries to do an invalid cmpxchg(). */ | |
233 | extern void __cmpxchg_called_with_bad_pointer(void); | |
234 | ||
4127272c | 235 | static inline unsigned long |
0332db5a HT |
236 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) |
237 | { | |
238 | switch (size) { | |
239 | case 4: | |
240 | return __cmpxchg_u32(ptr, old, new); | |
241 | #if 0 /* we don't have __cmpxchg_u64 */ | |
242 | case 8: | |
243 | return __cmpxchg_u64(ptr, old, new); | |
244 | #endif /* 0 */ | |
245 | } | |
246 | __cmpxchg_called_with_bad_pointer(); | |
247 | return old; | |
248 | } | |
249 | ||
250 | #define cmpxchg(ptr,o,n) \ | |
251 | ({ \ | |
252 | __typeof__(*(ptr)) _o_ = (o); \ | |
253 | __typeof__(*(ptr)) _n_ = (n); \ | |
254 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
255 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
256 | }) | |
257 | ||
258 | #endif /* __KERNEL__ */ | |
259 | ||
1da177e4 LT |
260 | /* |
261 | * Memory barrier. | |
262 | * | |
263 | * mb() prevents loads and stores being reordered across this point. | |
264 | * rmb() prevents loads being reordered across this point. | |
265 | * wmb() prevents stores being reordered across this point. | |
266 | */ | |
267 | #define mb() barrier() | |
268 | #define rmb() mb() | |
269 | #define wmb() mb() | |
270 | ||
271 | /** | |
272 | * read_barrier_depends - Flush all pending reads that subsequents reads | |
273 | * depend on. | |
274 | * | |
275 | * No data-dependent reads from memory-like regions are ever reordered | |
276 | * over this barrier. All reads preceding this primitive are guaranteed | |
277 | * to access memory (but not necessarily other CPUs' caches) before any | |
278 | * reads following this primitive that depend on the data return by | |
279 | * any of the preceding reads. This primitive is much lighter weight than | |
280 | * rmb() on most CPUs, and is never heavier weight than is | |
281 | * rmb(). | |
282 | * | |
283 | * These ordering constraints are respected by both the local CPU | |
284 | * and the compiler. | |
285 | * | |
286 | * Ordering is not guaranteed by anything other than these primitives, | |
287 | * not even by data dependencies. See the documentation for | |
288 | * memory_barrier() for examples and URLs to more information. | |
289 | * | |
290 | * For example, the following code would force ordering (the initial | |
291 | * value of "a" is zero, "b" is one, and "p" is "&a"): | |
292 | * | |
293 | * <programlisting> | |
294 | * CPU 0 CPU 1 | |
295 | * | |
296 | * b = 2; | |
297 | * memory_barrier(); | |
298 | * p = &b; q = p; | |
299 | * read_barrier_depends(); | |
300 | * d = *q; | |
301 | * </programlisting> | |
302 | * | |
303 | * | |
304 | * because the read of "*q" depends on the read of "p" and these | |
305 | * two reads are separated by a read_barrier_depends(). However, | |
306 | * the following code, with the same initial values for "a" and "b": | |
307 | * | |
308 | * <programlisting> | |
309 | * CPU 0 CPU 1 | |
310 | * | |
311 | * a = 2; | |
312 | * memory_barrier(); | |
313 | * b = 3; y = b; | |
314 | * read_barrier_depends(); | |
315 | * x = a; | |
316 | * </programlisting> | |
317 | * | |
318 | * does not enforce ordering, since there is no data dependency between | |
319 | * the read of "a" and the read of "b". Therefore, on some CPUs, such | |
320 | * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() | |
d6e05edc | 321 | * in cases like this where there are no data dependencies. |
1da177e4 LT |
322 | **/ |
323 | ||
324 | #define read_barrier_depends() do { } while (0) | |
325 | ||
326 | #ifdef CONFIG_SMP | |
327 | #define smp_mb() mb() | |
328 | #define smp_rmb() rmb() | |
329 | #define smp_wmb() wmb() | |
330 | #define smp_read_barrier_depends() read_barrier_depends() | |
a27f3113 | 331 | #define set_mb(var, value) do { (void) xchg(&var, value); } while (0) |
1da177e4 LT |
332 | #else |
333 | #define smp_mb() barrier() | |
334 | #define smp_rmb() barrier() | |
335 | #define smp_wmb() barrier() | |
336 | #define smp_read_barrier_depends() do { } while (0) | |
a27f3113 | 337 | #define set_mb(var, value) do { var = value; barrier(); } while (0) |
1da177e4 LT |
338 | #endif |
339 | ||
1da177e4 LT |
340 | #define arch_align_stack(x) (x) |
341 | ||
fabb626a | 342 | #endif /* _ASM_M32R_SYSTEM_H */ |