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1 | #ifndef _ASM_M32R_M32R_H_ |
2 | #define _ASM_M32R_M32R_H_ | |
3 | ||
4 | /* | |
5 | * Renesas M32R processor | |
6 | * | |
7 | * Copyright (C) 2003, 2004 Renesas Technology Corp. | |
8 | */ | |
9 | ||
10 | #include <linux/config.h> | |
11 | ||
12 | /* Chip type */ | |
13 | #if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP) | |
14 | #include <asm/m32r_mp_fpga.h> | |
15 | #elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ | |
16 | || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ | |
17 | || defined(CONFIG_CHIP_OPSP) | |
18 | #include <asm/m32102.h> | |
1da177e4 LT |
19 | #endif |
20 | ||
21 | /* Platform type */ | |
22 | #if defined(CONFIG_PLAT_M32700UT) | |
23 | #include <asm/m32700ut/m32700ut_pld.h> | |
24 | #include <asm/m32700ut/m32700ut_lan.h> | |
25 | #include <asm/m32700ut/m32700ut_lcd.h> | |
26 | #endif /* CONFIG_PLAT_M32700UT */ | |
27 | ||
28 | #if defined(CONFIG_PLAT_OPSPUT) | |
29 | #include <asm/opsput/opsput_pld.h> | |
30 | #include <asm/opsput/opsput_lan.h> | |
31 | #include <asm/opsput/opsput_lcd.h> | |
32 | #endif /* CONFIG_PLAT_OPSPUT */ | |
33 | ||
34 | #if defined(CONFIG_PLAT_MAPPI2) | |
35 | #include <asm/mappi2/mappi2_pld.h> | |
36 | #endif /* CONFIG_PLAT_MAPPI2 */ | |
37 | ||
23680863 HT |
38 | #if defined(CONFIG_PLAT_MAPPI3) |
39 | #include <asm/mappi3/mappi3_pld.h> | |
40 | #endif /* CONFIG_PLAT_MAPPI3 */ | |
41 | ||
1da177e4 LT |
42 | #if defined(CONFIG_PLAT_USRV) |
43 | #include <asm/m32700ut/m32700ut_pld.h> | |
44 | #endif | |
45 | ||
46 | /* | |
47 | * M32R Register | |
48 | */ | |
49 | ||
50 | /* | |
51 | * MMU Register | |
52 | */ | |
53 | ||
54 | #define MMU_REG_BASE (0xffff0000) | |
55 | #define ITLB_BASE (0xfe000000) | |
56 | #define DTLB_BASE (0xfe000800) | |
57 | ||
58 | #define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES | |
59 | ||
60 | #define MATM MMU_REG_BASE /* MMU Address Translation Mode | |
61 | Register */ | |
62 | #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */ | |
63 | #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */ | |
64 | #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */ | |
65 | #define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual | |
66 | Address Register */ | |
67 | #define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page | |
68 | Number Register */ | |
69 | #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */ | |
70 | #define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address | |
71 | Register */ | |
72 | #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */ | |
73 | #define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for | |
74 | Instruciton */ | |
75 | #define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */ | |
76 | ||
77 | #define MATM_offset (MATM - MMU_REG_BASE) | |
78 | #define MPSZ_offset (MPSZ - MMU_REG_BASE) | |
79 | #define MASID_offset (MASID - MMU_REG_BASE) | |
80 | #define MESTS_offset (MESTS - MMU_REG_BASE) | |
81 | #define MDEVA_offset (MDEVA - MMU_REG_BASE) | |
82 | #define MDEVP_offset (MDEVP - MMU_REG_BASE) | |
83 | #define MPTB_offset (MPTB - MMU_REG_BASE) | |
84 | #define MSVA_offset (MSVA - MMU_REG_BASE) | |
85 | #define MTOP_offset (MTOP - MMU_REG_BASE) | |
86 | #define MIDXI_offset (MIDXI - MMU_REG_BASE) | |
87 | #define MIDXD_offset (MIDXD - MMU_REG_BASE) | |
88 | ||
89 | #define MESTS_IT (1 << 0) /* Instruction TLB miss */ | |
90 | #define MESTS_IA (1 << 1) /* Instruction Access Exception */ | |
91 | #define MESTS_DT (1 << 4) /* Operand TLB miss */ | |
92 | #define MESTS_DA (1 << 5) /* Operand Access Exception */ | |
93 | #define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */ | |
94 | ||
95 | /* | |
96 | * PSW (Processor Status Word) | |
97 | */ | |
98 | ||
99 | /* PSW bit */ | |
100 | #define M32R_PSW_BIT_SM (7) /* Stack Mode */ | |
101 | #define M32R_PSW_BIT_IE (6) /* Interrupt Enable */ | |
102 | #define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */ | |
103 | #define M32R_PSW_BIT_C (0) /* Condition */ | |
104 | #define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */ | |
105 | #define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */ | |
106 | #define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */ | |
107 | #define M32R_PSW_BIT_BC (0+8) /* Backup Condition */ | |
108 | ||
109 | /* PSW bit map */ | |
110 | #define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */ | |
111 | #define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */ | |
112 | #define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */ | |
113 | #define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */ | |
114 | #define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */ | |
115 | #define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */ | |
116 | #define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */ | |
117 | #define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */ | |
118 | ||
119 | /* | |
120 | * Direct address to SFR | |
121 | */ | |
122 | ||
123 | #include <asm/page.h> | |
124 | #ifdef CONFIG_MMU | |
125 | #define NONCACHE_OFFSET __PAGE_OFFSET+0x20000000 | |
126 | #else | |
127 | #define NONCACHE_OFFSET __PAGE_OFFSET | |
128 | #endif /* CONFIG_MMU */ | |
129 | ||
130 | #define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET | |
131 | #define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET | |
132 | #define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET | |
133 | #define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET | |
134 | #define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET | |
135 | #define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET | |
136 | ||
137 | #endif /* _ASM_M32R_M32R_H_ */ |