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7868f1ed JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV MMR definitions | |
7 | * | |
8 | * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_IA64_UV_MMRS__ | |
12 | #define __ASM_IA64_UV_MMRS__ | |
13 | ||
8cac39b9 DS |
14 | #define UV_MMR_ENABLE (1UL << 63) |
15 | ||
16 | /* ========================================================================= */ | |
17 | /* UVH_BAU_DATA_CONFIG */ | |
18 | /* ========================================================================= */ | |
19 | #define UVH_BAU_DATA_CONFIG 0x61680UL | |
20 | #define UVH_BAU_DATA_CONFIG_32 0x0438 | |
21 | ||
22 | #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 | |
23 | #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
24 | #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 | |
25 | #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | |
26 | #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | |
27 | #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
28 | #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 | |
29 | #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | |
30 | #define UVH_BAU_DATA_CONFIG_P_SHFT 13 | |
31 | #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | |
32 | #define UVH_BAU_DATA_CONFIG_T_SHFT 15 | |
33 | #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | |
34 | #define UVH_BAU_DATA_CONFIG_M_SHFT 16 | |
35 | #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | |
36 | #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | |
37 | #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
38 | ||
39 | union uvh_bau_data_config_u { | |
40 | unsigned long v; | |
41 | struct uvh_bau_data_config_s { | |
42 | unsigned long vector_ : 8; /* RW */ | |
43 | unsigned long dm : 3; /* RW */ | |
44 | unsigned long destmode : 1; /* RW */ | |
45 | unsigned long status : 1; /* RO */ | |
46 | unsigned long p : 1; /* RO */ | |
47 | unsigned long rsvd_14 : 1; /* */ | |
48 | unsigned long t : 1; /* RO */ | |
49 | unsigned long m : 1; /* RW */ | |
50 | unsigned long rsvd_17_31: 15; /* */ | |
51 | unsigned long apic_id : 32; /* RW */ | |
52 | } s; | |
53 | }; | |
54 | ||
55 | /* ========================================================================= */ | |
56 | /* UVH_EVENT_OCCURRED0 */ | |
57 | /* ========================================================================= */ | |
58 | #define UVH_EVENT_OCCURRED0 0x70000UL | |
59 | #define UVH_EVENT_OCCURRED0_32 0x005e8 | |
60 | ||
61 | #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | |
62 | #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL | |
63 | #define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 | |
64 | #define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL | |
65 | #define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 | |
66 | #define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL | |
67 | #define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3 | |
68 | #define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL | |
69 | #define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4 | |
70 | #define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL | |
71 | #define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5 | |
72 | #define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL | |
73 | #define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6 | |
74 | #define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL | |
75 | #define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 | |
76 | #define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL | |
77 | #define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 | |
78 | #define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL | |
79 | #define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 | |
80 | #define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL | |
81 | #define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 | |
82 | #define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL | |
83 | #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 | |
84 | #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL | |
85 | #define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 | |
86 | #define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL | |
87 | #define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 | |
88 | #define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL | |
89 | #define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 | |
90 | #define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL | |
91 | #define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 | |
92 | #define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL | |
93 | #define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 | |
94 | #define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL | |
95 | #define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 | |
96 | #define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL | |
97 | #define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 | |
98 | #define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL | |
99 | #define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 | |
100 | #define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL | |
101 | #define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 | |
102 | #define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL | |
103 | #define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 | |
104 | #define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL | |
105 | #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 | |
106 | #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL | |
107 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 | |
108 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL | |
109 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 | |
110 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL | |
111 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 | |
112 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL | |
113 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 | |
114 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL | |
115 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 | |
116 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL | |
117 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 | |
118 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL | |
119 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 | |
120 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL | |
121 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 | |
122 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL | |
123 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 | |
124 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL | |
125 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 | |
126 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL | |
127 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 | |
128 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL | |
129 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 | |
130 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL | |
131 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 | |
132 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL | |
133 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 | |
134 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL | |
135 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 | |
136 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL | |
137 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 | |
138 | #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL | |
139 | #define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 | |
140 | #define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL | |
141 | #define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 | |
142 | #define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL | |
143 | #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 | |
144 | #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL | |
145 | #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 | |
146 | #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL | |
147 | #define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43 | |
148 | #define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL | |
149 | #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 | |
150 | #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL | |
151 | #define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45 | |
152 | #define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL | |
153 | #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 | |
154 | #define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL | |
155 | #define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 | |
156 | #define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL | |
157 | #define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 | |
158 | #define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL | |
159 | #define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 | |
160 | #define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL | |
161 | #define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 | |
162 | #define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL | |
163 | #define UVH_EVENT_OCCURRED0_RTC0_SHFT 51 | |
164 | #define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL | |
165 | #define UVH_EVENT_OCCURRED0_RTC1_SHFT 52 | |
166 | #define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL | |
167 | #define UVH_EVENT_OCCURRED0_RTC2_SHFT 53 | |
168 | #define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL | |
169 | #define UVH_EVENT_OCCURRED0_RTC3_SHFT 54 | |
170 | #define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL | |
171 | #define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55 | |
172 | #define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL | |
173 | #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 | |
174 | #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL | |
175 | union uvh_event_occurred0_u { | |
176 | unsigned long v; | |
177 | struct uvh_event_occurred0_s { | |
178 | unsigned long lb_hcerr : 1; /* RW, W1C */ | |
179 | unsigned long gr0_hcerr : 1; /* RW, W1C */ | |
180 | unsigned long gr1_hcerr : 1; /* RW, W1C */ | |
181 | unsigned long lh_hcerr : 1; /* RW, W1C */ | |
182 | unsigned long rh_hcerr : 1; /* RW, W1C */ | |
183 | unsigned long xn_hcerr : 1; /* RW, W1C */ | |
184 | unsigned long si_hcerr : 1; /* RW, W1C */ | |
185 | unsigned long lb_aoerr0 : 1; /* RW, W1C */ | |
186 | unsigned long gr0_aoerr0 : 1; /* RW, W1C */ | |
187 | unsigned long gr1_aoerr0 : 1; /* RW, W1C */ | |
188 | unsigned long lh_aoerr0 : 1; /* RW, W1C */ | |
189 | unsigned long rh_aoerr0 : 1; /* RW, W1C */ | |
190 | unsigned long xn_aoerr0 : 1; /* RW, W1C */ | |
191 | unsigned long si_aoerr0 : 1; /* RW, W1C */ | |
192 | unsigned long lb_aoerr1 : 1; /* RW, W1C */ | |
193 | unsigned long gr0_aoerr1 : 1; /* RW, W1C */ | |
194 | unsigned long gr1_aoerr1 : 1; /* RW, W1C */ | |
195 | unsigned long lh_aoerr1 : 1; /* RW, W1C */ | |
196 | unsigned long rh_aoerr1 : 1; /* RW, W1C */ | |
197 | unsigned long xn_aoerr1 : 1; /* RW, W1C */ | |
198 | unsigned long si_aoerr1 : 1; /* RW, W1C */ | |
199 | unsigned long rh_vpi_int : 1; /* RW, W1C */ | |
200 | unsigned long system_shutdown_int : 1; /* RW, W1C */ | |
201 | unsigned long lb_irq_int_0 : 1; /* RW, W1C */ | |
202 | unsigned long lb_irq_int_1 : 1; /* RW, W1C */ | |
203 | unsigned long lb_irq_int_2 : 1; /* RW, W1C */ | |
204 | unsigned long lb_irq_int_3 : 1; /* RW, W1C */ | |
205 | unsigned long lb_irq_int_4 : 1; /* RW, W1C */ | |
206 | unsigned long lb_irq_int_5 : 1; /* RW, W1C */ | |
207 | unsigned long lb_irq_int_6 : 1; /* RW, W1C */ | |
208 | unsigned long lb_irq_int_7 : 1; /* RW, W1C */ | |
209 | unsigned long lb_irq_int_8 : 1; /* RW, W1C */ | |
210 | unsigned long lb_irq_int_9 : 1; /* RW, W1C */ | |
211 | unsigned long lb_irq_int_10 : 1; /* RW, W1C */ | |
212 | unsigned long lb_irq_int_11 : 1; /* RW, W1C */ | |
213 | unsigned long lb_irq_int_12 : 1; /* RW, W1C */ | |
214 | unsigned long lb_irq_int_13 : 1; /* RW, W1C */ | |
215 | unsigned long lb_irq_int_14 : 1; /* RW, W1C */ | |
216 | unsigned long lb_irq_int_15 : 1; /* RW, W1C */ | |
217 | unsigned long l1_nmi_int : 1; /* RW, W1C */ | |
218 | unsigned long stop_clock : 1; /* RW, W1C */ | |
219 | unsigned long asic_to_l1 : 1; /* RW, W1C */ | |
220 | unsigned long l1_to_asic : 1; /* RW, W1C */ | |
221 | unsigned long ltc_int : 1; /* RW, W1C */ | |
222 | unsigned long la_seq_trigger : 1; /* RW, W1C */ | |
223 | unsigned long ipi_int : 1; /* RW, W1C */ | |
224 | unsigned long extio_int0 : 1; /* RW, W1C */ | |
225 | unsigned long extio_int1 : 1; /* RW, W1C */ | |
226 | unsigned long extio_int2 : 1; /* RW, W1C */ | |
227 | unsigned long extio_int3 : 1; /* RW, W1C */ | |
228 | unsigned long profile_int : 1; /* RW, W1C */ | |
229 | unsigned long rtc0 : 1; /* RW, W1C */ | |
230 | unsigned long rtc1 : 1; /* RW, W1C */ | |
231 | unsigned long rtc2 : 1; /* RW, W1C */ | |
232 | unsigned long rtc3 : 1; /* RW, W1C */ | |
233 | unsigned long bau_data : 1; /* RW, W1C */ | |
234 | unsigned long power_management_req : 1; /* RW, W1C */ | |
235 | unsigned long rsvd_57_63 : 7; /* */ | |
236 | } s; | |
237 | }; | |
238 | ||
239 | /* ========================================================================= */ | |
240 | /* UVH_EVENT_OCCURRED0_ALIAS */ | |
241 | /* ========================================================================= */ | |
242 | #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL | |
243 | #define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0 | |
244 | ||
245 | /* ========================================================================= */ | |
246 | /* UVH_INT_CMPB */ | |
247 | /* ========================================================================= */ | |
248 | #define UVH_INT_CMPB 0x22080UL | |
249 | ||
250 | #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 | |
251 | #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | |
7868f1ed | 252 | |
8cac39b9 DS |
253 | union uvh_int_cmpb_u { |
254 | unsigned long v; | |
255 | struct uvh_int_cmpb_s { | |
256 | unsigned long real_time_cmpb : 56; /* RW */ | |
257 | unsigned long rsvd_56_63 : 8; /* */ | |
258 | } s; | |
259 | }; | |
260 | ||
261 | /* ========================================================================= */ | |
262 | /* UVH_INT_CMPC */ | |
263 | /* ========================================================================= */ | |
264 | #define UVH_INT_CMPC 0x22100UL | |
265 | ||
266 | #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 | |
267 | #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL | |
268 | ||
269 | union uvh_int_cmpc_u { | |
270 | unsigned long v; | |
271 | struct uvh_int_cmpc_s { | |
272 | unsigned long real_time_cmpc : 56; /* RW */ | |
273 | unsigned long rsvd_56_63 : 8; /* */ | |
274 | } s; | |
275 | }; | |
276 | ||
277 | /* ========================================================================= */ | |
278 | /* UVH_INT_CMPD */ | |
279 | /* ========================================================================= */ | |
280 | #define UVH_INT_CMPD 0x22180UL | |
281 | ||
282 | #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 | |
283 | #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL | |
284 | ||
285 | union uvh_int_cmpd_u { | |
286 | unsigned long v; | |
287 | struct uvh_int_cmpd_s { | |
288 | unsigned long real_time_cmpd : 56; /* RW */ | |
289 | unsigned long rsvd_56_63 : 8; /* */ | |
290 | } s; | |
291 | }; | |
7868f1ed JS |
292 | |
293 | /* ========================================================================= */ | |
294 | /* UVH_NODE_ID */ | |
295 | /* ========================================================================= */ | |
296 | #define UVH_NODE_ID 0x0UL | |
297 | ||
298 | #define UVH_NODE_ID_FORCE1_SHFT 0 | |
299 | #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL | |
300 | #define UVH_NODE_ID_MANUFACTURER_SHFT 1 | |
301 | #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL | |
302 | #define UVH_NODE_ID_PART_NUMBER_SHFT 12 | |
303 | #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL | |
304 | #define UVH_NODE_ID_REVISION_SHFT 28 | |
305 | #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL | |
306 | #define UVH_NODE_ID_NODE_ID_SHFT 32 | |
307 | #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL | |
308 | #define UVH_NODE_ID_NODES_PER_BIT_SHFT 48 | |
309 | #define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL | |
310 | #define UVH_NODE_ID_NI_PORT_SHFT 56 | |
311 | #define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL | |
312 | ||
313 | union uvh_node_id_u { | |
314 | unsigned long v; | |
315 | struct uvh_node_id_s { | |
316 | unsigned long force1 : 1; /* RO */ | |
317 | unsigned long manufacturer : 11; /* RO */ | |
318 | unsigned long part_number : 16; /* RO */ | |
319 | unsigned long revision : 4; /* RO */ | |
320 | unsigned long node_id : 15; /* RW */ | |
321 | unsigned long rsvd_47 : 1; /* */ | |
322 | unsigned long nodes_per_bit : 7; /* RW */ | |
323 | unsigned long rsvd_55 : 1; /* */ | |
324 | unsigned long ni_port : 4; /* RO */ | |
325 | unsigned long rsvd_60_63 : 4; /* */ | |
326 | } s; | |
327 | }; | |
328 | ||
329 | /* ========================================================================= */ | |
330 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ | |
331 | /* ========================================================================= */ | |
332 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL | |
333 | ||
334 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | |
335 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
336 | ||
337 | union uvh_rh_gam_alias210_redirect_config_0_mmr_u { | |
338 | unsigned long v; | |
339 | struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { | |
340 | unsigned long rsvd_0_23 : 24; /* */ | |
341 | unsigned long dest_base : 22; /* RW */ | |
342 | unsigned long rsvd_46_63: 18; /* */ | |
343 | } s; | |
344 | }; | |
345 | ||
346 | /* ========================================================================= */ | |
347 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ | |
348 | /* ========================================================================= */ | |
349 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL | |
350 | ||
351 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | |
352 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
353 | ||
354 | union uvh_rh_gam_alias210_redirect_config_1_mmr_u { | |
355 | unsigned long v; | |
356 | struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { | |
357 | unsigned long rsvd_0_23 : 24; /* */ | |
358 | unsigned long dest_base : 22; /* RW */ | |
359 | unsigned long rsvd_46_63: 18; /* */ | |
360 | } s; | |
361 | }; | |
362 | ||
363 | /* ========================================================================= */ | |
364 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ | |
365 | /* ========================================================================= */ | |
366 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL | |
367 | ||
368 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | |
369 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
370 | ||
371 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u { | |
372 | unsigned long v; | |
373 | struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { | |
374 | unsigned long rsvd_0_23 : 24; /* */ | |
375 | unsigned long dest_base : 22; /* RW */ | |
376 | unsigned long rsvd_46_63: 18; /* */ | |
377 | } s; | |
378 | }; | |
379 | ||
380 | /* ========================================================================= */ | |
381 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ | |
382 | /* ========================================================================= */ | |
383 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL | |
384 | ||
385 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 | |
386 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | |
8cac39b9 DS |
387 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 |
388 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL | |
7868f1ed JS |
389 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 |
390 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | |
391 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | |
392 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | |
393 | ||
394 | union uvh_rh_gam_gru_overlay_config_mmr_u { | |
395 | unsigned long v; | |
396 | struct uvh_rh_gam_gru_overlay_config_mmr_s { | |
397 | unsigned long rsvd_0_27: 28; /* */ | |
398 | unsigned long base : 18; /* RW */ | |
8cac39b9 | 399 | unsigned long rsvd_46_47: 2; /* */ |
7868f1ed | 400 | unsigned long gr4 : 1; /* RW */ |
8cac39b9 | 401 | unsigned long rsvd_49_51: 3; /* */ |
7868f1ed JS |
402 | unsigned long n_gru : 4; /* RW */ |
403 | unsigned long rsvd_56_62: 7; /* */ | |
404 | unsigned long enable : 1; /* RW */ | |
405 | } s; | |
406 | }; | |
407 | ||
408 | /* ========================================================================= */ | |
409 | /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ | |
410 | /* ========================================================================= */ | |
411 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL | |
412 | ||
413 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 | |
414 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | |
415 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 | |
416 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL | |
417 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | |
418 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | |
419 | ||
420 | union uvh_rh_gam_mmr_overlay_config_mmr_u { | |
421 | unsigned long v; | |
422 | struct uvh_rh_gam_mmr_overlay_config_mmr_s { | |
423 | unsigned long rsvd_0_25: 26; /* */ | |
424 | unsigned long base : 20; /* RW */ | |
425 | unsigned long dual_hub : 1; /* RW */ | |
426 | unsigned long rsvd_47_62: 16; /* */ | |
427 | unsigned long enable : 1; /* RW */ | |
428 | } s; | |
429 | }; | |
430 | ||
431 | /* ========================================================================= */ | |
432 | /* UVH_RTC */ | |
433 | /* ========================================================================= */ | |
8cac39b9 | 434 | #define UVH_RTC 0x340000UL |
7868f1ed JS |
435 | |
436 | #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 | |
437 | #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | |
438 | ||
439 | union uvh_rtc_u { | |
440 | unsigned long v; | |
441 | struct uvh_rtc_s { | |
442 | unsigned long real_time_clock : 56; /* RW */ | |
443 | unsigned long rsvd_56_63 : 8; /* */ | |
444 | } s; | |
445 | }; | |
446 | ||
8cac39b9 DS |
447 | /* ========================================================================= */ |
448 | /* UVH_RTC1_INT_CONFIG */ | |
449 | /* ========================================================================= */ | |
450 | #define UVH_RTC1_INT_CONFIG 0x615c0UL | |
451 | ||
452 | #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 | |
453 | #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
454 | #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 | |
455 | #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL | |
456 | #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 | |
457 | #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
458 | #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 | |
459 | #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | |
460 | #define UVH_RTC1_INT_CONFIG_P_SHFT 13 | |
461 | #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL | |
462 | #define UVH_RTC1_INT_CONFIG_T_SHFT 15 | |
463 | #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL | |
464 | #define UVH_RTC1_INT_CONFIG_M_SHFT 16 | |
465 | #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | |
466 | #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 | |
467 | #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
468 | ||
469 | union uvh_rtc1_int_config_u { | |
470 | unsigned long v; | |
471 | struct uvh_rtc1_int_config_s { | |
472 | unsigned long vector_ : 8; /* RW */ | |
473 | unsigned long dm : 3; /* RW */ | |
474 | unsigned long destmode : 1; /* RW */ | |
475 | unsigned long status : 1; /* RO */ | |
476 | unsigned long p : 1; /* RO */ | |
477 | unsigned long rsvd_14 : 1; /* */ | |
478 | unsigned long t : 1; /* RO */ | |
479 | unsigned long m : 1; /* RW */ | |
480 | unsigned long rsvd_17_31: 15; /* */ | |
481 | unsigned long apic_id : 32; /* RW */ | |
482 | } s; | |
483 | }; | |
484 | ||
485 | /* ========================================================================= */ | |
486 | /* UVH_RTC2_INT_CONFIG */ | |
487 | /* ========================================================================= */ | |
488 | #define UVH_RTC2_INT_CONFIG 0x61600UL | |
489 | ||
490 | #define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0 | |
491 | #define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
492 | #define UVH_RTC2_INT_CONFIG_DM_SHFT 8 | |
493 | #define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL | |
494 | #define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11 | |
495 | #define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
496 | #define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12 | |
497 | #define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | |
498 | #define UVH_RTC2_INT_CONFIG_P_SHFT 13 | |
499 | #define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL | |
500 | #define UVH_RTC2_INT_CONFIG_T_SHFT 15 | |
501 | #define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL | |
502 | #define UVH_RTC2_INT_CONFIG_M_SHFT 16 | |
503 | #define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL | |
504 | #define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32 | |
505 | #define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
506 | ||
507 | union uvh_rtc2_int_config_u { | |
508 | unsigned long v; | |
509 | struct uvh_rtc2_int_config_s { | |
510 | unsigned long vector_ : 8; /* RW */ | |
511 | unsigned long dm : 3; /* RW */ | |
512 | unsigned long destmode : 1; /* RW */ | |
513 | unsigned long status : 1; /* RO */ | |
514 | unsigned long p : 1; /* RO */ | |
515 | unsigned long rsvd_14 : 1; /* */ | |
516 | unsigned long t : 1; /* RO */ | |
517 | unsigned long m : 1; /* RW */ | |
518 | unsigned long rsvd_17_31: 15; /* */ | |
519 | unsigned long apic_id : 32; /* RW */ | |
520 | } s; | |
521 | }; | |
522 | ||
523 | /* ========================================================================= */ | |
524 | /* UVH_RTC3_INT_CONFIG */ | |
525 | /* ========================================================================= */ | |
526 | #define UVH_RTC3_INT_CONFIG 0x61640UL | |
527 | ||
528 | #define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0 | |
529 | #define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
530 | #define UVH_RTC3_INT_CONFIG_DM_SHFT 8 | |
531 | #define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL | |
532 | #define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11 | |
533 | #define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
534 | #define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12 | |
535 | #define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | |
536 | #define UVH_RTC3_INT_CONFIG_P_SHFT 13 | |
537 | #define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL | |
538 | #define UVH_RTC3_INT_CONFIG_T_SHFT 15 | |
539 | #define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL | |
540 | #define UVH_RTC3_INT_CONFIG_M_SHFT 16 | |
541 | #define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL | |
542 | #define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32 | |
543 | #define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
544 | ||
545 | union uvh_rtc3_int_config_u { | |
546 | unsigned long v; | |
547 | struct uvh_rtc3_int_config_s { | |
548 | unsigned long vector_ : 8; /* RW */ | |
549 | unsigned long dm : 3; /* RW */ | |
550 | unsigned long destmode : 1; /* RW */ | |
551 | unsigned long status : 1; /* RO */ | |
552 | unsigned long p : 1; /* RO */ | |
553 | unsigned long rsvd_14 : 1; /* */ | |
554 | unsigned long t : 1; /* RO */ | |
555 | unsigned long m : 1; /* RW */ | |
556 | unsigned long rsvd_17_31: 15; /* */ | |
557 | unsigned long apic_id : 32; /* RW */ | |
558 | } s; | |
559 | }; | |
560 | ||
561 | /* ========================================================================= */ | |
562 | /* UVH_RTC_INC_RATIO */ | |
563 | /* ========================================================================= */ | |
564 | #define UVH_RTC_INC_RATIO 0x350000UL | |
565 | ||
566 | #define UVH_RTC_INC_RATIO_FRACTION_SHFT 0 | |
567 | #define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL | |
568 | #define UVH_RTC_INC_RATIO_RATIO_SHFT 20 | |
569 | #define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL | |
570 | ||
571 | union uvh_rtc_inc_ratio_u { | |
572 | unsigned long v; | |
573 | struct uvh_rtc_inc_ratio_s { | |
574 | unsigned long fraction : 20; /* RW */ | |
575 | unsigned long ratio : 3; /* RW */ | |
576 | unsigned long rsvd_23_63: 41; /* */ | |
577 | } s; | |
578 | }; | |
579 | ||
7868f1ed JS |
580 | /* ========================================================================= */ |
581 | /* UVH_SI_ADDR_MAP_CONFIG */ | |
582 | /* ========================================================================= */ | |
583 | #define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL | |
584 | ||
585 | #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0 | |
586 | #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL | |
587 | #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8 | |
588 | #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL | |
589 | ||
590 | union uvh_si_addr_map_config_u { | |
591 | unsigned long v; | |
592 | struct uvh_si_addr_map_config_s { | |
593 | unsigned long m_skt : 6; /* RW */ | |
594 | unsigned long rsvd_6_7: 2; /* */ | |
595 | unsigned long n_skt : 4; /* RW */ | |
596 | unsigned long rsvd_12_63: 52; /* */ | |
597 | } s; | |
598 | }; | |
599 | ||
600 | /* ========================================================================= */ | |
601 | /* UVH_SI_ALIAS0_OVERLAY_CONFIG */ | |
602 | /* ========================================================================= */ | |
603 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL | |
604 | ||
605 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24 | |
606 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | |
607 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | |
608 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | |
609 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63 | |
610 | #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | |
611 | ||
612 | union uvh_si_alias0_overlay_config_u { | |
613 | unsigned long v; | |
614 | struct uvh_si_alias0_overlay_config_s { | |
615 | unsigned long rsvd_0_23: 24; /* */ | |
616 | unsigned long base : 8; /* RW */ | |
617 | unsigned long rsvd_32_47: 16; /* */ | |
618 | unsigned long m_alias : 5; /* RW */ | |
619 | unsigned long rsvd_53_62: 10; /* */ | |
620 | unsigned long enable : 1; /* RW */ | |
621 | } s; | |
622 | }; | |
623 | ||
624 | /* ========================================================================= */ | |
625 | /* UVH_SI_ALIAS1_OVERLAY_CONFIG */ | |
626 | /* ========================================================================= */ | |
627 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL | |
628 | ||
629 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24 | |
630 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | |
631 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | |
632 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | |
633 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63 | |
634 | #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | |
635 | ||
636 | union uvh_si_alias1_overlay_config_u { | |
637 | unsigned long v; | |
638 | struct uvh_si_alias1_overlay_config_s { | |
639 | unsigned long rsvd_0_23: 24; /* */ | |
640 | unsigned long base : 8; /* RW */ | |
641 | unsigned long rsvd_32_47: 16; /* */ | |
642 | unsigned long m_alias : 5; /* RW */ | |
643 | unsigned long rsvd_53_62: 10; /* */ | |
644 | unsigned long enable : 1; /* RW */ | |
645 | } s; | |
646 | }; | |
647 | ||
648 | /* ========================================================================= */ | |
649 | /* UVH_SI_ALIAS2_OVERLAY_CONFIG */ | |
650 | /* ========================================================================= */ | |
651 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL | |
652 | ||
653 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24 | |
654 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL | |
655 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48 | |
656 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL | |
657 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63 | |
658 | #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL | |
659 | ||
660 | union uvh_si_alias2_overlay_config_u { | |
661 | unsigned long v; | |
662 | struct uvh_si_alias2_overlay_config_s { | |
663 | unsigned long rsvd_0_23: 24; /* */ | |
664 | unsigned long base : 8; /* RW */ | |
665 | unsigned long rsvd_32_47: 16; /* */ | |
666 | unsigned long m_alias : 5; /* RW */ | |
667 | unsigned long rsvd_53_62: 10; /* */ | |
668 | unsigned long enable : 1; /* RW */ | |
669 | } s; | |
670 | }; | |
671 | ||
672 | ||
673 | #endif /* __ASM_IA64_UV_MMRS__ */ |