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1 | #ifndef _ASM_IA64_HW_IRQ_H |
2 | #define _ASM_IA64_HW_IRQ_H | |
3 | ||
4 | /* | |
5 | * Copyright (C) 2001-2003 Hewlett-Packard Co | |
6 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
7 | */ | |
8 | ||
9 | #include <linux/interrupt.h> | |
10 | #include <linux/sched.h> | |
11 | #include <linux/types.h> | |
12 | #include <linux/profile.h> | |
13 | ||
14 | #include <asm/machvec.h> | |
15 | #include <asm/ptrace.h> | |
16 | #include <asm/smp.h> | |
17 | ||
18 | typedef u8 ia64_vector; | |
19 | ||
20 | /* | |
21 | * 0 special | |
22 | * | |
23 | * 1,3-14 are reserved from firmware | |
24 | * | |
25 | * 16-255 (vectored external interrupts) are available | |
26 | * | |
27 | * 15 spurious interrupt (see IVR) | |
28 | * | |
29 | * 16 lowest priority, 255 highest priority | |
30 | * | |
31 | * 15 classes of 16 interrupts each. | |
32 | */ | |
33 | #define IA64_MIN_VECTORED_IRQ 16 | |
34 | #define IA64_MAX_VECTORED_IRQ 255 | |
35 | #define IA64_NUM_VECTORS 256 | |
36 | ||
37 | #define AUTO_ASSIGN -1 | |
38 | ||
39 | #define IA64_SPURIOUS_INT_VECTOR 0x0f | |
40 | ||
41 | /* | |
42 | * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI. | |
43 | */ | |
44 | #define IA64_CPEP_VECTOR 0x1c /* corrected platform error polling vector */ | |
45 | #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */ | |
46 | #define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */ | |
47 | #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */ | |
48 | /* | |
49 | * Vectors 0x20-0x2f are reserved for legacy ISA IRQs. | |
50 | */ | |
51 | #define IA64_FIRST_DEVICE_VECTOR 0x30 | |
52 | #define IA64_LAST_DEVICE_VECTOR 0xe7 | |
53 | #define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) | |
54 | ||
55 | #define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ | |
56 | #define IA64_PERFMON_VECTOR 0xee /* performanc monitor interrupt vector */ | |
57 | #define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */ | |
58 | #define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */ | |
59 | #define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */ | |
60 | #define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */ | |
61 | ||
62 | /* Used for encoding redirected irqs */ | |
63 | ||
64 | #define IA64_IRQ_REDIRECTED (1 << 31) | |
65 | ||
66 | /* IA64 inter-cpu interrupt related definitions */ | |
67 | ||
68 | #define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000 | |
69 | ||
70 | /* Delivery modes for inter-cpu interrupts */ | |
71 | enum { | |
72 | IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */ | |
73 | IA64_IPI_DM_PMI = 0x2, /* pend a PMI */ | |
74 | IA64_IPI_DM_NMI = 0x4, /* pend an NMI (vector 2) */ | |
75 | IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */ | |
76 | IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */ | |
77 | }; | |
78 | ||
79 | extern __u8 isa_irq_to_vector_map[16]; | |
80 | #define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)] | |
81 | ||
82 | extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ | |
83 | ||
24eeb568 | 84 | extern int assign_irq_vector_nopanic (int irq); /* allocate a free vector without panic */ |
1da177e4 LT |
85 | extern int assign_irq_vector (int irq); /* allocate a free vector */ |
86 | extern void free_irq_vector (int vector); | |
87 | extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); | |
88 | extern void register_percpu_irq (ia64_vector vec, struct irqaction *action); | |
89 | ||
90 | static inline void | |
91 | hw_resend_irq (struct hw_interrupt_type *h, unsigned int vector) | |
92 | { | |
93 | platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); | |
94 | } | |
95 | ||
96 | /* | |
97 | * Default implementations for the irq-descriptor API: | |
98 | */ | |
99 | ||
100 | extern irq_desc_t irq_desc[NR_IRQS]; | |
101 | ||
102 | #ifndef CONFIG_IA64_GENERIC | |
103 | static inline unsigned int | |
104 | __ia64_local_vector_to_irq (ia64_vector vec) | |
105 | { | |
106 | return (unsigned int) vec; | |
107 | } | |
108 | #endif | |
109 | ||
110 | /* | |
111 | * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt | |
112 | * vectors. On smaller systems, there is a one-to-one correspondence between interrupt | |
113 | * vectors and the Linux irq numbers. However, larger systems may have multiple interrupt | |
114 | * domains meaning that the translation from vector number to irq number depends on the | |
115 | * interrupt domain that a CPU belongs to. This API abstracts such platform-dependent | |
116 | * differences and provides a uniform means to translate between vector and irq numbers | |
117 | * and to obtain the irq descriptor for a given irq number. | |
118 | */ | |
119 | ||
120 | /* Return a pointer to the irq descriptor for IRQ. */ | |
121 | static inline irq_desc_t * | |
122 | irq_descp (int irq) | |
123 | { | |
124 | return irq_desc + irq; | |
125 | } | |
126 | ||
127 | /* Extract the IA-64 vector that corresponds to IRQ. */ | |
128 | static inline ia64_vector | |
129 | irq_to_vector (int irq) | |
130 | { | |
131 | return (ia64_vector) irq; | |
132 | } | |
133 | ||
134 | /* | |
135 | * Convert the local IA-64 vector to the corresponding irq number. This translation is | |
136 | * done in the context of the interrupt domain that the currently executing CPU belongs | |
137 | * to. | |
138 | */ | |
139 | static inline unsigned int | |
140 | local_vector_to_irq (ia64_vector vec) | |
141 | { | |
142 | return platform_local_vector_to_irq(vec); | |
143 | } | |
144 | ||
145 | #endif /* _ASM_IA64_HW_IRQ_H */ |