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1da177e4 LT |
1 | #ifndef __ARCH_DESC_H |
2 | #define __ARCH_DESC_H | |
3 | ||
4 | #include <asm/ldt.h> | |
5 | #include <asm/segment.h> | |
6 | ||
7 | #define CPU_16BIT_STACK_SIZE 1024 | |
8 | ||
9 | #ifndef __ASSEMBLY__ | |
10 | ||
11 | #include <linux/preempt.h> | |
12 | #include <linux/smp.h> | |
13 | #include <linux/percpu.h> | |
14 | ||
15 | #include <asm/mmu.h> | |
16 | ||
17 | extern struct desc_struct cpu_gdt_table[GDT_ENTRIES]; | |
18 | DECLARE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]); | |
19 | ||
251e6912 ZA |
20 | #define get_cpu_gdt_table(_cpu) (per_cpu(cpu_gdt_table,_cpu)) |
21 | ||
1da177e4 LT |
22 | DECLARE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]); |
23 | ||
24 | struct Xgt_desc_struct { | |
25 | unsigned short size; | |
26 | unsigned long address __attribute__((packed)); | |
27 | unsigned short pad; | |
28 | } __attribute__ ((packed)); | |
29 | ||
30 | extern struct Xgt_desc_struct idt_descr, cpu_gdt_descr[NR_CPUS]; | |
31 | ||
2f2984eb ZA |
32 | #define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) |
33 | #define load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) | |
1da177e4 | 34 | |
4d37e7e3 ZA |
35 | #define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) |
36 | #define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) | |
37 | #define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr)) | |
38 | #define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt)) | |
39 | ||
40 | #define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr)) | |
41 | #define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr)) | |
42 | #define store_tr(tr) __asm__ ("str %0":"=mr" (tr)) | |
43 | #define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt)) | |
44 | ||
1da177e4 LT |
45 | /* |
46 | * This is the ldt that every process will get unless we need | |
47 | * something other than this. | |
48 | */ | |
49 | extern struct desc_struct default_ldt[]; | |
50 | extern void set_intr_gate(unsigned int irq, void * addr); | |
51 | ||
52 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
53 | __asm__ __volatile__ ("movw %w3,0(%2)\n\t" \ | |
2f2984eb ZA |
54 | "movw %w1,2(%2)\n\t" \ |
55 | "rorl $16,%1\n\t" \ | |
56 | "movb %b1,4(%2)\n\t" \ | |
1da177e4 LT |
57 | "movb %4,5(%2)\n\t" \ |
58 | "movb $0,6(%2)\n\t" \ | |
2f2984eb ZA |
59 | "movb %h1,7(%2)\n\t" \ |
60 | "rorl $16,%1" \ | |
61 | : "=m"(*(n)) : "q" (addr), "r"(n), "ir"(limit), "i"(type)) | |
1da177e4 LT |
62 | |
63 | static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *addr) | |
64 | { | |
251e6912 | 65 | _set_tssldt_desc(&get_cpu_gdt_table(cpu)[entry], (int)addr, |
1da177e4 LT |
66 | offsetof(struct tss_struct, __cacheline_filler) - 1, 0x89); |
67 | } | |
68 | ||
69 | #define set_tss_desc(cpu,addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) | |
70 | ||
71 | static inline void set_ldt_desc(unsigned int cpu, void *addr, unsigned int size) | |
72 | { | |
251e6912 | 73 | _set_tssldt_desc(&get_cpu_gdt_table(cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82); |
1da177e4 LT |
74 | } |
75 | ||
76 | #define LDT_entry_a(info) \ | |
77 | ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff)) | |
78 | ||
79 | #define LDT_entry_b(info) \ | |
80 | (((info)->base_addr & 0xff000000) | \ | |
81 | (((info)->base_addr & 0x00ff0000) >> 16) | \ | |
82 | ((info)->limit & 0xf0000) | \ | |
83 | (((info)->read_exec_only ^ 1) << 9) | \ | |
84 | ((info)->contents << 10) | \ | |
85 | (((info)->seg_not_present ^ 1) << 15) | \ | |
86 | ((info)->seg_32bit << 22) | \ | |
87 | ((info)->limit_in_pages << 23) | \ | |
88 | ((info)->useable << 20) | \ | |
89 | 0x7000) | |
90 | ||
91 | #define LDT_empty(info) (\ | |
92 | (info)->base_addr == 0 && \ | |
93 | (info)->limit == 0 && \ | |
94 | (info)->contents == 0 && \ | |
95 | (info)->read_exec_only == 1 && \ | |
96 | (info)->seg_32bit == 0 && \ | |
97 | (info)->limit_in_pages == 0 && \ | |
98 | (info)->seg_not_present == 1 && \ | |
99 | (info)->useable == 0 ) | |
100 | ||
f2f30ebc ZA |
101 | static inline void write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 entry_b) |
102 | { | |
103 | __u32 *lp = (__u32 *)((char *)ldt + entry*8); | |
104 | *lp = entry_a; | |
105 | *(lp+1) = entry_b; | |
106 | } | |
107 | ||
1da177e4 LT |
108 | #if TLS_SIZE != 24 |
109 | # error update this code. | |
110 | #endif | |
111 | ||
112 | static inline void load_TLS(struct thread_struct *t, unsigned int cpu) | |
113 | { | |
251e6912 | 114 | #define C(i) get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i] |
1da177e4 LT |
115 | C(0); C(1); C(2); |
116 | #undef C | |
117 | } | |
118 | ||
119 | static inline void clear_LDT(void) | |
120 | { | |
121 | int cpu = get_cpu(); | |
122 | ||
123 | set_ldt_desc(cpu, &default_ldt[0], 5); | |
124 | load_LDT_desc(); | |
125 | put_cpu(); | |
126 | } | |
127 | ||
128 | /* | |
129 | * load one particular LDT into the current CPU | |
130 | */ | |
131 | static inline void load_LDT_nolock(mm_context_t *pc, int cpu) | |
132 | { | |
133 | void *segments = pc->ldt; | |
134 | int count = pc->size; | |
135 | ||
136 | if (likely(!count)) { | |
137 | segments = &default_ldt[0]; | |
138 | count = 5; | |
139 | } | |
140 | ||
141 | set_ldt_desc(cpu, segments, count); | |
142 | load_LDT_desc(); | |
143 | } | |
144 | ||
145 | static inline void load_LDT(mm_context_t *pc) | |
146 | { | |
147 | int cpu = get_cpu(); | |
148 | load_LDT_nolock(pc, cpu); | |
149 | put_cpu(); | |
150 | } | |
151 | ||
152 | static inline unsigned long get_desc_base(unsigned long *desc) | |
153 | { | |
154 | unsigned long base; | |
155 | base = ((desc[0] >> 16) & 0x0000ffff) | | |
156 | ((desc[1] << 16) & 0x00ff0000) | | |
157 | (desc[1] & 0xff000000); | |
158 | return base; | |
159 | } | |
160 | ||
161 | #endif /* !__ASSEMBLY__ */ | |
162 | ||
163 | #endif |