Merge tag 'kvm-ppc-fixes-5.7-1' into topic/ppc-kvm
[linux-block.git] / include / asm-generic / pgtable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT
2#ifndef _ASM_GENERIC_PGTABLE_H
3#define _ASM_GENERIC_PGTABLE_H
4
f25748e3
DW
5#include <linux/pfn.h>
6
673eae82 7#ifndef __ASSEMBLY__
9535239f 8#ifdef CONFIG_MMU
673eae82 9
fbd71844 10#include <linux/mm_types.h>
187f1882 11#include <linux/bug.h>
e61ce6ad 12#include <linux/errno.h>
5a281062 13#include <asm-generic/pgtable_uffd.h>
fbd71844 14
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15#if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \
16 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS
17#error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED
235a8f02
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18#endif
19
6ee8630e
HD
20/*
21 * On almost all architectures and configurations, 0 can be used as the
22 * upper ceiling to free_pgtables(): on many architectures it has the same
23 * effect as using TASK_SIZE. However, there is one configuration which
24 * must impose a more careful limit, to avoid freeing kernel pgtables.
25 */
26#ifndef USER_PGTABLES_CEILING
27#define USER_PGTABLES_CEILING 0UL
28#endif
29
1da177e4 30#ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
e2cda322
AA
31extern int ptep_set_access_flags(struct vm_area_struct *vma,
32 unsigned long address, pte_t *ptep,
33 pte_t entry, int dirty);
34#endif
35
36#ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
bd5e88ad 37#ifdef CONFIG_TRANSPARENT_HUGEPAGE
e2cda322
AA
38extern int pmdp_set_access_flags(struct vm_area_struct *vma,
39 unsigned long address, pmd_t *pmdp,
40 pmd_t entry, int dirty);
a00cc7d9
MW
41extern int pudp_set_access_flags(struct vm_area_struct *vma,
42 unsigned long address, pud_t *pudp,
43 pud_t entry, int dirty);
bd5e88ad
VG
44#else
45static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
46 unsigned long address, pmd_t *pmdp,
47 pmd_t entry, int dirty)
48{
49 BUILD_BUG();
50 return 0;
51}
a00cc7d9
MW
52static inline int pudp_set_access_flags(struct vm_area_struct *vma,
53 unsigned long address, pud_t *pudp,
54 pud_t entry, int dirty)
55{
56 BUILD_BUG();
57 return 0;
58}
bd5e88ad 59#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
60#endif
61
62#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
e2cda322
AA
63static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
64 unsigned long address,
65 pte_t *ptep)
66{
67 pte_t pte = *ptep;
68 int r = 1;
69 if (!pte_young(pte))
70 r = 0;
71 else
72 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte));
73 return r;
74}
75#endif
76
77#ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
78#ifdef CONFIG_TRANSPARENT_HUGEPAGE
79static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
80 unsigned long address,
81 pmd_t *pmdp)
82{
83 pmd_t pmd = *pmdp;
84 int r = 1;
85 if (!pmd_young(pmd))
86 r = 0;
87 else
88 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd));
89 return r;
90}
bd5e88ad 91#else
e2cda322
AA
92static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
93 unsigned long address,
94 pmd_t *pmdp)
95{
bd5e88ad 96 BUILD_BUG();
e2cda322
AA
97 return 0;
98}
99#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
100#endif
101
102#ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
e2cda322
AA
103int ptep_clear_flush_young(struct vm_area_struct *vma,
104 unsigned long address, pte_t *ptep);
105#endif
106
107#ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
bd5e88ad
VG
108#ifdef CONFIG_TRANSPARENT_HUGEPAGE
109extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
110 unsigned long address, pmd_t *pmdp);
111#else
112/*
113 * Despite relevant to THP only, this API is called from generic rmap code
114 * under PageTransHuge(), hence needs a dummy implementation for !THP
115 */
116static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
117 unsigned long address, pmd_t *pmdp)
118{
119 BUILD_BUG();
120 return 0;
121}
122#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
123#endif
124
1da177e4 125#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
e2cda322
AA
126static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
127 unsigned long address,
128 pte_t *ptep)
129{
130 pte_t pte = *ptep;
131 pte_clear(mm, address, ptep);
132 return pte;
133}
134#endif
135
e2cda322 136#ifdef CONFIG_TRANSPARENT_HUGEPAGE
a00cc7d9 137#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
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138static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
139 unsigned long address,
140 pmd_t *pmdp)
e2cda322
AA
141{
142 pmd_t pmd = *pmdp;
2d28a227 143 pmd_clear(pmdp);
e2cda322 144 return pmd;
49b24d6b 145}
a00cc7d9
MW
146#endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */
147#ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
148static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
149 unsigned long address,
150 pud_t *pudp)
151{
152 pud_t pud = *pudp;
153
154 pud_clear(pudp);
155 return pud;
156}
157#endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */
e2cda322 158#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4 159
fcbe08d6 160#ifdef CONFIG_TRANSPARENT_HUGEPAGE
a00cc7d9 161#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
8809aa2d 162static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm,
fcbe08d6
MS
163 unsigned long address, pmd_t *pmdp,
164 int full)
165{
8809aa2d 166 return pmdp_huge_get_and_clear(mm, address, pmdp);
fcbe08d6 167}
fcbe08d6
MS
168#endif
169
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MW
170#ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
171static inline pud_t pudp_huge_get_and_clear_full(struct mm_struct *mm,
172 unsigned long address, pud_t *pudp,
173 int full)
174{
175 return pudp_huge_get_and_clear(mm, address, pudp);
176}
177#endif
178#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
179
a600388d 180#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
e2cda322
AA
181static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
182 unsigned long address, pte_t *ptep,
183 int full)
184{
185 pte_t pte;
186 pte = ptep_get_and_clear(mm, address, ptep);
187 return pte;
188}
a600388d
ZA
189#endif
190
9888a1ca
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191/*
192 * Some architectures may be able to avoid expensive synchronization
193 * primitives when modifications are made to PTE's which are already
194 * not present, or in the process of an address space destruction.
195 */
196#ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
e2cda322
AA
197static inline void pte_clear_not_present_full(struct mm_struct *mm,
198 unsigned long address,
199 pte_t *ptep,
200 int full)
201{
202 pte_clear(mm, address, ptep);
203}
a600388d
ZA
204#endif
205
1da177e4 206#ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
e2cda322
AA
207extern pte_t ptep_clear_flush(struct vm_area_struct *vma,
208 unsigned long address,
209 pte_t *ptep);
210#endif
211
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212#ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
213extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
e2cda322
AA
214 unsigned long address,
215 pmd_t *pmdp);
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MW
216extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma,
217 unsigned long address,
218 pud_t *pudp);
1da177e4
LT
219#endif
220
221#ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
8c65b4a6 222struct mm_struct;
1da177e4
LT
223static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
224{
225 pte_t old_pte = *ptep;
226 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
227}
228#endif
229
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230#ifndef pte_savedwrite
231#define pte_savedwrite pte_write
232#endif
233
234#ifndef pte_mk_savedwrite
235#define pte_mk_savedwrite pte_mkwrite
236#endif
237
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238#ifndef pte_clear_savedwrite
239#define pte_clear_savedwrite pte_wrprotect
240#endif
241
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AK
242#ifndef pmd_savedwrite
243#define pmd_savedwrite pmd_write
244#endif
245
246#ifndef pmd_mk_savedwrite
247#define pmd_mk_savedwrite pmd_mkwrite
248#endif
249
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250#ifndef pmd_clear_savedwrite
251#define pmd_clear_savedwrite pmd_wrprotect
252#endif
253
e2cda322
AA
254#ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT
255#ifdef CONFIG_TRANSPARENT_HUGEPAGE
256static inline void pmdp_set_wrprotect(struct mm_struct *mm,
257 unsigned long address, pmd_t *pmdp)
258{
259 pmd_t old_pmd = *pmdp;
260 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd));
261}
bd5e88ad 262#else
e2cda322
AA
263static inline void pmdp_set_wrprotect(struct mm_struct *mm,
264 unsigned long address, pmd_t *pmdp)
265{
bd5e88ad 266 BUILD_BUG();
e2cda322
AA
267}
268#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
269#endif
a00cc7d9
MW
270#ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT
271#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
272static inline void pudp_set_wrprotect(struct mm_struct *mm,
273 unsigned long address, pud_t *pudp)
274{
275 pud_t old_pud = *pudp;
276
277 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud));
278}
279#else
280static inline void pudp_set_wrprotect(struct mm_struct *mm,
281 unsigned long address, pud_t *pudp)
282{
283 BUILD_BUG();
284}
285#endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */
286#endif
e2cda322 287
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288#ifndef pmdp_collapse_flush
289#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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AK
290extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
291 unsigned long address, pmd_t *pmdp);
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AK
292#else
293static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
294 unsigned long address,
295 pmd_t *pmdp)
296{
297 BUILD_BUG();
298 return *pmdp;
299}
300#define pmdp_collapse_flush pmdp_collapse_flush
301#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
302#endif
303
e3ebcf64 304#ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
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AK
305extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
306 pgtable_t pgtable);
e3ebcf64
GS
307#endif
308
309#ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
6b0b50b0 310extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
e3ebcf64
GS
311#endif
312
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313#ifdef CONFIG_TRANSPARENT_HUGEPAGE
314/*
315 * This is an implementation of pmdp_establish() that is only suitable for an
316 * architecture that doesn't have hardware dirty/accessed bits. In this case we
317 * can't race with CPU which sets these bits and non-atomic aproach is fine.
318 */
319static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma,
320 unsigned long address, pmd_t *pmdp, pmd_t pmd)
321{
322 pmd_t old_pmd = *pmdp;
323 set_pmd_at(vma->vm_mm, address, pmdp, pmd);
324 return old_pmd;
325}
326#endif
327
46dcde73 328#ifndef __HAVE_ARCH_PMDP_INVALIDATE
d52605d7 329extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
46dcde73
GS
330 pmd_t *pmdp);
331#endif
332
1da177e4 333#ifndef __HAVE_ARCH_PTE_SAME
e2cda322
AA
334static inline int pte_same(pte_t pte_a, pte_t pte_b)
335{
336 return pte_val(pte_a) == pte_val(pte_b);
337}
338#endif
339
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KW
340#ifndef __HAVE_ARCH_PTE_UNUSED
341/*
342 * Some architectures provide facilities to virtualization guests
343 * so that they can flag allocated pages as unused. This allows the
344 * host to transparently reclaim unused pages. This function returns
345 * whether the pte's page is unused.
346 */
347static inline int pte_unused(pte_t pte)
348{
349 return 0;
350}
351#endif
352
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353#ifndef pte_access_permitted
354#define pte_access_permitted(pte, write) \
355 (pte_present(pte) && (!(write) || pte_write(pte)))
356#endif
357
358#ifndef pmd_access_permitted
359#define pmd_access_permitted(pmd, write) \
360 (pmd_present(pmd) && (!(write) || pmd_write(pmd)))
361#endif
362
363#ifndef pud_access_permitted
364#define pud_access_permitted(pud, write) \
365 (pud_present(pud) && (!(write) || pud_write(pud)))
366#endif
367
368#ifndef p4d_access_permitted
369#define p4d_access_permitted(p4d, write) \
370 (p4d_present(p4d) && (!(write) || p4d_write(p4d)))
371#endif
372
373#ifndef pgd_access_permitted
374#define pgd_access_permitted(pgd, write) \
375 (pgd_present(pgd) && (!(write) || pgd_write(pgd)))
376#endif
377
e2cda322 378#ifndef __HAVE_ARCH_PMD_SAME
e2cda322
AA
379static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
380{
381 return pmd_val(pmd_a) == pmd_val(pmd_b);
382}
a00cc7d9
MW
383
384static inline int pud_same(pud_t pud_a, pud_t pud_b)
385{
386 return pud_val(pud_a) == pud_val(pud_b);
387}
1da177e4
LT
388#endif
389
0cebbb60
DW
390#ifndef __HAVE_ARCH_P4D_SAME
391static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b)
392{
393 return p4d_val(p4d_a) == p4d_val(p4d_b);
394}
395#endif
396
397#ifndef __HAVE_ARCH_PGD_SAME
398static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b)
399{
400 return pgd_val(pgd_a) == pgd_val(pgd_b);
401}
402#endif
403
4369deaa
DW
404/*
405 * Use set_p*_safe(), and elide TLB flushing, when confident that *no*
406 * TLB flush will be required as a result of the "set". For example, use
407 * in scenarios where it is known ahead of time that the routine is
408 * setting non-present entries, or re-setting an existing entry to the
409 * same value. Otherwise, use the typical "set" helpers and flush the
410 * TLB.
411 */
412#define set_pte_safe(ptep, pte) \
413({ \
414 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \
415 set_pte(ptep, pte); \
416})
417
418#define set_pmd_safe(pmdp, pmd) \
419({ \
420 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \
421 set_pmd(pmdp, pmd); \
422})
423
424#define set_pud_safe(pudp, pud) \
425({ \
426 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \
427 set_pud(pudp, pud); \
428})
429
430#define set_p4d_safe(p4dp, p4d) \
431({ \
432 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \
433 set_p4d(p4dp, p4d); \
434})
435
436#define set_pgd_safe(pgdp, pgd) \
437({ \
438 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \
439 set_pgd(pgdp, pgd); \
440})
441
ca827d55
KA
442#ifndef __HAVE_ARCH_DO_SWAP_PAGE
443/*
444 * Some architectures support metadata associated with a page. When a
445 * page is being swapped out, this metadata must be saved so it can be
446 * restored when the page is swapped back in. SPARC M7 and newer
447 * processors support an ADI (Application Data Integrity) tag for the
448 * page as metadata for the page. arch_do_swap_page() can restore this
449 * metadata when a page is swapped back in.
450 */
451static inline void arch_do_swap_page(struct mm_struct *mm,
452 struct vm_area_struct *vma,
453 unsigned long addr,
454 pte_t pte, pte_t oldpte)
455{
456
457}
458#endif
459
460#ifndef __HAVE_ARCH_UNMAP_ONE
461/*
462 * Some architectures support metadata associated with a page. When a
463 * page is being swapped out, this metadata must be saved so it can be
464 * restored when the page is swapped back in. SPARC M7 and newer
465 * processors support an ADI (Application Data Integrity) tag for the
466 * page as metadata for the page. arch_unmap_one() can save this
467 * metadata on a swap-out of a page.
468 */
469static inline int arch_unmap_one(struct mm_struct *mm,
470 struct vm_area_struct *vma,
471 unsigned long addr,
472 pte_t orig_pte)
473{
474 return 0;
475}
476#endif
477
1da177e4
LT
478#ifndef __HAVE_ARCH_PGD_OFFSET_GATE
479#define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
480#endif
481
0b0968a3 482#ifndef __HAVE_ARCH_MOVE_PTE
8b1f3124 483#define move_pte(pte, prot, old_addr, new_addr) (pte)
8b1f3124
NP
484#endif
485
2c3cf556 486#ifndef pte_accessible
20841405 487# define pte_accessible(mm, pte) ((void)(pte), 1)
2c3cf556
RR
488#endif
489
61c77326
SL
490#ifndef flush_tlb_fix_spurious_fault
491#define flush_tlb_fix_spurious_fault(vma, address) flush_tlb_page(vma, address)
492#endif
493
0634a632
PM
494#ifndef pgprot_noncached
495#define pgprot_noncached(prot) (prot)
496#endif
497
2520bd31 498#ifndef pgprot_writecombine
499#define pgprot_writecombine pgprot_noncached
500#endif
501
d1b4bfbf
TK
502#ifndef pgprot_writethrough
503#define pgprot_writethrough pgprot_noncached
504#endif
505
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LD
506#ifndef pgprot_device
507#define pgprot_device pgprot_noncached
508#endif
509
64e45507
PF
510#ifndef pgprot_modify
511#define pgprot_modify pgprot_modify
512static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
513{
514 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
515 newprot = pgprot_noncached(newprot);
516 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
517 newprot = pgprot_writecombine(newprot);
518 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
519 newprot = pgprot_device(newprot);
520 return newprot;
521}
522#endif
523
1da177e4 524/*
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HD
525 * When walking page tables, get the address of the next boundary,
526 * or the end address of the range if that comes earlier. Although no
527 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
1da177e4
LT
528 */
529
1da177e4
LT
530#define pgd_addr_end(addr, end) \
531({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
532 (__boundary - 1 < (end) - 1)? __boundary: (end); \
533})
1da177e4 534
c2febafc
KS
535#ifndef p4d_addr_end
536#define p4d_addr_end(addr, end) \
537({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \
538 (__boundary - 1 < (end) - 1)? __boundary: (end); \
539})
540#endif
541
1da177e4
LT
542#ifndef pud_addr_end
543#define pud_addr_end(addr, end) \
544({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
545 (__boundary - 1 < (end) - 1)? __boundary: (end); \
546})
547#endif
548
549#ifndef pmd_addr_end
550#define pmd_addr_end(addr, end) \
551({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
552 (__boundary - 1 < (end) - 1)? __boundary: (end); \
553})
554#endif
555
1da177e4
LT
556/*
557 * When walking page tables, we usually want to skip any p?d_none entries;
558 * and any p?d_bad entries - reporting the error before resetting to none.
559 * Do the tests inline, but report and clear the bad entry in mm/memory.c.
560 */
561void pgd_clear_bad(pgd_t *);
f2400abc
VG
562
563#ifndef __PAGETABLE_P4D_FOLDED
c2febafc 564void p4d_clear_bad(p4d_t *);
f2400abc
VG
565#else
566#define p4d_clear_bad(p4d) do { } while (0)
567#endif
568
569#ifndef __PAGETABLE_PUD_FOLDED
1da177e4 570void pud_clear_bad(pud_t *);
f2400abc
VG
571#else
572#define pud_clear_bad(p4d) do { } while (0)
573#endif
574
1da177e4
LT
575void pmd_clear_bad(pmd_t *);
576
577static inline int pgd_none_or_clear_bad(pgd_t *pgd)
578{
579 if (pgd_none(*pgd))
580 return 1;
581 if (unlikely(pgd_bad(*pgd))) {
582 pgd_clear_bad(pgd);
583 return 1;
584 }
585 return 0;
586}
587
c2febafc
KS
588static inline int p4d_none_or_clear_bad(p4d_t *p4d)
589{
590 if (p4d_none(*p4d))
591 return 1;
592 if (unlikely(p4d_bad(*p4d))) {
593 p4d_clear_bad(p4d);
594 return 1;
595 }
596 return 0;
597}
598
1da177e4
LT
599static inline int pud_none_or_clear_bad(pud_t *pud)
600{
601 if (pud_none(*pud))
602 return 1;
603 if (unlikely(pud_bad(*pud))) {
604 pud_clear_bad(pud);
605 return 1;
606 }
607 return 0;
608}
609
610static inline int pmd_none_or_clear_bad(pmd_t *pmd)
611{
612 if (pmd_none(*pmd))
613 return 1;
614 if (unlikely(pmd_bad(*pmd))) {
615 pmd_clear_bad(pmd);
616 return 1;
617 }
618 return 0;
619}
9535239f 620
0cbe3e26 621static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma,
1ea0704e
JF
622 unsigned long addr,
623 pte_t *ptep)
624{
625 /*
626 * Get the current pte state, but zero it out to make it
627 * non-present, preventing the hardware from asynchronously
628 * updating it.
629 */
0cbe3e26 630 return ptep_get_and_clear(vma->vm_mm, addr, ptep);
1ea0704e
JF
631}
632
0cbe3e26 633static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma,
1ea0704e
JF
634 unsigned long addr,
635 pte_t *ptep, pte_t pte)
636{
637 /*
638 * The pte is non-present, so there's no hardware state to
639 * preserve.
640 */
0cbe3e26 641 set_pte_at(vma->vm_mm, addr, ptep, pte);
1ea0704e
JF
642}
643
644#ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
645/*
646 * Start a pte protection read-modify-write transaction, which
647 * protects against asynchronous hardware modifications to the pte.
648 * The intention is not to prevent the hardware from making pte
649 * updates, but to prevent any updates it may make from being lost.
650 *
651 * This does not protect against other software modifications of the
652 * pte; the appropriate pte lock must be held over the transation.
653 *
654 * Note that this interface is intended to be batchable, meaning that
655 * ptep_modify_prot_commit may not actually update the pte, but merely
656 * queue the update to be done at some later time. The update must be
657 * actually committed before the pte lock is released, however.
658 */
0cbe3e26 659static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
1ea0704e
JF
660 unsigned long addr,
661 pte_t *ptep)
662{
0cbe3e26 663 return __ptep_modify_prot_start(vma, addr, ptep);
1ea0704e
JF
664}
665
666/*
667 * Commit an update to a pte, leaving any hardware-controlled bits in
668 * the PTE unmodified.
669 */
0cbe3e26 670static inline void ptep_modify_prot_commit(struct vm_area_struct *vma,
1ea0704e 671 unsigned long addr,
04a86453 672 pte_t *ptep, pte_t old_pte, pte_t pte)
1ea0704e 673{
0cbe3e26 674 __ptep_modify_prot_commit(vma, addr, ptep, pte);
1ea0704e
JF
675}
676#endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
fe1a6875 677#endif /* CONFIG_MMU */
1ea0704e 678
21729f81
TL
679/*
680 * No-op macros that just return the current protection value. Defined here
681 * because these macros can be used used even if CONFIG_MMU is not defined.
682 */
683#ifndef pgprot_encrypted
684#define pgprot_encrypted(prot) (prot)
685#endif
686
687#ifndef pgprot_decrypted
688#define pgprot_decrypted(prot) (prot)
689#endif
690
9535239f
GU
691/*
692 * A facility to provide lazy MMU batching. This allows PTE updates and
693 * page invalidations to be delayed until a call to leave lazy MMU mode
694 * is issued. Some architectures may benefit from doing this, and it is
695 * beneficial for both shadow and direct mode hypervisors, which may batch
696 * the PTE updates which happen during this window. Note that using this
697 * interface requires that read hazards be removed from the code. A read
698 * hazard could result in the direct mode hypervisor case, since the actual
699 * write to the page tables may not yet have taken place, so reads though
700 * a raw PTE pointer after it has been modified are not guaranteed to be
701 * up to date. This mode can only be entered and left under the protection of
702 * the page table locks for all page tables which may be modified. In the UP
703 * case, this is required so that preemption is disabled, and in the SMP case,
704 * it must synchronize the delayed page table writes properly on other CPUs.
705 */
706#ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE
707#define arch_enter_lazy_mmu_mode() do {} while (0)
708#define arch_leave_lazy_mmu_mode() do {} while (0)
709#define arch_flush_lazy_mmu_mode() do {} while (0)
710#endif
711
712/*
7fd7d83d
JF
713 * A facility to provide batching of the reload of page tables and
714 * other process state with the actual context switch code for
715 * paravirtualized guests. By convention, only one of the batched
716 * update (lazy) modes (CPU, MMU) should be active at any given time,
717 * entry should never be nested, and entry and exits should always be
718 * paired. This is for sanity of maintaining and reasoning about the
719 * kernel code. In this case, the exit (end of the context switch) is
720 * in architecture-specific code, and so doesn't need a generic
721 * definition.
9535239f 722 */
7fd7d83d 723#ifndef __HAVE_ARCH_START_CONTEXT_SWITCH
224101ed 724#define arch_start_context_switch(prev) do {} while (0)
9535239f
GU
725#endif
726
ab6e3d09
NH
727#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
728#ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION
729static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
730{
731 return pmd;
732}
733
734static inline int pmd_swp_soft_dirty(pmd_t pmd)
735{
736 return 0;
737}
738
739static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
740{
741 return pmd;
742}
743#endif
744#else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */
0f8975ec
PE
745static inline int pte_soft_dirty(pte_t pte)
746{
747 return 0;
748}
749
750static inline int pmd_soft_dirty(pmd_t pmd)
751{
752 return 0;
753}
754
755static inline pte_t pte_mksoft_dirty(pte_t pte)
756{
757 return pte;
758}
759
760static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
761{
762 return pmd;
763}
179ef71c 764
a7b76174
MS
765static inline pte_t pte_clear_soft_dirty(pte_t pte)
766{
767 return pte;
768}
769
770static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
771{
772 return pmd;
773}
774
179ef71c
CG
775static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
776{
777 return pte;
778}
779
780static inline int pte_swp_soft_dirty(pte_t pte)
781{
782 return 0;
783}
784
785static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
786{
787 return pte;
788}
ab6e3d09
NH
789
790static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
791{
792 return pmd;
793}
794
795static inline int pmd_swp_soft_dirty(pmd_t pmd)
796{
797 return 0;
798}
799
800static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
801{
802 return pmd;
803}
0f8975ec
PE
804#endif
805
34801ba9 806#ifndef __HAVE_PFNMAP_TRACKING
807/*
5180da41
SS
808 * Interfaces that can be used by architecture code to keep track of
809 * memory type of pfn mappings specified by the remap_pfn_range,
67fa1666 810 * vmf_insert_pfn.
5180da41
SS
811 */
812
813/*
814 * track_pfn_remap is called when a _new_ pfn mapping is being established
815 * by remap_pfn_range() for physical range indicated by pfn and size.
34801ba9 816 */
5180da41 817static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
b3b9c293
KK
818 unsigned long pfn, unsigned long addr,
819 unsigned long size)
34801ba9 820{
821 return 0;
822}
823
824/*
5180da41 825 * track_pfn_insert is called when a _new_ single pfn is established
67fa1666 826 * by vmf_insert_pfn().
5180da41 827 */
308a047c
BP
828static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
829 pfn_t pfn)
5180da41 830{
5180da41
SS
831}
832
833/*
834 * track_pfn_copy is called when vma that is covering the pfnmap gets
34801ba9 835 * copied through copy_page_range().
836 */
5180da41 837static inline int track_pfn_copy(struct vm_area_struct *vma)
34801ba9 838{
839 return 0;
840}
841
842/*
d9fe4fab 843 * untrack_pfn is called while unmapping a pfnmap for a region.
34801ba9 844 * untrack can be called for a specific region indicated by pfn and size or
5180da41 845 * can be for the entire vma (in which case pfn, size are zero).
34801ba9 846 */
5180da41
SS
847static inline void untrack_pfn(struct vm_area_struct *vma,
848 unsigned long pfn, unsigned long size)
34801ba9 849{
850}
d9fe4fab
TK
851
852/*
853 * untrack_pfn_moved is called while mremapping a pfnmap for a new region.
854 */
855static inline void untrack_pfn_moved(struct vm_area_struct *vma)
856{
857}
34801ba9 858#else
5180da41 859extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
b3b9c293
KK
860 unsigned long pfn, unsigned long addr,
861 unsigned long size);
308a047c
BP
862extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
863 pfn_t pfn);
5180da41
SS
864extern int track_pfn_copy(struct vm_area_struct *vma);
865extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
866 unsigned long size);
d9fe4fab 867extern void untrack_pfn_moved(struct vm_area_struct *vma);
34801ba9 868#endif
869
816422ad
KS
870#ifdef __HAVE_COLOR_ZERO_PAGE
871static inline int is_zero_pfn(unsigned long pfn)
872{
873 extern unsigned long zero_pfn;
874 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
875 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
876}
877
2f91ec8c
KS
878#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
879
816422ad
KS
880#else
881static inline int is_zero_pfn(unsigned long pfn)
882{
883 extern unsigned long zero_pfn;
884 return pfn == zero_pfn;
885}
886
887static inline unsigned long my_zero_pfn(unsigned long addr)
888{
889 extern unsigned long zero_pfn;
890 return zero_pfn;
891}
892#endif
893
1a5a9906
AA
894#ifdef CONFIG_MMU
895
5f6e8da7
AA
896#ifndef CONFIG_TRANSPARENT_HUGEPAGE
897static inline int pmd_trans_huge(pmd_t pmd)
898{
899 return 0;
900}
e4e40e02 901#ifndef pmd_write
e2cda322
AA
902static inline int pmd_write(pmd_t pmd)
903{
904 BUG();
905 return 0;
906}
e4e40e02 907#endif /* pmd_write */
1a5a9906
AA
908#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
909
1501899a
DW
910#ifndef pud_write
911static inline int pud_write(pud_t pud)
912{
913 BUG();
914 return 0;
915}
916#endif /* pud_write */
917
bf1a12a8
TH
918#if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE)
919static inline int pmd_devmap(pmd_t pmd)
920{
921 return 0;
922}
923static inline int pud_devmap(pud_t pud)
924{
925 return 0;
926}
927static inline int pgd_devmap(pgd_t pgd)
928{
929 return 0;
930}
931#endif
932
a00cc7d9
MW
933#if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \
934 (defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
935 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD))
936static inline int pud_trans_huge(pud_t pud)
937{
938 return 0;
939}
940#endif
941
625110b5
TH
942/* See pmd_none_or_trans_huge_or_clear_bad for discussion. */
943static inline int pud_none_or_trans_huge_or_dev_or_clear_bad(pud_t *pud)
944{
945 pud_t pudval = READ_ONCE(*pud);
946
947 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval))
948 return 1;
949 if (unlikely(pud_bad(pudval))) {
950 pud_clear_bad(pud);
951 return 1;
952 }
953 return 0;
954}
955
956/* See pmd_trans_unstable for discussion. */
957static inline int pud_trans_unstable(pud_t *pud)
958{
959#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
960 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
961 return pud_none_or_trans_huge_or_dev_or_clear_bad(pud);
962#else
963 return 0;
964#endif
965}
966
26c19178
AA
967#ifndef pmd_read_atomic
968static inline pmd_t pmd_read_atomic(pmd_t *pmdp)
969{
970 /*
971 * Depend on compiler for an atomic pmd read. NOTE: this is
972 * only going to work, if the pmdval_t isn't larger than
973 * an unsigned long.
974 */
975 return *pmdp;
976}
977#endif
978
953c66c2
AK
979#ifndef arch_needs_pgtable_deposit
980#define arch_needs_pgtable_deposit() (false)
981#endif
1a5a9906
AA
982/*
983 * This function is meant to be used by sites walking pagetables with
984 * the mmap_sem hold in read mode to protect against MADV_DONTNEED and
985 * transhuge page faults. MADV_DONTNEED can convert a transhuge pmd
986 * into a null pmd and the transhuge page fault can convert a null pmd
987 * into an hugepmd or into a regular pmd (if the hugepage allocation
988 * fails). While holding the mmap_sem in read mode the pmd becomes
989 * stable and stops changing under us only if it's not null and not a
990 * transhuge pmd. When those races occurs and this function makes a
991 * difference vs the standard pmd_none_or_clear_bad, the result is
992 * undefined so behaving like if the pmd was none is safe (because it
993 * can return none anyway). The compiler level barrier() is critically
994 * important to compute the two checks atomically on the same pmdval.
26c19178
AA
995 *
996 * For 32bit kernels with a 64bit large pmd_t this automatically takes
997 * care of reading the pmd atomically to avoid SMP race conditions
998 * against pmd_populate() when the mmap_sem is hold for reading by the
999 * caller (a special atomic read not done by "gcc" as in the generic
1000 * version above, is also needed when THP is disabled because the page
1001 * fault can populate the pmd from under us).
1a5a9906
AA
1002 */
1003static inline int pmd_none_or_trans_huge_or_clear_bad(pmd_t *pmd)
1004{
26c19178 1005 pmd_t pmdval = pmd_read_atomic(pmd);
1a5a9906
AA
1006 /*
1007 * The barrier will stabilize the pmdval in a register or on
1008 * the stack so that it will stop changing under the code.
e4eed03f
AA
1009 *
1010 * When CONFIG_TRANSPARENT_HUGEPAGE=y on x86 32bit PAE,
1011 * pmd_read_atomic is allowed to return a not atomic pmdval
1012 * (for example pointing to an hugepage that has never been
1013 * mapped in the pmd). The below checks will only care about
1014 * the low part of the pmd with 32bit PAE x86 anyway, with the
1015 * exception of pmd_none(). So the important thing is that if
1016 * the low part of the pmd is found null, the high part will
1017 * be also null or the pmd_none() check below would be
1018 * confused.
1a5a9906
AA
1019 */
1020#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1021 barrier();
1022#endif
84c3fc4e
ZY
1023 /*
1024 * !pmd_present() checks for pmd migration entries
1025 *
1026 * The complete check uses is_pmd_migration_entry() in linux/swapops.h
1027 * But using that requires moving current function and pmd_trans_unstable()
1028 * to linux/swapops.h to resovle dependency, which is too much code move.
1029 *
1030 * !pmd_present() is equivalent to is_pmd_migration_entry() currently,
1031 * because !pmd_present() pages can only be under migration not swapped
1032 * out.
1033 *
1034 * pmd_none() is preseved for future condition checks on pmd migration
1035 * entries and not confusing with this function name, although it is
1036 * redundant with !pmd_present().
1037 */
1038 if (pmd_none(pmdval) || pmd_trans_huge(pmdval) ||
1039 (IS_ENABLED(CONFIG_ARCH_ENABLE_THP_MIGRATION) && !pmd_present(pmdval)))
1a5a9906
AA
1040 return 1;
1041 if (unlikely(pmd_bad(pmdval))) {
ee53664b 1042 pmd_clear_bad(pmd);
1a5a9906
AA
1043 return 1;
1044 }
1045 return 0;
1046}
1047
1048/*
1049 * This is a noop if Transparent Hugepage Support is not built into
1050 * the kernel. Otherwise it is equivalent to
1051 * pmd_none_or_trans_huge_or_clear_bad(), and shall only be called in
1052 * places that already verified the pmd is not none and they want to
1053 * walk ptes while holding the mmap sem in read mode (write mode don't
1054 * need this). If THP is not enabled, the pmd can't go away under the
1055 * code even if MADV_DONTNEED runs, but if THP is enabled we need to
1056 * run a pmd_trans_unstable before walking the ptes after
9ef258ba
KW
1057 * split_huge_pmd returns (because it may have run when the pmd become
1058 * null, but then a page fault can map in a THP and not a regular page).
1a5a9906
AA
1059 */
1060static inline int pmd_trans_unstable(pmd_t *pmd)
1061{
1062#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1063 return pmd_none_or_trans_huge_or_clear_bad(pmd);
1064#else
1065 return 0;
5f6e8da7 1066#endif
1a5a9906
AA
1067}
1068
e7bb4b6d
MG
1069#ifndef CONFIG_NUMA_BALANCING
1070/*
1071 * Technically a PTE can be PROTNONE even when not doing NUMA balancing but
1072 * the only case the kernel cares is for NUMA balancing and is only ever set
1073 * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked
1074 * _PAGE_PROTNONE so by by default, implement the helper as "always no". It
1075 * is the responsibility of the caller to distinguish between PROT_NONE
1076 * protections and NUMA hinting fault protections.
1077 */
1078static inline int pte_protnone(pte_t pte)
1079{
1080 return 0;
1081}
1082
1083static inline int pmd_protnone(pmd_t pmd)
1084{
1085 return 0;
1086}
1087#endif /* CONFIG_NUMA_BALANCING */
1088
1a5a9906 1089#endif /* CONFIG_MMU */
5f6e8da7 1090
e61ce6ad 1091#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
c2febafc
KS
1092
1093#ifndef __PAGETABLE_P4D_FOLDED
1094int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot);
1095int p4d_clear_huge(p4d_t *p4d);
1096#else
1097static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
1098{
1099 return 0;
1100}
1101static inline int p4d_clear_huge(p4d_t *p4d)
1102{
1103 return 0;
1104}
1105#endif /* !__PAGETABLE_P4D_FOLDED */
1106
e61ce6ad
TK
1107int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
1108int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
b9820d8f
TK
1109int pud_clear_huge(pud_t *pud);
1110int pmd_clear_huge(pmd_t *pmd);
8e2d4340 1111int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);
785a19f9
CP
1112int pud_free_pmd_page(pud_t *pud, unsigned long addr);
1113int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);
e61ce6ad 1114#else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */
c2febafc
KS
1115static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
1116{
1117 return 0;
1118}
e61ce6ad
TK
1119static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
1120{
1121 return 0;
1122}
1123static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
1124{
1125 return 0;
1126}
c2febafc
KS
1127static inline int p4d_clear_huge(p4d_t *p4d)
1128{
1129 return 0;
1130}
b9820d8f
TK
1131static inline int pud_clear_huge(pud_t *pud)
1132{
1133 return 0;
1134}
1135static inline int pmd_clear_huge(pmd_t *pmd)
1136{
1137 return 0;
1138}
8e2d4340
WD
1139static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
1140{
1141 return 0;
1142}
785a19f9 1143static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr)
b6bdb751
TK
1144{
1145 return 0;
1146}
785a19f9 1147static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
b6bdb751
TK
1148{
1149 return 0;
1150}
e61ce6ad
TK
1151#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
1152
458aa76d
AK
1153#ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
1154#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1155/*
1156 * ARCHes with special requirements for evicting THP backing TLB entries can
1157 * implement this. Otherwise also, it can help optimize normal TLB flush in
1158 * THP regime. stock flush_tlb_range() typically has optimization to nuke the
1159 * entire TLB TLB if flush span is greater than a threshold, which will
1160 * likely be true for a single huge page. Thus a single thp flush will
1161 * invalidate the entire TLB which is not desitable.
1162 * e.g. see arch/arc: flush_pmd_tlb_range
1163 */
1164#define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
a00cc7d9 1165#define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
458aa76d
AK
1166#else
1167#define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG()
a00cc7d9 1168#define flush_pud_tlb_range(vma, addr, end) BUILD_BUG()
458aa76d
AK
1169#endif
1170#endif
1171
08ea8c07
BX
1172struct file;
1173int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
1174 unsigned long size, pgprot_t *vma_prot);
613e396b
TG
1175
1176#ifndef CONFIG_X86_ESPFIX64
1177static inline void init_espfix_bsp(void) { }
1178#endif
1179
782de70c 1180extern void __init pgtable_cache_init(void);
caa84136 1181
6c26fcd2
JK
1182#ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED
1183static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot)
1184{
1185 return true;
1186}
1187
1188static inline bool arch_has_pfn_modify_check(void)
1189{
1190 return false;
1191}
1192#endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */
1193
a3266bd4
LR
1194/*
1195 * Architecture PAGE_KERNEL_* fallbacks
1196 *
1197 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either
1198 * because they really don't support them, or the port needs to be updated to
1199 * reflect the required functionality. Below are a set of relatively safe
1200 * fallbacks, as best effort, which we can count on in lieu of the architectures
1201 * not defining them on their own yet.
1202 */
1203
1204#ifndef PAGE_KERNEL_RO
1205# define PAGE_KERNEL_RO PAGE_KERNEL
1206#endif
1207
1a9b4b3d
LR
1208#ifndef PAGE_KERNEL_EXEC
1209# define PAGE_KERNEL_EXEC PAGE_KERNEL
1210#endif
1211
1da177e4
LT
1212#endif /* !__ASSEMBLY__ */
1213
40d158e6
AV
1214#ifndef io_remap_pfn_range
1215#define io_remap_pfn_range remap_pfn_range
1216#endif
1217
fd8cfd30
HD
1218#ifndef has_transparent_hugepage
1219#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1220#define has_transparent_hugepage() 1
1221#else
1222#define has_transparent_hugepage() 0
1223#endif
1224#endif
1225
1071fc57
MS
1226/*
1227 * On some architectures it depends on the mm if the p4d/pud or pmd
1228 * layer of the page table hierarchy is folded or not.
1229 */
1230#ifndef mm_p4d_folded
1231#define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED)
1232#endif
1233
1234#ifndef mm_pud_folded
1235#define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED)
1236#endif
1237
1238#ifndef mm_pmd_folded
1239#define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED)
1240#endif
1241
93fab1b2
SP
1242/*
1243 * p?d_leaf() - true if this entry is a final mapping to a physical address.
1244 * This differs from p?d_huge() by the fact that they are always available (if
1245 * the architecture supports large pages at the appropriate level) even
1246 * if CONFIG_HUGETLB_PAGE is not defined.
1247 * Only meaningful when called on a valid entry.
1248 */
1249#ifndef pgd_leaf
1250#define pgd_leaf(x) 0
1251#endif
1252#ifndef p4d_leaf
1253#define p4d_leaf(x) 0
1254#endif
1255#ifndef pud_leaf
1256#define pud_leaf(x) 0
1257#endif
1258#ifndef pmd_leaf
1259#define pmd_leaf(x) 0
1260#endif
1261
1da177e4 1262#endif /* _ASM_GENERIC_PGTABLE_H */