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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | #ifndef __GENERIC_IO_H |
3 | #define __GENERIC_IO_H | |
4 | ||
5 | #include <linux/linkage.h> | |
dae409a2 | 6 | #include <asm/byteorder.h> |
1da177e4 LT |
7 | |
8 | /* | |
9 | * These are the "generic" interfaces for doing new-style | |
10 | * memory-mapped or PIO accesses. Architectures may do | |
11 | * their own arch-optimized versions, these just act as | |
12 | * wrappers around the old-style IO register access functions: | |
13 | * read[bwl]/write[bwl]/in[bwl]/out[bwl] | |
14 | * | |
15 | * Don't include this directly, include it from <asm/io.h>. | |
16 | */ | |
17 | ||
18 | /* | |
19 | * Read/write from/to an (offsettable) iomem cookie. It might be a PIO | |
20 | * access or a MMIO access, these functions don't care. The info is | |
21 | * encoded in the hardware mapping set up by the mapping functions | |
22 | * (or the cookie itself, depending on implementation and hw). | |
23 | * | |
24 | * The generic routines just encode the PIO/MMIO as part of the | |
25 | * cookie, and coldly assume that the MMIO IO mappings are not | |
26 | * in the low address range. Architectures for which this is not | |
27 | * true can't use this generic implementation. | |
28 | */ | |
8f28ca6b KK |
29 | extern unsigned int ioread8(const void __iomem *); |
30 | extern unsigned int ioread16(const void __iomem *); | |
31 | extern unsigned int ioread16be(const void __iomem *); | |
32 | extern unsigned int ioread32(const void __iomem *); | |
33 | extern unsigned int ioread32be(const void __iomem *); | |
9e44fb18 | 34 | #ifdef CONFIG_64BIT |
8f28ca6b KK |
35 | extern u64 ioread64(const void __iomem *); |
36 | extern u64 ioread64be(const void __iomem *); | |
9e44fb18 | 37 | #endif |
1da177e4 | 38 | |
79bf0cbd LG |
39 | #ifdef readq |
40 | #define ioread64_lo_hi ioread64_lo_hi | |
41 | #define ioread64_hi_lo ioread64_hi_lo | |
42 | #define ioread64be_lo_hi ioread64be_lo_hi | |
43 | #define ioread64be_hi_lo ioread64be_hi_lo | |
8f28ca6b KK |
44 | extern u64 ioread64_lo_hi(const void __iomem *addr); |
45 | extern u64 ioread64_hi_lo(const void __iomem *addr); | |
46 | extern u64 ioread64be_lo_hi(const void __iomem *addr); | |
47 | extern u64 ioread64be_hi_lo(const void __iomem *addr); | |
79bf0cbd LG |
48 | #endif |
49 | ||
144b2a91 HH |
50 | extern void iowrite8(u8, void __iomem *); |
51 | extern void iowrite16(u16, void __iomem *); | |
52 | extern void iowrite16be(u16, void __iomem *); | |
53 | extern void iowrite32(u32, void __iomem *); | |
54 | extern void iowrite32be(u32, void __iomem *); | |
9e44fb18 HG |
55 | #ifdef CONFIG_64BIT |
56 | extern void iowrite64(u64, void __iomem *); | |
57 | extern void iowrite64be(u64, void __iomem *); | |
58 | #endif | |
1da177e4 | 59 | |
79bf0cbd LG |
60 | #ifdef writeq |
61 | #define iowrite64_lo_hi iowrite64_lo_hi | |
62 | #define iowrite64_hi_lo iowrite64_hi_lo | |
63 | #define iowrite64be_lo_hi iowrite64be_lo_hi | |
64 | #define iowrite64be_hi_lo iowrite64be_hi_lo | |
65 | extern void iowrite64_lo_hi(u64 val, void __iomem *addr); | |
66 | extern void iowrite64_hi_lo(u64 val, void __iomem *addr); | |
67 | extern void iowrite64be_lo_hi(u64 val, void __iomem *addr); | |
68 | extern void iowrite64be_hi_lo(u64 val, void __iomem *addr); | |
69 | #endif | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * "string" versions of the above. Note that they | |
73 | * use native byte ordering for the accesses (on | |
74 | * the assumption that IO and memory agree on a | |
75 | * byte order, and CPU byteorder is irrelevant). | |
76 | * | |
77 | * They do _not_ update the port address. If you | |
78 | * want MMIO that copies stuff laid out in MMIO | |
79 | * memory across multiple ports, use "memcpy_toio()" | |
80 | * and friends. | |
81 | */ | |
8f28ca6b KK |
82 | extern void ioread8_rep(const void __iomem *port, void *buf, unsigned long count); |
83 | extern void ioread16_rep(const void __iomem *port, void *buf, unsigned long count); | |
84 | extern void ioread32_rep(const void __iomem *port, void *buf, unsigned long count); | |
1da177e4 | 85 | |
144b2a91 HH |
86 | extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count); |
87 | extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count); | |
88 | extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count); | |
1da177e4 | 89 | |
ce816fa8 | 90 | #ifdef CONFIG_HAS_IOPORT_MAP |
1da177e4 LT |
91 | /* Create a virtual mapping cookie for an IO port range */ |
92 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | |
93 | extern void ioport_unmap(void __iomem *); | |
82ed223c | 94 | #endif |
1da177e4 | 95 | |
1526a756 | 96 | #ifndef ARCH_HAS_IOREMAP_WC |
4bdc0d67 | 97 | #define ioremap_wc ioremap |
1526a756 | 98 | #endif |
99 | ||
d838270e | 100 | #ifndef ARCH_HAS_IOREMAP_WT |
4bdc0d67 | 101 | #define ioremap_wt ioremap |
d838270e TK |
102 | #endif |
103 | ||
7c566bb5 HM |
104 | #ifndef ARCH_HAS_IOREMAP_NP |
105 | /* See the comment in asm-generic/io.h about ioremap_np(). */ | |
106 | #define ioremap_np ioremap_np | |
107 | static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size) | |
108 | { | |
109 | return NULL; | |
110 | } | |
111 | #endif | |
112 | ||
66eab4df MT |
113 | #include <asm-generic/pci_iomap.h> |
114 | ||
1da177e4 | 115 | #endif |