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b4d0d230 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
93ea02bb | 2 | /* |
739d875d | 3 | * Generic barrier definitions. |
885df91c DH |
4 | * |
5 | * It should be possible to use these on really simple architectures, | |
6 | * but it serves more as a starting point for new ports. | |
7 | * | |
8 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | |
9 | * Written by David Howells (dhowells@redhat.com) | |
885df91c DH |
10 | */ |
11 | #ifndef __ASM_GENERIC_BARRIER_H | |
12 | #define __ASM_GENERIC_BARRIER_H | |
13 | ||
14 | #ifndef __ASSEMBLY__ | |
15 | ||
3347acc6 | 16 | #include <linux/compiler.h> |
f948666d | 17 | #include <linux/kcsan-checks.h> |
e506ea45 | 18 | #include <asm/rwonce.h> |
93ea02bb PZ |
19 | |
20 | #ifndef nop | |
21 | #define nop() asm volatile ("nop") | |
22 | #endif | |
885df91c | 23 | |
2505a51a ME |
24 | /* |
25 | * Architectures that want generic instrumentation can define __ prefixed | |
26 | * variants of all barriers. | |
27 | */ | |
28 | ||
29 | #ifdef __mb | |
30 | #define mb() do { kcsan_mb(); __mb(); } while (0) | |
31 | #endif | |
32 | ||
33 | #ifdef __rmb | |
34 | #define rmb() do { kcsan_rmb(); __rmb(); } while (0) | |
35 | #endif | |
36 | ||
37 | #ifdef __wmb | |
38 | #define wmb() do { kcsan_wmb(); __wmb(); } while (0) | |
39 | #endif | |
40 | ||
ed59dfd9 KW |
41 | #ifdef __dma_mb |
42 | #define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0) | |
43 | #endif | |
44 | ||
2505a51a ME |
45 | #ifdef __dma_rmb |
46 | #define dma_rmb() do { kcsan_rmb(); __dma_rmb(); } while (0) | |
47 | #endif | |
48 | ||
49 | #ifdef __dma_wmb | |
50 | #define dma_wmb() do { kcsan_wmb(); __dma_wmb(); } while (0) | |
51 | #endif | |
52 | ||
885df91c | 53 | /* |
93ea02bb PZ |
54 | * Force strict CPU ordering. And yes, this is required on UP too when we're |
55 | * talking to devices. | |
885df91c | 56 | * |
93ea02bb | 57 | * Fall back to compiler barriers if nothing better is provided. |
885df91c DH |
58 | */ |
59 | ||
93ea02bb PZ |
60 | #ifndef mb |
61 | #define mb() barrier() | |
62 | #endif | |
63 | ||
64 | #ifndef rmb | |
885df91c | 65 | #define rmb() mb() |
93ea02bb PZ |
66 | #endif |
67 | ||
68 | #ifndef wmb | |
69 | #define wmb() mb() | |
70 | #endif | |
71 | ||
ed59dfd9 KW |
72 | #ifndef dma_mb |
73 | #define dma_mb() mb() | |
74 | #endif | |
75 | ||
1077fa36 AD |
76 | #ifndef dma_rmb |
77 | #define dma_rmb() rmb() | |
78 | #endif | |
79 | ||
80 | #ifndef dma_wmb | |
81 | #define dma_wmb() wmb() | |
82 | #endif | |
83 | ||
a9e4252a MT |
84 | #ifndef __smp_mb |
85 | #define __smp_mb() mb() | |
86 | #endif | |
87 | ||
88 | #ifndef __smp_rmb | |
89 | #define __smp_rmb() rmb() | |
90 | #endif | |
91 | ||
92 | #ifndef __smp_wmb | |
93 | #define __smp_wmb() wmb() | |
94 | #endif | |
95 | ||
885df91c | 96 | #ifdef CONFIG_SMP |
470c27e4 VG |
97 | |
98 | #ifndef smp_mb | |
f948666d | 99 | #define smp_mb() do { kcsan_mb(); __smp_mb(); } while (0) |
470c27e4 VG |
100 | #endif |
101 | ||
102 | #ifndef smp_rmb | |
f948666d | 103 | #define smp_rmb() do { kcsan_rmb(); __smp_rmb(); } while (0) |
470c27e4 VG |
104 | #endif |
105 | ||
106 | #ifndef smp_wmb | |
f948666d | 107 | #define smp_wmb() do { kcsan_wmb(); __smp_wmb(); } while (0) |
470c27e4 VG |
108 | #endif |
109 | ||
0890a264 LT |
110 | #else /* !CONFIG_SMP */ |
111 | ||
470c27e4 | 112 | #ifndef smp_mb |
885df91c | 113 | #define smp_mb() barrier() |
470c27e4 VG |
114 | #endif |
115 | ||
116 | #ifndef smp_rmb | |
885df91c | 117 | #define smp_rmb() barrier() |
470c27e4 VG |
118 | #endif |
119 | ||
120 | #ifndef smp_wmb | |
885df91c | 121 | #define smp_wmb() barrier() |
470c27e4 VG |
122 | #endif |
123 | ||
0890a264 | 124 | #endif /* CONFIG_SMP */ |
470c27e4 | 125 | |
a9e4252a MT |
126 | #ifndef __smp_store_mb |
127 | #define __smp_store_mb(var, value) do { WRITE_ONCE(var, value); __smp_mb(); } while (0) | |
128 | #endif | |
129 | ||
130 | #ifndef __smp_mb__before_atomic | |
131 | #define __smp_mb__before_atomic() __smp_mb() | |
132 | #endif | |
133 | ||
134 | #ifndef __smp_mb__after_atomic | |
135 | #define __smp_mb__after_atomic() __smp_mb() | |
136 | #endif | |
137 | ||
138 | #ifndef __smp_store_release | |
139 | #define __smp_store_release(p, v) \ | |
140 | do { \ | |
141 | compiletime_assert_atomic_type(*p); \ | |
142 | __smp_mb(); \ | |
143 | WRITE_ONCE(*p, v); \ | |
144 | } while (0) | |
145 | #endif | |
146 | ||
147 | #ifndef __smp_load_acquire | |
148 | #define __smp_load_acquire(p) \ | |
149 | ({ \ | |
54988727 | 150 | __unqual_scalar_typeof(*p) ___p1 = READ_ONCE(*p); \ |
a9e4252a MT |
151 | compiletime_assert_atomic_type(*p); \ |
152 | __smp_mb(); \ | |
54988727 | 153 | (typeof(*p))___p1; \ |
a9e4252a MT |
154 | }) |
155 | #endif | |
156 | ||
157 | #ifdef CONFIG_SMP | |
158 | ||
159 | #ifndef smp_store_mb | |
f948666d | 160 | #define smp_store_mb(var, value) do { kcsan_mb(); __smp_store_mb(var, value); } while (0) |
a9e4252a MT |
161 | #endif |
162 | ||
163 | #ifndef smp_mb__before_atomic | |
f948666d | 164 | #define smp_mb__before_atomic() do { kcsan_mb(); __smp_mb__before_atomic(); } while (0) |
a9e4252a MT |
165 | #endif |
166 | ||
167 | #ifndef smp_mb__after_atomic | |
f948666d | 168 | #define smp_mb__after_atomic() do { kcsan_mb(); __smp_mb__after_atomic(); } while (0) |
a9e4252a MT |
169 | #endif |
170 | ||
171 | #ifndef smp_store_release | |
f948666d | 172 | #define smp_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0) |
a9e4252a MT |
173 | #endif |
174 | ||
175 | #ifndef smp_load_acquire | |
176 | #define smp_load_acquire(p) __smp_load_acquire(p) | |
177 | #endif | |
178 | ||
179 | #else /* !CONFIG_SMP */ | |
180 | ||
b92b8b35 | 181 | #ifndef smp_store_mb |
a9e4252a | 182 | #define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0) |
93ea02bb | 183 | #endif |
885df91c | 184 | |
febdbfe8 | 185 | #ifndef smp_mb__before_atomic |
a9e4252a | 186 | #define smp_mb__before_atomic() barrier() |
febdbfe8 PZ |
187 | #endif |
188 | ||
189 | #ifndef smp_mb__after_atomic | |
a9e4252a | 190 | #define smp_mb__after_atomic() barrier() |
febdbfe8 PZ |
191 | #endif |
192 | ||
57f7c037 | 193 | #ifndef smp_store_release |
47933ad4 PZ |
194 | #define smp_store_release(p, v) \ |
195 | do { \ | |
196 | compiletime_assert_atomic_type(*p); \ | |
a9e4252a | 197 | barrier(); \ |
76695af2 | 198 | WRITE_ONCE(*p, v); \ |
47933ad4 | 199 | } while (0) |
57f7c037 | 200 | #endif |
47933ad4 | 201 | |
57f7c037 | 202 | #ifndef smp_load_acquire |
47933ad4 PZ |
203 | #define smp_load_acquire(p) \ |
204 | ({ \ | |
54988727 | 205 | __unqual_scalar_typeof(*p) ___p1 = READ_ONCE(*p); \ |
47933ad4 | 206 | compiletime_assert_atomic_type(*p); \ |
a9e4252a | 207 | barrier(); \ |
54988727 | 208 | (typeof(*p))___p1; \ |
47933ad4 | 209 | }) |
57f7c037 | 210 | #endif |
47933ad4 | 211 | |
726328d9 | 212 | #endif /* CONFIG_SMP */ |
a9e4252a | 213 | |
6a65d263 | 214 | /* Barriers for virtual machine guests when talking to an SMP host */ |
f948666d ME |
215 | #define virt_mb() do { kcsan_mb(); __smp_mb(); } while (0) |
216 | #define virt_rmb() do { kcsan_rmb(); __smp_rmb(); } while (0) | |
217 | #define virt_wmb() do { kcsan_wmb(); __smp_wmb(); } while (0) | |
218 | #define virt_store_mb(var, value) do { kcsan_mb(); __smp_store_mb(var, value); } while (0) | |
219 | #define virt_mb__before_atomic() do { kcsan_mb(); __smp_mb__before_atomic(); } while (0) | |
220 | #define virt_mb__after_atomic() do { kcsan_mb(); __smp_mb__after_atomic(); } while (0) | |
221 | #define virt_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0) | |
6a65d263 MT |
222 | #define virt_load_acquire(p) __smp_load_acquire(p) |
223 | ||
7cb45c0f PZ |
224 | /** |
225 | * smp_acquire__after_ctrl_dep() - Provide ACQUIRE ordering after a control dependency | |
226 | * | |
227 | * A control dependency provides a LOAD->STORE order, the additional RMB | |
228 | * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order, | |
229 | * aka. (load)-ACQUIRE. | |
230 | * | |
231 | * Architectures that do not do load speculation can have this be barrier(). | |
232 | */ | |
233 | #ifndef smp_acquire__after_ctrl_dep | |
234 | #define smp_acquire__after_ctrl_dep() smp_rmb() | |
235 | #endif | |
236 | ||
237 | /** | |
fcfdfe30 | 238 | * smp_cond_load_relaxed() - (Spin) wait for cond with no ordering guarantees |
7cb45c0f PZ |
239 | * @ptr: pointer to the variable to wait on |
240 | * @cond: boolean expression to wait for | |
241 | * | |
fcfdfe30 | 242 | * Equivalent to using READ_ONCE() on the condition variable. |
7cb45c0f PZ |
243 | * |
244 | * Due to C lacking lambda expressions we load the value of *ptr into a | |
245 | * pre-named variable @VAL to be used in @cond. | |
246 | */ | |
fcfdfe30 WD |
247 | #ifndef smp_cond_load_relaxed |
248 | #define smp_cond_load_relaxed(ptr, cond_expr) ({ \ | |
7cb45c0f | 249 | typeof(ptr) __PTR = (ptr); \ |
54988727 | 250 | __unqual_scalar_typeof(*ptr) VAL; \ |
7cb45c0f PZ |
251 | for (;;) { \ |
252 | VAL = READ_ONCE(*__PTR); \ | |
253 | if (cond_expr) \ | |
254 | break; \ | |
255 | cpu_relax(); \ | |
256 | } \ | |
54988727 | 257 | (typeof(*ptr))VAL; \ |
7cb45c0f PZ |
258 | }) |
259 | #endif | |
260 | ||
fcfdfe30 WD |
261 | /** |
262 | * smp_cond_load_acquire() - (Spin) wait for cond with ACQUIRE ordering | |
263 | * @ptr: pointer to the variable to wait on | |
264 | * @cond: boolean expression to wait for | |
265 | * | |
266 | * Equivalent to using smp_load_acquire() on the condition variable but employs | |
267 | * the control dependency of the wait to reduce the barrier on many platforms. | |
268 | */ | |
269 | #ifndef smp_cond_load_acquire | |
270 | #define smp_cond_load_acquire(ptr, cond_expr) ({ \ | |
54988727 | 271 | __unqual_scalar_typeof(*ptr) _val; \ |
fcfdfe30 WD |
272 | _val = smp_cond_load_relaxed(ptr, cond_expr); \ |
273 | smp_acquire__after_ctrl_dep(); \ | |
54988727 | 274 | (typeof(*ptr))_val; \ |
fcfdfe30 WD |
275 | }) |
276 | #endif | |
277 | ||
3e79f082 AK |
278 | /* |
279 | * pmem_wmb() ensures that all stores for which the modification | |
280 | * are written to persistent storage by preceding instructions have | |
281 | * updated persistent storage before any data access or data transfer | |
282 | * caused by subsequent instructions is initiated. | |
283 | */ | |
284 | #ifndef pmem_wmb | |
285 | #define pmem_wmb() wmb() | |
286 | #endif | |
287 | ||
d5624bb2 XW |
288 | /* |
289 | * ioremap_wc() maps I/O memory as memory with write-combining attributes. For | |
290 | * this kind of memory accesses, the CPU may wait for prior accesses to be | |
291 | * merged with subsequent ones. In some situation, such wait is bad for the | |
292 | * performance. io_stop_wc() can be used to prevent the merging of | |
293 | * write-combining memory accesses before this macro with those after it. | |
294 | */ | |
295 | #ifndef io_stop_wc | |
440323b6 | 296 | #define io_stop_wc() do { } while (0) |
d5624bb2 XW |
297 | #endif |
298 | ||
885df91c DH |
299 | #endif /* !__ASSEMBLY__ */ |
300 | #endif /* __ASM_GENERIC_BARRIER_H */ |