Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* bitops.h: bit operations for the Fujitsu FR-V CPUs |
2 | * | |
3 | * For an explanation of how atomic ops work in this arch, see: | |
0868ff7a | 4 | * Documentation/frv/atomic-ops.txt |
1da177e4 LT |
5 | * |
6 | * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. | |
7 | * Written by David Howells (dhowells@redhat.com) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | #ifndef _ASM_BITOPS_H | |
15 | #define _ASM_BITOPS_H | |
16 | ||
1da177e4 LT |
17 | #include <linux/compiler.h> |
18 | #include <asm/byteorder.h> | |
1da177e4 LT |
19 | |
20 | #ifdef __KERNEL__ | |
21 | ||
0624517d JS |
22 | #ifndef _LINUX_BITOPS_H |
23 | #error only <linux/bitops.h> can be included directly | |
24 | #endif | |
25 | ||
1f6d7a93 | 26 | #include <asm-generic/bitops/ffz.h> |
1da177e4 LT |
27 | |
28 | /* | |
29 | * clear_bit() doesn't provide any barrier for the compiler. | |
30 | */ | |
31 | #define smp_mb__before_clear_bit() barrier() | |
32 | #define smp_mb__after_clear_bit() barrier() | |
33 | ||
6784fd59 MD |
34 | #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS |
35 | static inline | |
36 | unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v) | |
37 | { | |
38 | unsigned long old, tmp; | |
39 | ||
40 | asm volatile( | |
41 | "0: \n" | |
42 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | |
43 | " ckeq icc3,cc7 \n" | |
44 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | |
45 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | |
46 | " and%I3 %1,%3,%2 \n" | |
47 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | |
48 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | |
49 | " beq icc3,#0,0b \n" | |
50 | : "+U"(*v), "=&r"(old), "=r"(tmp) | |
51 | : "NPr"(~mask) | |
52 | : "memory", "cc7", "cc3", "icc3" | |
53 | ); | |
54 | ||
55 | return old; | |
56 | } | |
57 | ||
58 | static inline | |
59 | unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v) | |
60 | { | |
61 | unsigned long old, tmp; | |
62 | ||
63 | asm volatile( | |
64 | "0: \n" | |
65 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | |
66 | " ckeq icc3,cc7 \n" | |
67 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | |
68 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | |
69 | " or%I3 %1,%3,%2 \n" | |
70 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | |
71 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | |
72 | " beq icc3,#0,0b \n" | |
73 | : "+U"(*v), "=&r"(old), "=r"(tmp) | |
74 | : "NPr"(mask) | |
75 | : "memory", "cc7", "cc3", "icc3" | |
76 | ); | |
77 | ||
78 | return old; | |
79 | } | |
80 | ||
81 | static inline | |
82 | unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v) | |
83 | { | |
84 | unsigned long old, tmp; | |
85 | ||
86 | asm volatile( | |
87 | "0: \n" | |
88 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | |
89 | " ckeq icc3,cc7 \n" | |
90 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | |
91 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | |
92 | " xor%I3 %1,%3,%2 \n" | |
93 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | |
94 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | |
95 | " beq icc3,#0,0b \n" | |
96 | : "+U"(*v), "=&r"(old), "=r"(tmp) | |
97 | : "NPr"(mask) | |
98 | : "memory", "cc7", "cc3", "icc3" | |
99 | ); | |
100 | ||
101 | return old; | |
102 | } | |
103 | ||
104 | #else | |
105 | ||
106 | extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v); | |
107 | extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v); | |
108 | extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v); | |
109 | ||
110 | #endif | |
111 | ||
112 | #define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v)) | |
113 | #define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v)) | |
114 | ||
1da177e4 LT |
115 | static inline int test_and_clear_bit(int nr, volatile void *addr) |
116 | { | |
117 | volatile unsigned long *ptr = addr; | |
118 | unsigned long mask = 1UL << (nr & 31); | |
119 | ptr += nr >> 5; | |
120 | return (atomic_test_and_ANDNOT_mask(mask, ptr) & mask) != 0; | |
121 | } | |
122 | ||
123 | static inline int test_and_set_bit(int nr, volatile void *addr) | |
124 | { | |
125 | volatile unsigned long *ptr = addr; | |
126 | unsigned long mask = 1UL << (nr & 31); | |
127 | ptr += nr >> 5; | |
128 | return (atomic_test_and_OR_mask(mask, ptr) & mask) != 0; | |
129 | } | |
130 | ||
131 | static inline int test_and_change_bit(int nr, volatile void *addr) | |
132 | { | |
133 | volatile unsigned long *ptr = addr; | |
134 | unsigned long mask = 1UL << (nr & 31); | |
135 | ptr += nr >> 5; | |
136 | return (atomic_test_and_XOR_mask(mask, ptr) & mask) != 0; | |
137 | } | |
138 | ||
139 | static inline void clear_bit(int nr, volatile void *addr) | |
140 | { | |
141 | test_and_clear_bit(nr, addr); | |
142 | } | |
143 | ||
144 | static inline void set_bit(int nr, volatile void *addr) | |
145 | { | |
146 | test_and_set_bit(nr, addr); | |
147 | } | |
148 | ||
149 | static inline void change_bit(int nr, volatile void * addr) | |
150 | { | |
151 | test_and_change_bit(nr, addr); | |
152 | } | |
153 | ||
154 | static inline void __clear_bit(int nr, volatile void * addr) | |
155 | { | |
156 | volatile unsigned long *a = addr; | |
157 | int mask; | |
158 | ||
159 | a += nr >> 5; | |
160 | mask = 1 << (nr & 31); | |
161 | *a &= ~mask; | |
162 | } | |
163 | ||
164 | static inline void __set_bit(int nr, volatile void * addr) | |
165 | { | |
166 | volatile unsigned long *a = addr; | |
167 | int mask; | |
168 | ||
169 | a += nr >> 5; | |
170 | mask = 1 << (nr & 31); | |
171 | *a |= mask; | |
172 | } | |
173 | ||
174 | static inline void __change_bit(int nr, volatile void *addr) | |
175 | { | |
176 | volatile unsigned long *a = addr; | |
177 | int mask; | |
178 | ||
179 | a += nr >> 5; | |
180 | mask = 1 << (nr & 31); | |
181 | *a ^= mask; | |
182 | } | |
183 | ||
184 | static inline int __test_and_clear_bit(int nr, volatile void * addr) | |
185 | { | |
186 | volatile unsigned long *a = addr; | |
187 | int mask, retval; | |
188 | ||
189 | a += nr >> 5; | |
190 | mask = 1 << (nr & 31); | |
191 | retval = (mask & *a) != 0; | |
192 | *a &= ~mask; | |
193 | return retval; | |
194 | } | |
195 | ||
196 | static inline int __test_and_set_bit(int nr, volatile void * addr) | |
197 | { | |
198 | volatile unsigned long *a = addr; | |
199 | int mask, retval; | |
200 | ||
201 | a += nr >> 5; | |
202 | mask = 1 << (nr & 31); | |
203 | retval = (mask & *a) != 0; | |
204 | *a |= mask; | |
205 | return retval; | |
206 | } | |
207 | ||
208 | static inline int __test_and_change_bit(int nr, volatile void * addr) | |
209 | { | |
210 | volatile unsigned long *a = addr; | |
211 | int mask, retval; | |
212 | ||
213 | a += nr >> 5; | |
214 | mask = 1 << (nr & 31); | |
215 | retval = (mask & *a) != 0; | |
216 | *a ^= mask; | |
217 | return retval; | |
218 | } | |
219 | ||
220 | /* | |
221 | * This routine doesn't need to be atomic. | |
222 | */ | |
223 | static inline int __constant_test_bit(int nr, const volatile void * addr) | |
224 | { | |
225 | return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; | |
226 | } | |
227 | ||
228 | static inline int __test_bit(int nr, const volatile void * addr) | |
229 | { | |
230 | int * a = (int *) addr; | |
231 | int mask; | |
232 | ||
233 | a += nr >> 5; | |
234 | mask = 1 << (nr & 0x1f); | |
235 | return ((mask & *a) != 0); | |
236 | } | |
237 | ||
238 | #define test_bit(nr,addr) \ | |
239 | (__builtin_constant_p(nr) ? \ | |
240 | __constant_test_bit((nr),(addr)) : \ | |
241 | __test_bit((nr),(addr))) | |
242 | ||
1f6d7a93 | 243 | #include <asm-generic/bitops/find.h> |
1da177e4 | 244 | |
92fc7072 DH |
245 | /** |
246 | * fls - find last bit set | |
247 | * @x: the word to search | |
248 | * | |
249 | * This is defined the same way as ffs: | |
250 | * - return 32..1 to indicate bit 31..0 most significant bit set | |
251 | * - return 0 to indicate no bits set | |
1da177e4 LT |
252 | */ |
253 | #define fls(x) \ | |
254 | ({ \ | |
255 | int bit; \ | |
256 | \ | |
92fc7072 DH |
257 | asm(" subcc %1,gr0,gr0,icc0 \n" \ |
258 | " ckne icc0,cc4 \n" \ | |
259 | " cscan.p %1,gr0,%0 ,cc4,#1 \n" \ | |
260 | " csub %0,%0,%0 ,cc4,#0 \n" \ | |
261 | " csub %2,%0,%0 ,cc4,#1 \n" \ | |
262 | : "=&r"(bit) \ | |
263 | : "r"(x), "r"(32) \ | |
264 | : "icc0", "cc4" \ | |
265 | ); \ | |
1da177e4 | 266 | \ |
92fc7072 | 267 | bit; \ |
1da177e4 LT |
268 | }) |
269 | ||
a8ad27d0 DH |
270 | /** |
271 | * fls64 - find last bit set in a 64-bit value | |
272 | * @n: the value to search | |
273 | * | |
274 | * This is defined the same way as ffs: | |
275 | * - return 64..1 to indicate bit 63..0 most significant bit set | |
276 | * - return 0 to indicate no bits set | |
277 | */ | |
278 | static inline __attribute__((const)) | |
279 | int fls64(u64 n) | |
280 | { | |
281 | union { | |
282 | u64 ll; | |
283 | struct { u32 h, l; }; | |
284 | } _; | |
285 | int bit, x, y; | |
286 | ||
287 | _.ll = n; | |
288 | ||
289 | asm(" subcc.p %3,gr0,gr0,icc0 \n" | |
290 | " subcc %4,gr0,gr0,icc1 \n" | |
291 | " ckne icc0,cc4 \n" | |
292 | " ckne icc1,cc5 \n" | |
293 | " norcr cc4,cc5,cc6 \n" | |
294 | " csub.p %0,%0,%0 ,cc6,1 \n" | |
295 | " orcr cc5,cc4,cc4 \n" | |
296 | " andcr cc4,cc5,cc4 \n" | |
297 | " cscan.p %3,gr0,%0 ,cc4,0 \n" | |
298 | " setlos #64,%1 \n" | |
299 | " cscan.p %4,gr0,%0 ,cc4,1 \n" | |
300 | " setlos #32,%2 \n" | |
301 | " csub.p %1,%0,%0 ,cc4,0 \n" | |
302 | " csub %2,%0,%0 ,cc4,1 \n" | |
303 | : "=&r"(bit), "=r"(x), "=r"(y) | |
304 | : "0r"(_.h), "r"(_.l) | |
305 | : "icc0", "icc1", "cc4", "cc5", "cc6" | |
306 | ); | |
307 | return bit; | |
308 | ||
309 | } | |
310 | ||
cf134483 DH |
311 | /** |
312 | * ffs - find first bit set | |
313 | * @x: the word to search | |
314 | * | |
315 | * - return 32..1 to indicate bit 31..0 most least significant bit set | |
316 | * - return 0 to indicate no bits set | |
317 | */ | |
318 | static inline __attribute__((const)) | |
319 | int ffs(int x) | |
320 | { | |
321 | /* Note: (x & -x) gives us a mask that is the least significant | |
322 | * (rightmost) 1-bit of the value in x. | |
323 | */ | |
324 | return fls(x & -x); | |
325 | } | |
326 | ||
327 | /** | |
328 | * __ffs - find first bit set | |
329 | * @x: the word to search | |
330 | * | |
331 | * - return 31..0 to indicate bit 31..0 most least significant bit set | |
332 | * - if no bits are set in x, the result is undefined | |
333 | */ | |
334 | static inline __attribute__((const)) | |
335 | int __ffs(unsigned long x) | |
336 | { | |
337 | int bit; | |
338 | asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x)); | |
339 | return 31 - bit; | |
340 | } | |
341 | ||
f0d1b0b3 DH |
342 | /* |
343 | * special slimline version of fls() for calculating ilog2_u32() | |
344 | * - note: no protection against n == 0 | |
345 | */ | |
346 | #define ARCH_HAS_ILOG2_U32 | |
347 | static inline __attribute__((const)) | |
348 | int __ilog2_u32(u32 n) | |
349 | { | |
350 | int bit; | |
351 | asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n)); | |
352 | return 31 - bit; | |
353 | } | |
354 | ||
355 | /* | |
356 | * special slimline version of fls64() for calculating ilog2_u64() | |
357 | * - note: no protection against n == 0 | |
358 | */ | |
359 | #define ARCH_HAS_ILOG2_U64 | |
360 | static inline __attribute__((const)) | |
361 | int __ilog2_u64(u64 n) | |
362 | { | |
363 | union { | |
364 | u64 ll; | |
365 | struct { u32 h, l; }; | |
366 | } _; | |
367 | int bit, x, y; | |
368 | ||
369 | _.ll = n; | |
370 | ||
371 | asm(" subcc %3,gr0,gr0,icc0 \n" | |
372 | " ckeq icc0,cc4 \n" | |
373 | " cscan.p %3,gr0,%0 ,cc4,0 \n" | |
374 | " setlos #63,%1 \n" | |
375 | " cscan.p %4,gr0,%0 ,cc4,1 \n" | |
376 | " setlos #31,%2 \n" | |
377 | " csub.p %1,%0,%0 ,cc4,0 \n" | |
378 | " csub %2,%0,%0 ,cc4,1 \n" | |
379 | : "=&r"(bit), "=r"(x), "=r"(y) | |
380 | : "0r"(_.h), "r"(_.l) | |
381 | : "icc0", "cc4" | |
382 | ); | |
383 | return bit; | |
384 | } | |
385 | ||
1f6d7a93 AM |
386 | #include <asm-generic/bitops/sched.h> |
387 | #include <asm-generic/bitops/hweight.h> | |
26333576 | 388 | #include <asm-generic/bitops/lock.h> |
1da177e4 | 389 | |
1f6d7a93 | 390 | #include <asm-generic/bitops/ext2-non-atomic.h> |
1da177e4 | 391 | |
67b0ad57 AM |
392 | #define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit ((nr) ^ 0x18, (addr)) |
393 | #define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr) ^ 0x18, (addr)) | |
1da177e4 | 394 | |
1f6d7a93 | 395 | #include <asm-generic/bitops/minix-le.h> |
1da177e4 LT |
396 | |
397 | #endif /* __KERNEL__ */ | |
398 | ||
399 | #endif /* _ASM_BITOPS_H */ |