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1 | /* |
2 | * linux/include/asm/traps.h | |
3 | * | |
4 | * Copyright (C) 1993 Hamish Macdonald | |
5 | * | |
6 | * Lineo, Inc Jul 2001 Tony Kou | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file COPYING in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #ifndef _BFIN_TRAPS_H | |
14 | #define _BFIN_TRAPS_H | |
15 | ||
16 | #define VEC_SYS (0) | |
17 | #define VEC_EXCPT01 (1) | |
18 | #define VEC_EXCPT02 (2) | |
19 | #define VEC_EXCPT03 (3) | |
20 | #define VEC_EXCPT04 (4) | |
21 | #define VEC_EXCPT05 (5) | |
22 | #define VEC_EXCPT06 (6) | |
23 | #define VEC_EXCPT07 (7) | |
24 | #define VEC_EXCPT08 (8) | |
25 | #define VEC_EXCPT09 (9) | |
26 | #define VEC_EXCPT10 (10) | |
27 | #define VEC_EXCPT11 (11) | |
28 | #define VEC_EXCPT12 (12) | |
29 | #define VEC_EXCPT13 (13) | |
30 | #define VEC_EXCPT14 (14) | |
31 | #define VEC_EXCPT15 (15) | |
32 | #define VEC_STEP (16) | |
33 | #define VEC_OVFLOW (17) | |
34 | #define VEC_UNDEF_I (33) | |
35 | #define VEC_ILGAL_I (34) | |
36 | #define VEC_CPLB_VL (35) | |
37 | #define VEC_MISALI_D (36) | |
38 | #define VEC_UNCOV (37) | |
39 | #define VEC_CPLB_M (38) | |
40 | #define VEC_CPLB_MHIT (39) | |
41 | #define VEC_WATCH (40) | |
42 | #define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */ | |
43 | #define VEC_MISALI_I (42) | |
44 | #define VEC_CPLB_I_VL (43) | |
45 | #define VEC_CPLB_I_M (44) | |
46 | #define VEC_CPLB_I_MHIT (45) | |
47 | #define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ | |
48 | ||
49 | #ifndef __ASSEMBLY__ | |
50 | ||
569a50ca RG |
51 | #define HWC_x2(level) \ |
52 | "System MMR Error\n" \ | |
53 | level " - An error occurred due to an invalid access to an System MMR location\n" \ | |
54 | level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \ | |
55 | level " or a 16-bit register is accessed with a 32-bit instruction.\n" | |
56 | #define HWC_x3(level) \ | |
57 | "External Memory Addressing Error\n" | |
58 | #define HWC_x12(level) \ | |
59 | "Performance Monitor Overflow\n" | |
60 | #define HWC_x18(level) \ | |
61 | "RAISE 5 instruction\n" \ | |
62 | level " Software issued a RAISE 5 instruction to invoke the Hardware\n" | |
63 | #define HWC_default(level) \ | |
64 | "Reserved\n" | |
65 | #define EXC_0x03(level) \ | |
66 | "Application stack overflow\n" \ | |
67 | level " - Please increase the stack size of the application using elf2flt -s option,\n" \ | |
68 | level " and/or reduce the stack use of the application.\n" | |
69 | #define EXC_0x10(level) \ | |
70 | "Single step\n" \ | |
71 | level " - When the processor is in single step mode, every instruction\n" \ | |
72 | level " generates an exception. Primarily used for debugging.\n" | |
73 | #define EXC_0x11(level) \ | |
74 | "Exception caused by a trace buffer full condition\n" \ | |
75 | level " - The processor takes this exception when the trace\n" \ | |
76 | level " buffer overflows (only when enabled by the Trace Unit Control register).\n" | |
77 | #define EXC_0x21(level) \ | |
78 | "Undefined instruction\n" \ | |
79 | level " - May be used to emulate instructions that are not defined for\n" \ | |
80 | level " a particular processor implementation.\n" | |
81 | #define EXC_0x22(level) \ | |
82 | "Illegal instruction combination\n" \ | |
83 | level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \ | |
84 | level " Processor Instruction Set Reference.\n" | |
85 | #define EXC_0x23(level) \ | |
86 | "Data access CPLB protection violation\n" \ | |
87 | level " - Attempted read or write to Supervisor resource,\n" \ | |
88 | level " or illegal data memory access. \n" | |
89 | #define EXC_0x24(level) \ | |
90 | "Data access misaligned address violation\n" \ | |
91 | level " - Attempted misaligned data memory or data cache access.\n" | |
92 | #define EXC_0x25(level) \ | |
93 | "Unrecoverable event\n" \ | |
94 | level " - For example, an exception generated while processing a previous exception.\n" | |
95 | #define EXC_0x26(level) \ | |
96 | "Data access CPLB miss\n" \ | |
97 | level " - Used by the MMU to signal a CPLB miss on a data access.\n" | |
98 | #define EXC_0x27(level) \ | |
99 | "Data access multiple CPLB hits\n" \ | |
100 | level " - More than one CPLB entry matches data fetch address.\n" | |
101 | #define EXC_0x28(level) \ | |
102 | "Program Sequencer Exception caused by an emulation watchpoint match\n" \ | |
103 | level " - There is a watchpoint match, and one of the EMUSW\n" \ | |
104 | level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" | |
105 | #define EXC_0x2A(level) \ | |
106 | "Instruction fetch misaligned address violation\n" \ | |
107 | level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ | |
108 | level " exception, the return address provided in RETX is the destination address which is\n" \ | |
109 | level " misaligned, rather than the address of the offending instruction.\n" | |
110 | #define EXC_0x2B(level) \ | |
111 | "CPLB protection violation\n" \ | |
112 | level " - Illegal instruction fetch access (memory protection violation).\n" | |
113 | #define EXC_0x2C(level) \ | |
114 | "Instruction fetch CPLB miss\n" \ | |
115 | level " - CPLB miss on an instruction fetch.\n" | |
116 | #define EXC_0x2D(level) \ | |
117 | "Instruction fetch multiple CPLB hits\n" \ | |
118 | level " - More than one CPLB entry matches instruction fetch address.\n" | |
119 | #define EXC_0x2E(level) \ | |
120 | "Illegal use of supervisor resource\n" \ | |
121 | level " - Attempted to use a Supervisor register or instruction from User mode.\n" \ | |
122 | level " Supervisor resources are registers and instructions that are reserved\n" \ | |
123 | level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ | |
124 | level " only instructions.\n" | |
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125 | |
126 | #endif /* __ASSEMBLY__ */ | |
127 | #endif /* _BFIN_TRAPS_H */ |