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1 | /************************************************************************ |
2 | * | |
3 | * This file is subject to the terms and conditions of the GNU Public | |
4 | * License. See the file "COPYING" in the main directory of this archive | |
5 | * for more details. | |
6 | * | |
7 | * Non-GPL License also available as part of VisualDSP++ | |
8 | * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html | |
9 | * | |
10 | * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved | |
11 | * | |
12 | * This file under source code control, please send bugs or changes to: | |
13 | * dsptools.support@analog.com | |
14 | * | |
15 | ************************************************************************/ | |
16 | /* | |
17 | * File: include/asm-blackfin/mach-bf533/defBF532.h | |
18 | * Based on: | |
19 | * Author: | |
20 | * | |
21 | * Created: | |
22 | * Description: | |
23 | * | |
24 | * Rev: | |
25 | * | |
26 | * Modified: | |
27 | * | |
28 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
29 | * | |
30 | * This program is free software; you can redistribute it and/or modify | |
31 | * it under the terms of the GNU General Public License as published by | |
32 | * the Free Software Foundation; either version 2, or (at your option) | |
33 | * any later version. | |
34 | * | |
35 | * This program is distributed in the hope that it will be useful, | |
36 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
37 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
38 | * GNU General Public License for more details. | |
39 | * | |
40 | * You should have received a copy of the GNU General Public License | |
41 | * along with this program; see the file COPYING. | |
42 | * If not, write to the Free Software Foundation, | |
43 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
44 | */ | |
45 | /* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ | |
46 | ||
47 | #ifndef _DEF_BF532_H | |
48 | #define _DEF_BF532_H | |
19381f02 | 49 | |
1394f032 BW |
50 | /* include all Core registers and bit definitions */ |
51 | #include <asm/mach-common/def_LPBlackfin.h> | |
52 | ||
53 | /*********************************************************************************** */ | |
54 | /* System MMR Register Map */ | |
55 | /*********************************************************************************** */ | |
56 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | |
57 | ||
58 | #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ | |
59 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ | |
60 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ | |
61 | #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ | |
62 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ | |
63 | #define CHIPID 0xFFC00014 /* Chip ID Register */ | |
1394f032 BW |
64 | |
65 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | |
19381f02 BW |
66 | #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ |
67 | #define SYSCR 0xFFC00104 /* System Configuration registe */ | |
1394f032 BW |
68 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ |
69 | #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ | |
70 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | |
71 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | |
72 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | |
73 | #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ | |
74 | #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ | |
75 | ||
76 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | |
77 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ | |
78 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ | |
79 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ | |
80 | ||
81 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | |
82 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ | |
83 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ | |
84 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ | |
85 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ | |
86 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ | |
87 | #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ | |
88 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ | |
89 | ||
90 | /* UART Controller (0xFFC00400 - 0xFFC004FF) */ | |
6ed83942 GY |
91 | |
92 | /* | |
93 | * Because include/linux/serial_reg.h have defined UART_*, | |
94 | * So we define blackfin uart regs to BFIN_UART_*. | |
95 | */ | |
96 | #define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ | |
97 | #define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ | |
98 | #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | |
99 | #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ | |
100 | #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | |
101 | #define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ | |
102 | #define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ | |
103 | #define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ | |
104 | #define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ | |
1394f032 | 105 | #if 0 |
6ed83942 | 106 | #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ |
1394f032 | 107 | #endif |
6ed83942 GY |
108 | #define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ |
109 | #define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ | |
1394f032 BW |
110 | |
111 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ | |
1d487f46 | 112 | #define SPI0_REGBASE 0xFFC00500 |
1394f032 BW |
113 | #define SPI_CTL 0xFFC00500 /* SPI Control Register */ |
114 | #define SPI_FLG 0xFFC00504 /* SPI Flag register */ | |
115 | #define SPI_STAT 0xFFC00508 /* SPI Status register */ | |
116 | #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | |
117 | #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | |
118 | #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ | |
119 | #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | |
120 | ||
121 | /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ | |
122 | ||
123 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ | |
124 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ | |
125 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ | |
126 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ | |
127 | ||
128 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ | |
129 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ | |
130 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ | |
131 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ | |
132 | ||
133 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ | |
134 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ | |
135 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ | |
136 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ | |
137 | ||
138 | #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ | |
139 | #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ | |
140 | #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ | |
141 | ||
142 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ | |
143 | ||
144 | #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ | |
145 | #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ | |
146 | #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ | |
147 | #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ | |
148 | #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ | |
149 | #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ | |
150 | #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ | |
151 | #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ | |
152 | #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ | |
153 | #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ | |
154 | #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ | |
155 | #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ | |
156 | #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ | |
157 | #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ | |
158 | #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ | |
159 | #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ | |
160 | #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ | |
161 | ||
162 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | |
163 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | |
164 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | |
165 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | |
166 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | |
167 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | |
168 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | |
169 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | |
170 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | |
171 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | |
172 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | |
173 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | |
174 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | |
175 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | |
176 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | |
177 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | |
178 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | |
179 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | |
180 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | |
181 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | |
182 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | |
183 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | |
184 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | |
185 | ||
186 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | |
187 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | |
188 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | |
189 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | |
190 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | |
191 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | |
192 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | |
193 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | |
194 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | |
195 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | |
196 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | |
197 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | |
198 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | |
199 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | |
200 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | |
201 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | |
202 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | |
203 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | |
204 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | |
205 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | |
206 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | |
207 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | |
208 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | |
209 | ||
210 | /* Asynchronous Memory Controller - External Bus Interface Unit */ | |
211 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | |
212 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | |
213 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | |
214 | ||
215 | /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | |
216 | ||
217 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | |
218 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | |
219 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | |
220 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | |
221 | ||
222 | /* DMA Traffic controls */ | |
1394f032 BW |
223 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
224 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | |
225 | ||
19381f02 BW |
226 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
227 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ | |
228 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | |
229 | ||
1394f032 BW |
230 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ |
231 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | |
232 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | |
233 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ | |
234 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ | |
235 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ | |
236 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ | |
237 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ | |
238 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ | |
239 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ | |
240 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ | |
241 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ | |
242 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ | |
243 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ | |
244 | ||
245 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ | |
246 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ | |
247 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ | |
248 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ | |
249 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ | |
250 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ | |
251 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ | |
252 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ | |
253 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ | |
254 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ | |
255 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ | |
256 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ | |
257 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ | |
258 | ||
259 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ | |
260 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ | |
261 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ | |
262 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ | |
263 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ | |
264 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ | |
265 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ | |
266 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ | |
267 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ | |
268 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ | |
269 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ | |
270 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ | |
271 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ | |
272 | ||
273 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ | |
274 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ | |
275 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ | |
276 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ | |
277 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ | |
278 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ | |
279 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ | |
280 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ | |
281 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ | |
282 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ | |
283 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ | |
284 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ | |
285 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ | |
286 | ||
287 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ | |
288 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ | |
289 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ | |
290 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ | |
291 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ | |
292 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ | |
293 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ | |
294 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ | |
295 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ | |
296 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ | |
297 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ | |
298 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ | |
299 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ | |
300 | ||
301 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ | |
302 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ | |
303 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ | |
304 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ | |
305 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ | |
306 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ | |
307 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ | |
308 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ | |
309 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ | |
310 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ | |
311 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ | |
312 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ | |
313 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ | |
314 | ||
315 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ | |
316 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ | |
317 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ | |
318 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ | |
319 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ | |
320 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ | |
321 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ | |
322 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ | |
323 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ | |
324 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ | |
325 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ | |
326 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ | |
327 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ | |
328 | ||
329 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ | |
330 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ | |
331 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ | |
332 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ | |
333 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ | |
334 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ | |
335 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ | |
336 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ | |
337 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ | |
338 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ | |
339 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ | |
340 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ | |
341 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ | |
342 | ||
343 | #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ | |
344 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ | |
345 | #define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ | |
346 | #define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ | |
347 | #define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ | |
348 | #define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ | |
349 | #define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ | |
350 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ | |
351 | #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ | |
352 | #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ | |
353 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ | |
354 | #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ | |
355 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ | |
356 | ||
357 | #define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ | |
358 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ | |
359 | #define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ | |
360 | #define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ | |
361 | #define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ | |
362 | #define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ | |
363 | #define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ | |
364 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ | |
365 | #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ | |
366 | #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ | |
367 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ | |
368 | #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ | |
369 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ | |
370 | ||
371 | #define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ | |
372 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ | |
373 | #define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ | |
374 | #define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ | |
375 | #define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ | |
376 | #define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ | |
377 | #define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ | |
378 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ | |
379 | #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ | |
380 | #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ | |
381 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ | |
382 | #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ | |
383 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ | |
384 | ||
385 | #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ | |
386 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ | |
387 | #define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ | |
388 | #define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ | |
389 | #define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ | |
390 | #define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ | |
391 | #define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ | |
392 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ | |
393 | #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ | |
394 | #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ | |
395 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ | |
396 | #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ | |
397 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ | |
398 | ||
399 | /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ | |
400 | ||
401 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | |
402 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ | |
403 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ | |
404 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ | |
405 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ | |
406 | ||
407 | /*********************************************************************************** */ | |
408 | /* System MMR Register Bits */ | |
409 | /******************************************************************************* */ | |
410 | ||
411 | /* ********************* PLL AND RESET MASKS ************************ */ | |
412 | ||
413 | /* PLL_CTL Masks */ | |
19381f02 BW |
414 | #define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */ |
415 | #define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */ | |
416 | #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ | |
417 | #define PLL_OFF 0x0002 /* Shut off PLL clocks */ | |
418 | #define STOPCK_OFF 0x0008 /* Core clock off */ | |
419 | #define STOPCK 0x0008 /* Core Clock Off */ | |
420 | #define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */ | |
421 | #if !defined(__ADSPBF538__) | |
422 | /* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */ | |
423 | # define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ | |
424 | # define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ | |
425 | #endif | |
426 | #define BYPASS 0x0100 /* Bypass the PLL */ | |
427 | /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ | |
428 | #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ | |
1394f032 BW |
429 | |
430 | /* PLL_DIV Masks */ | |
19381f02 BW |
431 | #define SSEL 0x000F /* System Select */ |
432 | #define CSEL 0x0030 /* Core Select */ | |
1394f032 BW |
433 | |
434 | #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ | |
435 | ||
436 | #define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ | |
437 | #define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ | |
438 | #define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ | |
439 | #define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ | |
19381f02 BW |
440 | /* PLL_DIV Macros */ |
441 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | |
1394f032 BW |
442 | |
443 | /* PLL_STAT Masks */ | |
444 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | |
445 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | |
446 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | |
447 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | |
448 | ||
19381f02 BW |
449 | /* VR_CTL Masks */ |
450 | #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ | |
451 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | |
452 | #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ | |
453 | #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ | |
454 | #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ | |
455 | ||
456 | #define GAIN 0x000C /* Voltage Level Gain */ | |
457 | #define GAIN_5 0x0000 /* GAIN = 5 */ | |
458 | #define GAIN_10 0x0004 /* GAIN = 10 */ | |
459 | #define GAIN_20 0x0008 /* GAIN = 20 */ | |
460 | #define GAIN_50 0x000C /* GAIN = 50 */ | |
461 | ||
462 | #define VLEV 0x00F0 /* Internal Voltage Level */ | |
463 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | |
464 | #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ | |
465 | #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ | |
466 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ | |
467 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ | |
468 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ | |
469 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ | |
470 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ | |
c2f95279 MH |
471 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ |
472 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | |
19381f02 BW |
473 | |
474 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | |
475 | #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ | |
476 | ||
1394f032 BW |
477 | /* CHIPID Masks */ |
478 | #define CHIPID_VERSION 0xF0000000 | |
479 | #define CHIPID_FAMILY 0x0FFFF000 | |
480 | #define CHIPID_MANUFACTURE 0x00000FFE | |
481 | ||
482 | /* SWRST Mask */ | |
19381f02 BW |
483 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ |
484 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ | |
485 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ | |
486 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ | |
487 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ | |
488 | ||
489 | /* SYSCR Masks */ | |
490 | #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ | |
491 | #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ | |
1394f032 BW |
492 | |
493 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ | |
494 | ||
495 | /* SIC_IAR0 Masks */ | |
496 | ||
497 | #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ | |
498 | #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ | |
499 | #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ | |
500 | #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ | |
501 | #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ | |
502 | #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ | |
503 | #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ | |
504 | #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ | |
505 | ||
506 | /* SIC_IAR1 Masks */ | |
507 | ||
508 | #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ | |
509 | #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ | |
510 | #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ | |
511 | #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ | |
512 | #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ | |
513 | #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ | |
514 | #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ | |
515 | #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ | |
516 | ||
517 | /* SIC_IAR2 Masks */ | |
518 | #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ | |
519 | #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ | |
520 | #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ | |
521 | #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ | |
522 | #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ | |
523 | #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ | |
524 | #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ | |
525 | #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ | |
526 | ||
527 | /* SIC_IMASK Masks */ | |
528 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | |
529 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | |
530 | #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ | |
531 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ | |
532 | ||
533 | /* SIC_IWR Masks */ | |
534 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | |
535 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | |
536 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ | |
537 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ | |
538 | ||
1394f032 BW |
539 | /* ***************************** UART CONTROLLER MASKS ********************** */ |
540 | ||
541 | /* UART_LCR Register */ | |
542 | ||
543 | #define DLAB 0x80 | |
544 | #define SB 0x40 | |
545 | #define STP 0x20 | |
546 | #define EPS 0x10 | |
547 | #define PEN 0x08 | |
548 | #define STB 0x04 | |
549 | #define WLS(x) ((x-5) & 0x03) | |
550 | ||
551 | #define DLAB_P 0x07 | |
552 | #define SB_P 0x06 | |
553 | #define STP_P 0x05 | |
554 | #define EPS_P 0x04 | |
555 | #define PEN_P 0x03 | |
556 | #define STB_P 0x02 | |
557 | #define WLS_P1 0x01 | |
558 | #define WLS_P0 0x00 | |
559 | ||
560 | /* UART_MCR Register */ | |
561 | #define LOOP_ENA 0x10 | |
562 | #define LOOP_ENA_P 0x04 | |
563 | ||
564 | /* UART_LSR Register */ | |
565 | #define TEMT 0x40 | |
566 | #define THRE 0x20 | |
567 | #define BI 0x10 | |
568 | #define FE 0x08 | |
569 | #define PE 0x04 | |
570 | #define OE 0x02 | |
571 | #define DR 0x01 | |
572 | ||
573 | #define TEMP_P 0x06 | |
574 | #define THRE_P 0x05 | |
575 | #define BI_P 0x04 | |
576 | #define FE_P 0x03 | |
577 | #define PE_P 0x02 | |
578 | #define OE_P 0x01 | |
579 | #define DR_P 0x00 | |
580 | ||
581 | /* UART_IER Register */ | |
582 | #define ELSI 0x04 | |
583 | #define ETBEI 0x02 | |
584 | #define ERBFI 0x01 | |
585 | ||
586 | #define ELSI_P 0x02 | |
587 | #define ETBEI_P 0x01 | |
588 | #define ERBFI_P 0x00 | |
589 | ||
590 | /* UART_IIR Register */ | |
591 | #define STATUS(x) ((x << 1) & 0x06) | |
592 | #define NINT 0x01 | |
593 | #define STATUS_P1 0x02 | |
594 | #define STATUS_P0 0x01 | |
595 | #define NINT_P 0x00 | |
596 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | |
597 | #define IIR_RX_READY 0x04 /* Receive data ready */ | |
598 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | |
599 | #define IIR_STATUS 0x06 | |
600 | ||
601 | /* UART_GCTL Register */ | |
602 | #define FFE 0x20 | |
603 | #define FPE 0x10 | |
604 | #define RPOLC 0x08 | |
605 | #define TPOLC 0x04 | |
606 | #define IREN 0x02 | |
607 | #define UCEN 0x01 | |
608 | ||
609 | #define FFE_P 0x05 | |
610 | #define FPE_P 0x04 | |
611 | #define RPOLC_P 0x03 | |
612 | #define TPOLC_P 0x02 | |
613 | #define IREN_P 0x01 | |
614 | #define UCEN_P 0x00 | |
615 | ||
616 | /* ********** SERIAL PORT MASKS ********************** */ | |
617 | ||
618 | /* SPORTx_TCR1 Masks */ | |
619 | #define TSPEN 0x0001 /* TX enable */ | |
620 | #define ITCLK 0x0002 /* Internal TX Clock Select */ | |
621 | #define TDTYPE 0x000C /* TX Data Formatting Select */ | |
19381f02 BW |
622 | #define DTYPE_NORM 0x0000 /* Data Format Normal */ |
623 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | |
624 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | |
1394f032 BW |
625 | #define TLSBIT 0x0010 /* TX Bit Order */ |
626 | #define ITFS 0x0200 /* Internal TX Frame Sync Select */ | |
627 | #define TFSR 0x0400 /* TX Frame Sync Required Select */ | |
628 | #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ | |
629 | #define LTFS 0x1000 /* Low TX Frame Sync Select */ | |
630 | #define LATFS 0x2000 /* Late TX Frame Sync Select */ | |
631 | #define TCKFE 0x4000 /* TX Clock Falling Edge Select */ | |
632 | ||
633 | /* SPORTx_TCR2 Masks */ | |
19381f02 BW |
634 | #if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \ |
635 | defined(__ADSPBF533__) | |
636 | # define SLEN 0x001F /*TX Word Length */ | |
637 | #else | |
638 | # define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ | |
639 | #endif | |
1394f032 BW |
640 | #define TXSE 0x0100 /*TX Secondary Enable */ |
641 | #define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ | |
642 | #define TRFST 0x0400 /*TX Right-First Data Order */ | |
643 | ||
644 | /* SPORTx_RCR1 Masks */ | |
645 | #define RSPEN 0x0001 /* RX enable */ | |
646 | #define IRCLK 0x0002 /* Internal RX Clock Select */ | |
647 | #define RDTYPE 0x000C /* RX Data Formatting Select */ | |
19381f02 BW |
648 | #define DTYPE_NORM 0x0000 /* no companding */ |
649 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | |
650 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | |
1394f032 BW |
651 | #define RLSBIT 0x0010 /* RX Bit Order */ |
652 | #define IRFS 0x0200 /* Internal RX Frame Sync Select */ | |
653 | #define RFSR 0x0400 /* RX Frame Sync Required Select */ | |
654 | #define LRFS 0x1000 /* Low RX Frame Sync Select */ | |
655 | #define LARFS 0x2000 /* Late RX Frame Sync Select */ | |
656 | #define RCKFE 0x4000 /* RX Clock Falling Edge Select */ | |
657 | ||
658 | /* SPORTx_RCR2 Masks */ | |
19381f02 | 659 | /* SLEN defined above */ |
1394f032 BW |
660 | #define RXSE 0x0100 /*RX Secondary Enable */ |
661 | #define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ | |
662 | #define RRFST 0x0400 /*Right-First Data Order */ | |
663 | ||
664 | /*SPORTx_STAT Masks */ | |
665 | #define RXNE 0x0001 /*RX FIFO Not Empty Status */ | |
666 | #define RUVF 0x0002 /*RX Underflow Status */ | |
667 | #define ROVF 0x0004 /*RX Overflow Status */ | |
668 | #define TXF 0x0008 /*TX FIFO Full Status */ | |
669 | #define TUVF 0x0010 /*TX Underflow Status */ | |
670 | #define TOVF 0x0020 /*TX Overflow Status */ | |
671 | #define TXHRE 0x0040 /*TX Hold Register Empty */ | |
672 | ||
673 | /*SPORTx_MCMC1 Masks */ | |
674 | #define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ | |
675 | #define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ | |
19381f02 BW |
676 | /* SPORTx_MCMC1 Macros */ |
677 | #define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ | |
678 | /* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */ | |
679 | #define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ | |
1394f032 BW |
680 | |
681 | /*SPORTx_MCMC2 Masks */ | |
19381f02 BW |
682 | #define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ |
683 | #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ | |
684 | #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ | |
685 | #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ | |
686 | #define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ | |
687 | #define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ | |
688 | #define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ | |
689 | #define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ | |
690 | #define MFD 0x0000F000 /*Multichannel Frame Delay */ | |
691 | #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ | |
692 | #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ | |
693 | #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ | |
694 | #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ | |
695 | #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ | |
696 | #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ | |
697 | #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ | |
698 | #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ | |
699 | #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ | |
700 | #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ | |
701 | #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ | |
702 | #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ | |
703 | #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ | |
704 | #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ | |
705 | #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ | |
706 | #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ | |
1394f032 BW |
707 | |
708 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ | |
709 | ||
710 | /* PPI_CONTROL Masks */ | |
711 | #define PORT_EN 0x00000001 /* PPI Port Enable */ | |
712 | #define PORT_DIR 0x00000002 /* PPI Port Direction */ | |
713 | #define XFR_TYPE 0x0000000C /* PPI Transfer Type */ | |
714 | #define PORT_CFG 0x00000030 /* PPI Port Configuration */ | |
715 | #define FLD_SEL 0x00000040 /* PPI Active Field Select */ | |
716 | #define PACK_EN 0x00000080 /* PPI Packing Mode */ | |
717 | #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ | |
718 | #define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ | |
719 | #define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ | |
720 | #define DLENGTH 0x00003800 /* PPI Data Length */ | |
721 | #define DLEN_8 0x0000 /* Data Length = 8 Bits */ | |
722 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ | |
723 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ | |
724 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ | |
725 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ | |
726 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ | |
727 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ | |
728 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ | |
729 | #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ | |
730 | #define POL 0x0000C000 /* PPI Signal Polarities */ | |
19381f02 BW |
731 | #define POLC 0x4000 /* PPI Clock Polarity */ |
732 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | |
1394f032 BW |
733 | |
734 | /* PPI_STATUS Masks */ | |
735 | #define FLD 0x00000400 /* Field Indicator */ | |
736 | #define FT_ERR 0x00000800 /* Frame Track Error */ | |
737 | #define OVR 0x00001000 /* FIFO Overflow Error */ | |
738 | #define UNDR 0x00002000 /* FIFO Underrun Error */ | |
739 | #define ERR_DET 0x00004000 /* Error Detected Indicator */ | |
740 | #define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ | |
741 | ||
742 | /* ********** DMA CONTROLLER MASKS *********************8 */ | |
743 | ||
744 | /*DMAx_CONFIG, MDMA_yy_CONFIG Masks */ | |
745 | #define DMAEN 0x00000001 /* Channel Enable */ | |
746 | #define WNR 0x00000002 /* Channel Direction (W/R*) */ | |
747 | #define WDSIZE_8 0x00000000 /* Word Size 8 bits */ | |
748 | #define WDSIZE_16 0x00000004 /* Word Size 16 bits */ | |
749 | #define WDSIZE_32 0x00000008 /* Word Size 32 bits */ | |
750 | #define DMA2D 0x00000010 /* 2D/1D* Mode */ | |
751 | #define RESTART 0x00000020 /* Restart */ | |
752 | #define DI_SEL 0x00000040 /* Data Interrupt Select */ | |
753 | #define DI_EN 0x00000080 /* Data Interrupt Enable */ | |
754 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | |
755 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | |
756 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | |
757 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | |
758 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | |
759 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | |
760 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | |
761 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | |
762 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | |
763 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | |
764 | #define NDSIZE 0x00000900 /* Next Descriptor Size */ | |
765 | #define DMAFLOW 0x00007000 /* Flow Control */ | |
766 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | |
767 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | |
768 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | |
769 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | |
770 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | |
771 | ||
772 | #define DMAEN_P 0 /* Channel Enable */ | |
773 | #define WNR_P 1 /* Channel Direction (W/R*) */ | |
774 | #define DMA2D_P 4 /* 2D/1D* Mode */ | |
775 | #define RESTART_P 5 /* Restart */ | |
776 | #define DI_SEL_P 6 /* Data Interrupt Select */ | |
777 | #define DI_EN_P 7 /* Data Interrupt Enable */ | |
778 | ||
779 | /*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ | |
780 | ||
781 | #define DMA_DONE 0x00000001 /* DMA Done Indicator */ | |
782 | #define DMA_ERR 0x00000002 /* DMA Error Indicator */ | |
783 | #define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ | |
784 | #define DMA_RUN 0x00000008 /* DMA Running Indicator */ | |
785 | ||
786 | #define DMA_DONE_P 0 /* DMA Done Indicator */ | |
787 | #define DMA_ERR_P 1 /* DMA Error Indicator */ | |
788 | #define DFETCH_P 2 /* Descriptor Fetch Indicator */ | |
789 | #define DMA_RUN_P 3 /* DMA Running Indicator */ | |
790 | ||
791 | /*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | |
792 | ||
793 | #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ | |
794 | #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ | |
795 | #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ | |
796 | #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ | |
797 | #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ | |
798 | #define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ | |
799 | #define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ | |
800 | #define PMAP 0x00007000 /* DMA Peripheral Map Field */ | |
801 | ||
19381f02 BW |
802 | #define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ |
803 | #define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ | |
804 | #define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ | |
805 | #define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ | |
806 | #define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ | |
807 | #define PMAP_SPI 0x5000 /* PMAP SPI DMA */ | |
808 | #define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */ | |
809 | #define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */ | |
810 | ||
1394f032 BW |
811 | /* ************* GENERAL PURPOSE TIMER MASKS ******************** */ |
812 | ||
813 | /* PWM Timer bit definitions */ | |
814 | ||
815 | /* TIMER_ENABLE Register */ | |
816 | #define TIMEN0 0x0001 | |
817 | #define TIMEN1 0x0002 | |
818 | #define TIMEN2 0x0004 | |
819 | ||
820 | #define TIMEN0_P 0x00 | |
821 | #define TIMEN1_P 0x01 | |
822 | #define TIMEN2_P 0x02 | |
823 | ||
824 | /* TIMER_DISABLE Register */ | |
825 | #define TIMDIS0 0x0001 | |
826 | #define TIMDIS1 0x0002 | |
827 | #define TIMDIS2 0x0004 | |
828 | ||
829 | #define TIMDIS0_P 0x00 | |
830 | #define TIMDIS1_P 0x01 | |
831 | #define TIMDIS2_P 0x02 | |
832 | ||
833 | /* TIMER_STATUS Register */ | |
834 | #define TIMIL0 0x0001 | |
835 | #define TIMIL1 0x0002 | |
836 | #define TIMIL2 0x0004 | |
19381f02 BW |
837 | #define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ |
838 | #define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ | |
839 | #define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ | |
1394f032 BW |
840 | #define TRUN0 0x1000 |
841 | #define TRUN1 0x2000 | |
842 | #define TRUN2 0x4000 | |
843 | ||
844 | #define TIMIL0_P 0x00 | |
845 | #define TIMIL1_P 0x01 | |
846 | #define TIMIL2_P 0x02 | |
19381f02 BW |
847 | #define TOVF_ERR0_P 0x04 |
848 | #define TOVF_ERR1_P 0x05 | |
849 | #define TOVF_ERR2_P 0x06 | |
1394f032 BW |
850 | #define TRUN0_P 0x0C |
851 | #define TRUN1_P 0x0D | |
852 | #define TRUN2_P 0x0E | |
853 | ||
19381f02 BW |
854 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ |
855 | #define TOVL_ERR0 TOVF_ERR0 | |
856 | #define TOVL_ERR1 TOVF_ERR1 | |
857 | #define TOVL_ERR2 TOVF_ERR2 | |
858 | #define TOVL_ERR0_P TOVF_ERR0_P | |
859 | #define TOVL_ERR1_P TOVF_ERR1_P | |
860 | #define TOVL_ERR2_P TOVF_ERR2_P | |
861 | ||
1394f032 BW |
862 | /* TIMERx_CONFIG Registers */ |
863 | #define PWM_OUT 0x0001 | |
864 | #define WDTH_CAP 0x0002 | |
865 | #define EXT_CLK 0x0003 | |
866 | #define PULSE_HI 0x0004 | |
867 | #define PERIOD_CNT 0x0008 | |
868 | #define IRQ_ENA 0x0010 | |
869 | #define TIN_SEL 0x0020 | |
870 | #define OUT_DIS 0x0040 | |
871 | #define CLK_SEL 0x0080 | |
872 | #define TOGGLE_HI 0x0100 | |
873 | #define EMU_RUN 0x0200 | |
874 | #define ERR_TYP(x) ((x & 0x03) << 14) | |
875 | ||
876 | #define TMODE_P0 0x00 | |
877 | #define TMODE_P1 0x01 | |
878 | #define PULSE_HI_P 0x02 | |
879 | #define PERIOD_CNT_P 0x03 | |
880 | #define IRQ_ENA_P 0x04 | |
881 | #define TIN_SEL_P 0x05 | |
882 | #define OUT_DIS_P 0x06 | |
883 | #define CLK_SEL_P 0x07 | |
884 | #define TOGGLE_HI_P 0x08 | |
885 | #define EMU_RUN_P 0x09 | |
886 | #define ERR_TYP_P0 0x0E | |
887 | #define ERR_TYP_P1 0x0F | |
888 | ||
889 | /*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ | |
890 | ||
891 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ | |
892 | #define PF0 0x0001 | |
893 | #define PF1 0x0002 | |
894 | #define PF2 0x0004 | |
895 | #define PF3 0x0008 | |
896 | #define PF4 0x0010 | |
897 | #define PF5 0x0020 | |
898 | #define PF6 0x0040 | |
899 | #define PF7 0x0080 | |
900 | #define PF8 0x0100 | |
901 | #define PF9 0x0200 | |
902 | #define PF10 0x0400 | |
903 | #define PF11 0x0800 | |
904 | #define PF12 0x1000 | |
905 | #define PF13 0x2000 | |
906 | #define PF14 0x4000 | |
907 | #define PF15 0x8000 | |
908 | ||
909 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ | |
910 | #define PF0_P 0 | |
911 | #define PF1_P 1 | |
912 | #define PF2_P 2 | |
913 | #define PF3_P 3 | |
914 | #define PF4_P 4 | |
915 | #define PF5_P 5 | |
916 | #define PF6_P 6 | |
917 | #define PF7_P 7 | |
918 | #define PF8_P 8 | |
919 | #define PF9_P 9 | |
920 | #define PF10_P 10 | |
921 | #define PF11_P 11 | |
922 | #define PF12_P 12 | |
923 | #define PF13_P 13 | |
924 | #define PF14_P 14 | |
925 | #define PF15_P 15 | |
926 | ||
927 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ | |
928 | ||
929 | /* SPI_CTL Masks */ | |
930 | #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ | |
19381f02 BW |
931 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ |
932 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | |
933 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | |
934 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | |
1394f032 BW |
935 | #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ |
936 | #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ | |
937 | #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ | |
938 | #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ | |
dbcc78be | 939 | #define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ |
1394f032 BW |
940 | #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ |
941 | #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ | |
942 | #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ | |
943 | #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ | |
944 | #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ | |
945 | #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ | |
946 | ||
947 | /* SPI_FLG Masks */ | |
948 | #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
949 | #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
950 | #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
951 | #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
952 | #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
953 | #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
954 | #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
955 | #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
956 | #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
957 | #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
958 | #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
959 | #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
960 | #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
961 | #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
962 | ||
963 | /* SPI_FLG Bit Positions */ | |
964 | #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
965 | #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
966 | #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
967 | #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
968 | #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
969 | #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
970 | #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
971 | #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | |
972 | #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | |
973 | #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | |
974 | #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | |
975 | #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | |
976 | #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | |
977 | #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | |
978 | ||
979 | /* SPI_STAT Masks */ | |
980 | #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ | |
981 | #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ | |
982 | #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ | |
983 | #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ | |
984 | #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ | |
985 | #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ | |
986 | #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ | |
987 | ||
19381f02 BW |
988 | /* SPIx_FLG Masks */ |
989 | #define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */ | |
990 | #define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */ | |
991 | #define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */ | |
992 | #define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */ | |
993 | #define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */ | |
994 | #define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */ | |
995 | #define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */ | |
996 | ||
1394f032 BW |
997 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ |
998 | ||
999 | /* AMGCTL Masks */ | |
1000 | #define AMCKEN 0x00000001 /* Enable CLKOUT */ | |
19381f02 | 1001 | #define AMBEN_NONE 0x00000000 /* All Banks Disabled */ |
1394f032 BW |
1002 | #define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ |
1003 | #define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ | |
1004 | #define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ | |
1005 | #define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ | |
1006 | ||
1007 | /* AMGCTL Bit Positions */ | |
1008 | #define AMCKEN_P 0x00000000 /* Enable CLKOUT */ | |
1009 | #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ | |
1010 | #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ | |
1011 | #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ | |
1012 | ||
1013 | /* AMBCTL0 Masks */ | |
1014 | #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ | |
1015 | #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ | |
1016 | #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ | |
1017 | #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ | |
1018 | #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ | |
1019 | #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ | |
1020 | #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ | |
1021 | #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ | |
1022 | #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ | |
1023 | #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ | |
1024 | #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ | |
1025 | #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ | |
1026 | #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ | |
1027 | #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ | |
1028 | #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ | |
1029 | #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ | |
1030 | #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ | |
1031 | #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ | |
1032 | #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ | |
1033 | #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ | |
1034 | #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ | |
1035 | #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ | |
1036 | #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ | |
1037 | #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ | |
1038 | #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ | |
1039 | #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ | |
1040 | #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ | |
1041 | #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ | |
1042 | #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ | |
1043 | #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ | |
1044 | #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ | |
1045 | #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ | |
1046 | #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ | |
1047 | #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ | |
1048 | #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ | |
1049 | #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ | |
1050 | #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ | |
1051 | #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ | |
1052 | #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ | |
1053 | #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ | |
1054 | #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ | |
1055 | #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ | |
1056 | #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ | |
1057 | #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ | |
1058 | #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ | |
1059 | #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ | |
1060 | #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ | |
1061 | #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ | |
1062 | #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ | |
1063 | #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ | |
1064 | #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
1065 | #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
1066 | #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
1067 | #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
1068 | #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
1069 | #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
1070 | #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
1071 | #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
1072 | #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ | |
1073 | #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ | |
1074 | #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ | |
1075 | #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ | |
1076 | #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ | |
1077 | #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ | |
1078 | #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ | |
1079 | #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ | |
1080 | #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ | |
1081 | #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ | |
1082 | #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ | |
1083 | #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ | |
1084 | #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ | |
1085 | #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ | |
1086 | #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ | |
1087 | #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ | |
1088 | #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ | |
1089 | #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ | |
1090 | #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ | |
1091 | #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ | |
1092 | #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ | |
1093 | #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ | |
1094 | #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ | |
1095 | #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ | |
1096 | #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ | |
1097 | #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ | |
1098 | #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ | |
1099 | #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ | |
1100 | #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ | |
1101 | #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ | |
1102 | ||
1103 | /* AMBCTL1 Masks */ | |
1104 | #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ | |
1105 | #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ | |
1106 | #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ | |
1107 | #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ | |
1108 | #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ | |
1109 | #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ | |
1110 | #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
1111 | #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
1112 | #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
1113 | #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
1114 | #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
1115 | #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
1116 | #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
1117 | #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
1118 | #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ | |
1119 | #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ | |
1120 | #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ | |
1121 | #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ | |
1122 | #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ | |
1123 | #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ | |
1124 | #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ | |
1125 | #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ | |
1126 | #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ | |
1127 | #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ | |
1128 | #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ | |
1129 | #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ | |
1130 | #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ | |
1131 | #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ | |
1132 | #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ | |
1133 | #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ | |
1134 | #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ | |
1135 | #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ | |
1136 | #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ | |
1137 | #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ | |
1138 | #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ | |
1139 | #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ | |
1140 | #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ | |
1141 | #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ | |
1142 | #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ | |
1143 | #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ | |
1144 | #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ | |
1145 | #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ | |
1146 | #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ | |
1147 | #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ | |
1148 | #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ | |
1149 | #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ | |
1150 | #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ | |
1151 | #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ | |
1152 | #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ | |
1153 | #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ | |
1154 | #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | |
1155 | #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | |
1156 | #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | |
1157 | #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | |
1158 | #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | |
1159 | #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | |
1160 | #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | |
1161 | #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | |
1162 | #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ | |
1163 | #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ | |
1164 | #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ | |
1165 | #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ | |
1166 | #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ | |
1167 | #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ | |
1168 | #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ | |
1169 | #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ | |
1170 | #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ | |
1171 | #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ | |
1172 | #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ | |
1173 | #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ | |
1174 | #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ | |
1175 | #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ | |
1176 | #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ | |
1177 | #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ | |
1178 | #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ | |
1179 | #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ | |
1180 | #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ | |
1181 | #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ | |
1182 | #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ | |
1183 | #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ | |
1184 | #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ | |
1185 | #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ | |
1186 | #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ | |
1187 | #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ | |
1188 | #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ | |
1189 | #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ | |
1190 | #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ | |
1191 | #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ | |
1192 | ||
1193 | /* ********************** SDRAM CONTROLLER MASKS *************************** */ | |
1194 | ||
1195 | /* SDGCTL Masks */ | |
1196 | #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ | |
1197 | #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ | |
1198 | #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ | |
1199 | #define PFE 0x00000010 /* Enable SDRAM prefetch */ | |
1200 | #define PFP 0x00000020 /* Prefetch has priority over AMC requests */ | |
19381f02 BW |
1201 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ |
1202 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ | |
1203 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ | |
1394f032 BW |
1204 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ |
1205 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | |
1206 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | |
1207 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | |
1208 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | |
1209 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | |
1210 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | |
1211 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | |
1212 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | |
1213 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | |
1214 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | |
1215 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | |
1216 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | |
1217 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | |
1218 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | |
1219 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | |
1220 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | |
1221 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | |
1222 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | |
1223 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | |
1224 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | |
1225 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | |
1226 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | |
1227 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | |
1228 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | |
1229 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | |
1230 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | |
1231 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | |
1232 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | |
1233 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | |
1234 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | |
1235 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | |
1236 | #define PUPSD 0x00200000 /*Power-up start delay */ | |
1237 | #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ | |
1238 | #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ | |
1239 | #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ | |
1240 | #define EBUFE 0x02000000 /* Enable external buffering timing */ | |
1241 | #define FBBRW 0x04000000 /* Fast back-to-back read write enable */ | |
1242 | #define EMREN 0x10000000 /* Extended mode register enable */ | |
1243 | #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ | |
1244 | #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ | |
1245 | ||
1246 | /* EBIU_SDBCTL Masks */ | |
1247 | #define EBE 0x00000001 /* Enable SDRAM external bank */ | |
1248 | #define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | |
1249 | #define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ | |
1250 | #define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ | |
1251 | #define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ | |
1252 | #define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | |
1253 | #define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ | |
1254 | #define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ | |
1255 | #define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ | |
1256 | ||
1257 | /* EBIU_SDSTAT Masks */ | |
1258 | #define SDCI 0x00000001 /* SDRAM controller is idle */ | |
1259 | #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ | |
1260 | #define SDPUA 0x00000004 /* SDRAM power up active */ | |
1261 | #define SDRS 0x00000008 /* SDRAM is in reset state */ | |
1262 | #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ | |
1263 | #define BGSTAT 0x00000020 /* Bus granted */ | |
1264 | ||
1394f032 BW |
1265 | |
1266 | #endif /* _DEF_BF532_H */ |