projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * linux/include/asm-arm/hardware/iomd.h | |
| 3 | * | |
| 4 | * Copyright (C) 1999 Russell King | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * This file contains information out the IOMD ASIC used in the | |
| 11 | * Acorn RiscPC and subsequently integrated into the CLPS7500 chips. | |
| 12 | */ | |
| 13 | #ifndef __ASMARM_HARDWARE_IOMD_H | |
| 14 | #define __ASMARM_HARDWARE_IOMD_H | |
| 15 | ||
| 16 | #include <linux/config.h> | |
| 17 | ||
| 18 | #ifndef __ASSEMBLY__ | |
| 19 | ||
| 20 | /* | |
| 21 | * We use __raw_base variants here so that we give the compiler the | |
| 22 | * chance to keep IOC_BASE in a register. | |
| 23 | */ | |
| 24 | #define iomd_readb(off) __raw_readb(IOMD_BASE + (off)) | |
| 25 | #define iomd_readl(off) __raw_readl(IOMD_BASE + (off)) | |
| 26 | #define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off)) | |
| 27 | #define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off)) | |
| 28 | ||
| 29 | #endif | |
| 30 | ||
| 31 | #define IOMD_CONTROL (0x000) | |
| 32 | #define IOMD_KARTTX (0x004) | |
| 33 | #define IOMD_KARTRX (0x004) | |
| 34 | #define IOMD_KCTRL (0x008) | |
| 35 | ||
| 36 | #ifdef CONFIG_ARCH_CLPS7500 | |
| 37 | #define IOMD_IOLINES (0x00C) | |
| 38 | #endif | |
| 39 | ||
| 40 | #define IOMD_IRQSTATA (0x010) | |
| 41 | #define IOMD_IRQREQA (0x014) | |
| 42 | #define IOMD_IRQCLRA (0x014) | |
| 43 | #define IOMD_IRQMASKA (0x018) | |
| 44 | ||
| 45 | #ifdef CONFIG_ARCH_CLPS7500 | |
| 46 | #define IOMD_SUSMODE (0x01C) | |
| 47 | #endif | |
| 48 | ||
| 49 | #define IOMD_IRQSTATB (0x020) | |
| 50 | #define IOMD_IRQREQB (0x024) | |
| 51 | #define IOMD_IRQMASKB (0x028) | |
| 52 | ||
| 53 | #define IOMD_FIQSTAT (0x030) | |
| 54 | #define IOMD_FIQREQ (0x034) | |
| 55 | #define IOMD_FIQMASK (0x038) | |
| 56 | ||
| 57 | #ifdef CONFIG_ARCH_CLPS7500 | |
| 58 | #define IOMD_CLKCTL (0x03C) | |
| 59 | #endif | |
| 60 | ||
| 61 | #define IOMD_T0CNTL (0x040) | |
| 62 | #define IOMD_T0LTCHL (0x040) | |
| 63 | #define IOMD_T0CNTH (0x044) | |
| 64 | #define IOMD_T0LTCHH (0x044) | |
| 65 | #define IOMD_T0GO (0x048) | |
| 66 | #define IOMD_T0LATCH (0x04c) | |
| 67 | ||
| 68 | #define IOMD_T1CNTL (0x050) | |
| 69 | #define IOMD_T1LTCHL (0x050) | |
| 70 | #define IOMD_T1CNTH (0x054) | |
| 71 | #define IOMD_T1LTCHH (0x054) | |
| 72 | #define IOMD_T1GO (0x058) | |
| 73 | #define IOMD_T1LATCH (0x05c) | |
| 74 | ||
| 75 | #ifdef CONFIG_ARCH_CLPS7500 | |
| 76 | #define IOMD_IRQSTATC (0x060) | |
| 77 | #define IOMD_IRQREQC (0x064) | |
| 78 | #define IOMD_IRQMASKC (0x068) | |
| 79 | ||
| 80 | #define IOMD_VIDMUX (0x06c) | |
| 81 | ||
| 82 | #define IOMD_IRQSTATD (0x070) | |
| 83 | #define IOMD_IRQREQD (0x074) | |
| 84 | #define IOMD_IRQMASKD (0x078) | |
| 85 | #endif | |
| 86 | ||
| 87 | #define IOMD_ROMCR0 (0x080) | |
| 88 | #define IOMD_ROMCR1 (0x084) | |
| 89 | #ifdef CONFIG_ARCH_RPC | |
| 90 | #define IOMD_DRAMCR (0x088) | |
| 91 | #endif | |
| 92 | #define IOMD_REFCR (0x08C) | |
| 93 | ||
| 94 | #define IOMD_FSIZE (0x090) | |
| 95 | #define IOMD_ID0 (0x094) | |
| 96 | #define IOMD_ID1 (0x098) | |
| 97 | #define IOMD_VERSION (0x09C) | |
| 98 | ||
| 99 | #ifdef CONFIG_ARCH_RPC | |
| 100 | #define IOMD_MOUSEX (0x0A0) | |
| 101 | #define IOMD_MOUSEY (0x0A4) | |
| 102 | #endif | |
| 103 | ||
| 104 | #ifdef CONFIG_ARCH_CLPS7500 | |
| 105 | #define IOMD_MSEDAT (0x0A8) | |
| 106 | #define IOMD_MSECTL (0x0Ac) | |
| 107 | #endif | |
| 108 | ||
| 109 | #ifdef CONFIG_ARCH_RPC | |
| 110 | #define IOMD_DMATCR (0x0C0) | |
| 111 | #endif | |
| 112 | #define IOMD_IOTCR (0x0C4) | |
| 113 | #define IOMD_ECTCR (0x0C8) | |
| 114 | #ifdef CONFIG_ARCH_RPC | |
| 115 | #define IOMD_DMAEXT (0x0CC) | |
| 116 | #endif | |
| 117 | #ifdef CONFIG_ARCH_CLPS7500 | |
| 118 | #define IOMD_ASTCR (0x0CC) | |
| 119 | #define IOMD_DRAMCR (0x0D0) | |
| 120 | #define IOMD_SELFREF (0x0D4) | |
| 121 | #define IOMD_ATODICR (0x0E0) | |
| 122 | #define IOMD_ATODSR (0x0E4) | |
| 123 | #define IOMD_ATODCC (0x0E8) | |
| 124 | #define IOMD_ATODCNT1 (0x0EC) | |
| 125 | #define IOMD_ATODCNT2 (0x0F0) | |
| 126 | #define IOMD_ATODCNT3 (0x0F4) | |
| 127 | #define IOMD_ATODCNT4 (0x0F8) | |
| 128 | #endif | |
| 129 | ||
| 130 | #ifdef CONFIG_ARCH_RPC | |
| 131 | #define DMA_EXT_IO0 1 | |
| 132 | #define DMA_EXT_IO1 2 | |
| 133 | #define DMA_EXT_IO2 4 | |
| 134 | #define DMA_EXT_IO3 8 | |
| 135 | ||
| 136 | #define IOMD_IO0CURA (0x100) | |
| 137 | #define IOMD_IO0ENDA (0x104) | |
| 138 | #define IOMD_IO0CURB (0x108) | |
| 139 | #define IOMD_IO0ENDB (0x10C) | |
| 140 | #define IOMD_IO0CR (0x110) | |
| 141 | #define IOMD_IO0ST (0x114) | |
| 142 | ||
| 143 | #define IOMD_IO1CURA (0x120) | |
| 144 | #define IOMD_IO1ENDA (0x124) | |
| 145 | #define IOMD_IO1CURB (0x128) | |
| 146 | #define IOMD_IO1ENDB (0x12C) | |
| 147 | #define IOMD_IO1CR (0x130) | |
| 148 | #define IOMD_IO1ST (0x134) | |
| 149 | ||
| 150 | #define IOMD_IO2CURA (0x140) | |
| 151 | #define IOMD_IO2ENDA (0x144) | |
| 152 | #define IOMD_IO2CURB (0x148) | |
| 153 | #define IOMD_IO2ENDB (0x14C) | |
| 154 | #define IOMD_IO2CR (0x150) | |
| 155 | #define IOMD_IO2ST (0x154) | |
| 156 | ||
| 157 | #define IOMD_IO3CURA (0x160) | |
| 158 | #define IOMD_IO3ENDA (0x164) | |
| 159 | #define IOMD_IO3CURB (0x168) | |
| 160 | #define IOMD_IO3ENDB (0x16C) | |
| 161 | #define IOMD_IO3CR (0x170) | |
| 162 | #define IOMD_IO3ST (0x174) | |
| 163 | #endif | |
| 164 | ||
| 165 | #define IOMD_SD0CURA (0x180) | |
| 166 | #define IOMD_SD0ENDA (0x184) | |
| 167 | #define IOMD_SD0CURB (0x188) | |
| 168 | #define IOMD_SD0ENDB (0x18C) | |
| 169 | #define IOMD_SD0CR (0x190) | |
| 170 | #define IOMD_SD0ST (0x194) | |
| 171 | ||
| 172 | #ifdef CONFIG_ARCH_RPC | |
| 173 | #define IOMD_SD1CURA (0x1A0) | |
| 174 | #define IOMD_SD1ENDA (0x1A4) | |
| 175 | #define IOMD_SD1CURB (0x1A8) | |
| 176 | #define IOMD_SD1ENDB (0x1AC) | |
| 177 | #define IOMD_SD1CR (0x1B0) | |
| 178 | #define IOMD_SD1ST (0x1B4) | |
| 179 | #endif | |
| 180 | ||
| 181 | #define IOMD_CURSCUR (0x1C0) | |
| 182 | #define IOMD_CURSINIT (0x1C4) | |
| 183 | ||
| 184 | #define IOMD_VIDCUR (0x1D0) | |
| 185 | #define IOMD_VIDEND (0x1D4) | |
| 186 | #define IOMD_VIDSTART (0x1D8) | |
| 187 | #define IOMD_VIDINIT (0x1DC) | |
| 188 | #define IOMD_VIDCR (0x1E0) | |
| 189 | ||
| 190 | #define IOMD_DMASTAT (0x1F0) | |
| 191 | #define IOMD_DMAREQ (0x1F4) | |
| 192 | #define IOMD_DMAMASK (0x1F8) | |
| 193 | ||
| 194 | #define DMA_END_S (1 << 31) | |
| 195 | #define DMA_END_L (1 << 30) | |
| 196 | ||
| 197 | #define DMA_CR_C 0x80 | |
| 198 | #define DMA_CR_D 0x40 | |
| 199 | #define DMA_CR_E 0x20 | |
| 200 | ||
| 201 | #define DMA_ST_OFL 4 | |
| 202 | #define DMA_ST_INT 2 | |
| 203 | #define DMA_ST_AB 1 | |
| 204 | ||
| 205 | /* | |
| 206 | * DMA (MEMC) compatibility | |
| 207 | */ | |
| 208 | #define HALF_SAM vram_half_sam | |
| 209 | #define VDMA_ALIGNMENT (HALF_SAM * 2) | |
| 210 | #define VDMA_XFERSIZE (HALF_SAM) | |
| 211 | #define VDMA_INIT IOMD_VIDINIT | |
| 212 | #define VDMA_START IOMD_VIDSTART | |
| 213 | #define VDMA_END IOMD_VIDEND | |
| 214 | ||
| 215 | #ifndef __ASSEMBLY__ | |
| 216 | extern unsigned int vram_half_sam; | |
| 217 | #define video_set_dma(start,end,offset) \ | |
| 218 | do { \ | |
| 219 | outl (SCREEN_START + start, VDMA_START); \ | |
| 220 | outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \ | |
| 221 | if (offset >= end - VDMA_XFERSIZE) \ | |
| 222 | offset |= 0x40000000; \ | |
| 223 | outl (SCREEN_START + offset, VDMA_INIT); \ | |
| 224 | } while (0) | |
| 225 | #endif | |
| 226 | ||
| 227 | #endif |