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1 | #ifndef __ASMARM_ELF_H |
2 | #define __ASMARM_ELF_H | |
3 | ||
4 | #include <linux/config.h> | |
5 | ||
6 | /* | |
7 | * ELF register definitions.. | |
8 | */ | |
9 | ||
10 | #include <asm/ptrace.h> | |
11 | #include <asm/user.h> | |
12 | #include <asm/procinfo.h> | |
13 | ||
14 | typedef unsigned long elf_greg_t; | |
15 | typedef unsigned long elf_freg_t[3]; | |
16 | ||
17 | #define EM_ARM 40 | |
18 | #define EF_ARM_APCS26 0x08 | |
19 | #define EF_ARM_SOFT_FLOAT 0x200 | |
20 | #define EF_ARM_EABI_MASK 0xFF000000 | |
21 | ||
22 | #define R_ARM_NONE 0 | |
23 | #define R_ARM_PC24 1 | |
24 | #define R_ARM_ABS32 2 | |
25 | ||
26 | #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) | |
27 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | |
28 | ||
29 | typedef struct user_fp elf_fpregset_t; | |
30 | ||
31 | /* | |
32 | * This is used to ensure we don't load something for the wrong architecture. | |
33 | */ | |
34 | #define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && (ELF_PROC_OK((x))) ) | |
35 | ||
36 | /* | |
37 | * These are used to set parameters in the core dumps. | |
38 | */ | |
39 | #define ELF_CLASS ELFCLASS32 | |
40 | #ifdef __ARMEB__ | |
41 | #define ELF_DATA ELFDATA2MSB; | |
42 | #else | |
43 | #define ELF_DATA ELFDATA2LSB; | |
44 | #endif | |
45 | #define ELF_ARCH EM_ARM | |
46 | ||
47 | #define USE_ELF_CORE_DUMP | |
48 | #define ELF_EXEC_PAGESIZE 4096 | |
49 | ||
50 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | |
51 | use of this is to invoke "./ld.so someprog" to test out a new version of | |
52 | the loader. We need to make sure that it is out of the way of the program | |
53 | that it will "exec", and that there is sufficient room for the brk. */ | |
54 | ||
55 | #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) | |
56 | ||
57 | /* When the program starts, a1 contains a pointer to a function to be | |
58 | registered with atexit, as per the SVR4 ABI. A value of 0 means we | |
59 | have no such handler. */ | |
60 | #define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0 | |
61 | ||
62 | /* This yields a mask that user programs can use to figure out what | |
63 | instruction set this cpu supports. */ | |
64 | ||
65 | #define ELF_HWCAP (elf_hwcap) | |
66 | ||
67 | /* This yields a string that ld.so will use to load implementation | |
68 | specific libraries for optimization. This is more specific in | |
69 | intent than poking at uname or /proc/cpuinfo. */ | |
70 | ||
71 | /* For now we just provide a fairly general string that describes the | |
72 | processor family. This could be made more specific later if someone | |
73 | implemented optimisations that require it. 26-bit CPUs give you | |
74 | "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't | |
75 | supported). 32-bit CPUs give you "v3[lb]" for anything based on an | |
76 | ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1 | |
77 | core. */ | |
78 | ||
79 | #define ELF_PLATFORM_SIZE 8 | |
80 | extern char elf_platform[]; | |
81 | #define ELF_PLATFORM (elf_platform) | |
82 | ||
83 | #ifdef __KERNEL__ | |
84 | ||
85 | /* | |
86 | * 32-bit code is always OK. Some cpus can do 26-bit, some can't. | |
87 | */ | |
88 | #define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x)) | |
89 | ||
90 | #define ELF_THUMB_OK(x) \ | |
91 | (( (elf_hwcap & HWCAP_THUMB) && ((x)->e_entry & 1) == 1) || \ | |
92 | ((x)->e_entry & 3) == 0) | |
93 | ||
94 | #define ELF_26BIT_OK(x) \ | |
95 | (( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \ | |
96 | ((x)->e_flags & EF_ARM_APCS26) == 0) | |
97 | ||
98 | #ifndef CONFIG_IWMMXT | |
99 | ||
100 | /* Old NetWinder binaries were compiled in such a way that the iBCS | |
101 | heuristic always trips on them. Until these binaries become uncommon | |
102 | enough not to care, don't trust the `ibcs' flag here. In any case | |
103 | there is no other ELF system currently supported by iBCS. | |
104 | @@ Could print a warning message to encourage users to upgrade. */ | |
105 | #define SET_PERSONALITY(ex,ibcs2) \ | |
106 | set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT)) | |
107 | ||
108 | #else | |
109 | ||
110 | /* | |
111 | * All iWMMXt capable CPUs don't support 26-bit mode. Yet they can run | |
112 | * legacy binaries which used to contain FPA11 floating point instructions | |
113 | * that have always been emulated by the kernel. PFA11 and iWMMXt overlap | |
114 | * on coprocessor 1 space though. We therefore must decide if given task | |
115 | * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked | |
116 | * at all times for the prefetch exception handler to catch FPA11 opcodes | |
117 | * and emulate them. The best indication to discriminate those two cases | |
118 | * is the SOFT_FLOAT flag in the ELF header. | |
119 | */ | |
120 | ||
121 | #define SET_PERSONALITY(ex,ibcs2) \ | |
122 | do { \ | |
123 | set_personality(PER_LINUX_32BIT); \ | |
124 | if (((ex).e_flags & EF_ARM_EABI_MASK) || \ | |
125 | ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \ | |
126 | set_thread_flag(TIF_USING_IWMMXT); \ | |
127 | } while (0) | |
128 | ||
129 | #endif | |
130 | ||
131 | #endif | |
132 | ||
133 | #endif |