projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 8785a8fb RK |
1 | /* |
| 2 | * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h | |
| 3 | * | |
| 4 | * Taken from pxa-regs.h by Russell King | |
| 5 | * | |
| 6 | * Author: Nicolas Pitre | |
| 7 | * Copyright: MontaVista Software Inc. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __PXA2XX_REGS_H | |
| 15 | #define __PXA2XX_REGS_H | |
| 16 | ||
| 17 | /* | |
| 18 | * Memory controller | |
| 19 | */ | |
| 20 | ||
| 21 | #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ | |
| 22 | #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ | |
| 23 | #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ | |
| 24 | #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ | |
| 25 | #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ | |
| 26 | #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ | |
| 27 | #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ | |
| 28 | #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ | |
| 29 | #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ | |
| 30 | #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ | |
| 31 | #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ | |
| 32 | #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ | |
| 33 | #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ | |
| 34 | #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ | |
| 35 | #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ | |
| 36 | #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ | |
| 37 | #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ | |
| 38 | ||
| 39 | /* | |
| 40 | * More handy macros for PCMCIA | |
| 41 | * | |
| 42 | * Arg is socket number | |
| 43 | */ | |
| 44 | #define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ | |
| 45 | #define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ | |
| 46 | #define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ | |
| 47 | ||
| 48 | /* MECR register defines */ | |
| 49 | #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ | |
| 50 | #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ | |
| 51 | ||
| 52 | #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ | |
| 53 | #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ | |
| 54 | #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ | |
| 55 | #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ | |
| 56 | #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ | |
| 57 | #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ | |
| 58 | #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ | |
| 59 | #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ | |
| 60 | #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ | |
| 61 | #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ | |
| 62 | #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ | |
| 63 | #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ | |
| 64 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ | |
| 65 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ | |
| 66 | ||
| 67 | ||
| 68 | #ifdef CONFIG_PXA27x | |
| 69 | ||
| 70 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ | |
| 71 | ||
| 72 | #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ | |
| 73 | #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ | |
| 74 | #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ | |
| 75 | #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ | |
| 76 | #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ | |
| 77 | #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ | |
| 78 | #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ | |
| 79 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ | |
| 80 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ | |
| 81 | ||
| 82 | #endif | |
| 83 | ||
| 84 | #endif |