[linux-block.git] / include / asm-arm / arch-omap / clock.h

/*
 *  linux/include/asm-arm/arch-omap/clock.h
 *
 *  Copyright (C) 2004 - 2005 Nokia corporation
 *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
 *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_OMAP_CLOCK_H
#define __ARCH_ARM_OMAP_CLOCK_H

struct module;
struct clk;

#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)

struct clksel_rate {
	u8			div;
	u32			val;
	u8			flags;
};

struct clksel {
	struct clk		 *parent;
	const struct clksel_rate *rates;
};

struct dpll_data {
	void __iomem		*mult_div1_reg;
	u32			mult_mask;
	u32			div1_mask;
#  if defined(CONFIG_ARCH_OMAP3)
	u8			modes;
	void __iomem		*control_reg;
	u32			enable_mask;
	u8			auto_recal_bit;
	u8			recal_en_bit;
	u8			recal_st_bit;
	void __iomem		*autoidle_reg;
	u32			autoidle_mask;
	void __iomem		*idlest_reg;
	u8			idlest_bit;
#  endif
};

#endif

struct clk {
	struct list_head	node;
	struct module		*owner;
	const char		*name;
	int			id;
	struct clk		*parent;
	unsigned long		rate;
	__u32			flags;
	void __iomem		*enable_reg;
	__u8			enable_bit;
	__s8			usecount;
	void			(*recalc)(struct clk *);
	int			(*set_rate)(struct clk *, unsigned long);
	long			(*round_rate)(struct clk *, unsigned long);
	void			(*init)(struct clk *);
	int			(*enable)(struct clk *);
	void			(*disable)(struct clk *);
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
	u8			fixed_div;
	void __iomem		*clksel_reg;
	u32			clksel_mask;
	const struct clksel	*clksel;
	const struct dpll_data	*dpll_data;
#else
	__u8			rate_offset;
	__u8			src_offset;
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
	struct dentry		*dent;	/* For visible tree hierarchy */
#endif
};

struct cpufreq_frequency_table;

struct clk_functions {
	int		(*clk_enable)(struct clk *clk);
	void		(*clk_disable)(struct clk *clk);
	long		(*clk_round_rate)(struct clk *clk, unsigned long rate);
	int		(*clk_set_rate)(struct clk *clk, unsigned long rate);
	int		(*clk_set_parent)(struct clk *clk, struct clk *parent);
	struct clk *	(*clk_get_parent)(struct clk *clk);
	void		(*clk_allow_idle)(struct clk *clk);
	void		(*clk_deny_idle)(struct clk *clk);
	void		(*clk_disable_unused)(struct clk *clk);
#ifdef CONFIG_CPU_FREQ
	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
#endif
};

extern unsigned int mpurate;

extern int clk_init(struct clk_functions * custom_clocks);
extern int clk_register(struct clk *clk);
extern void clk_unregister(struct clk *clk);
extern void propagate_rate(struct clk *clk);
extern void recalculate_root_clocks(void);
extern void followparent_recalc(struct clk * clk);
extern void clk_allow_idle(struct clk *clk);
extern void clk_deny_idle(struct clk *clk);
extern int clk_get_usecount(struct clk *clk);
extern void clk_enable_init_clocks(void);

/* Clock flags */
#define RATE_CKCTL		(1 << 0)	/* Main fixed ratio clocks */
#define RATE_FIXED		(1 << 1)	/* Fixed clock rate */
#define RATE_PROPAGATES		(1 << 2)	/* Program children too */
#define VIRTUAL_CLOCK		(1 << 3)	/* Composite clock from table */
#define ALWAYS_ENABLED		(1 << 4)	/* Clock cannot be disabled */
#define ENABLE_REG_32BIT	(1 << 5)	/* Use 32-bit access */
#define VIRTUAL_IO_ADDRESS	(1 << 6)	/* Clock in virtual address */
#define CLOCK_IDLE_CONTROL	(1 << 7)
#define CLOCK_NO_IDLE_PARENT	(1 << 8)
#define DELAYED_APP		(1 << 9)	/* Delay application of clock */
#define CONFIG_PARTICIPANT	(1 << 10)	/* Fundamental clock */
#define ENABLE_ON_INIT		(1 << 11)	/* Enable upon framework init */
#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
/* bits 13-20 are currently free */
#define CLOCK_IN_OMAP310	(1 << 21)
#define CLOCK_IN_OMAP730	(1 << 22)
#define CLOCK_IN_OMAP1510	(1 << 23)
#define CLOCK_IN_OMAP16XX	(1 << 24)
#define CLOCK_IN_OMAP242X	(1 << 25)
#define CLOCK_IN_OMAP243X	(1 << 26)
#define CLOCK_IN_OMAP343X	(1 << 27)	/* clocks common to all 343X */
#define PARENT_CONTROLS_CLOCK	(1 << 28)
#define CLOCK_IN_OMAP3430ES1	(1 << 29)	/* 3430ES1 clocks only */
#define CLOCK_IN_OMAP3430ES2	(1 << 30)	/* 3430ES2 clocks only */

/* Clksel_rate flags */
#define DEFAULT_RATE		(1 << 0)
#define RATE_IN_242X		(1 << 1)
#define RATE_IN_243X		(1 << 2)
#define RATE_IN_343X		(1 << 3)	/* rates common to all 343X */
#define RATE_IN_3430ES2		(1 << 4)	/* 3430ES2 rates only */

#define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)


/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
#define CORE_CLK_SRC_32K		0
#define CORE_CLK_SRC_DPLL		1
#define CORE_CLK_SRC_DPLL_X2		2

#endif
Commit	Line	Data
9ad5897c TL	1	/*
	2	* linux/include/asm-arm/arch-omap/clock.h
	3	*
	4	* Copyright (C) 2004 - 2005 Nokia corporation
	5	* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
	6	* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __ARCH_ARM_OMAP_CLOCK_H
	14	#define __ARCH_ARM_OMAP_CLOCK_H
	15
	16	struct module;
6b8858a9 PW	17	struct clk;
6b8858a9 PW	18
b045d080	19	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
6b8858a9 PW	20
	21	struct clksel_rate {
	22	u8 div;
	23	u32 val;
	24	u8 flags;
	25	};
	26
	27	struct clksel {
	28	struct clk *parent;
	29	const struct clksel_rate *rates;
	30	};
	31
	32	struct dpll_data {
	33	void __iomem *mult_div1_reg;
	34	u32 mult_mask;
	35	u32 div1_mask;
b045d080	36	# if defined(CONFIG_ARCH_OMAP3)
542313cc	37	u8 modes;
b045d080 PW	38	void __iomem *control_reg;
	39	u32 enable_mask;
	40	u8 auto_recal_bit;
	41	u8 recal_en_bit;
	42	u8 recal_st_bit;
542313cc PW	43	void __iomem *autoidle_reg;
	44	u32 autoidle_mask;
	45	void __iomem *idlest_reg;
	46	u8 idlest_bit;
b045d080	47	# endif
6b8858a9 PW	48	};
	49
	50	#endif
9ad5897c TL	51
	52	struct clk {
	53	struct list_head node;
	54	struct module *owner;
	55	const char *name;
b824efae	56	int id;
9ad5897c TL	57	struct clk *parent;
	58	unsigned long rate;
	59	__u32 flags;
	60	void __iomem *enable_reg;
	61	__u8 enable_bit;
9ad5897c TL	62	__s8 usecount;
	63	void (recalc)(struct clk );
	64	int (set_rate)(struct clk , unsigned long);
	65	long (round_rate)(struct clk , unsigned long);
	66	void (init)(struct clk );
	67	int (enable)(struct clk );
	68	void (disable)(struct clk );
b045d080	69	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
6b8858a9 PW	70	u8 fixed_div;
	71	void __iomem *clksel_reg;
	72	u32 clksel_mask;
	73	const struct clksel *clksel;
	74	const struct dpll_data *dpll_data;
	75	#else
	76	__u8 rate_offset;
	77	__u8 src_offset;
	78	#endif
137b3ee2 HD	79	#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
	80	struct dentry dent; / For visible tree hierarchy */
	81	#endif
9ad5897c TL	82	};
9ad5897c TL	83
b851cb28 RK	84	struct cpufreq_frequency_table;
b851cb28 RK	85
9ad5897c TL	86	struct clk_functions {
	87	int (clk_enable)(struct clk clk);
	88	void (clk_disable)(struct clk clk);
9ad5897c TL	89	long (clk_round_rate)(struct clk clk, unsigned long rate);
	90	int (clk_set_rate)(struct clk clk, unsigned long rate);
	91	int (clk_set_parent)(struct clk clk, struct clk *parent);
	92	struct clk * (clk_get_parent)(struct clk clk);
	93	void (clk_allow_idle)(struct clk clk);
	94	void (clk_deny_idle)(struct clk clk);
90afd5cb	95	void (clk_disable_unused)(struct clk clk);
b851cb28 RK	96	#ifdef CONFIG_CPU_FREQ
	97	void (clk_init_cpufreq_table)(struct cpufreq_frequency_table *);
	98	#endif
9ad5897c TL	99	};
	100
	101	extern unsigned int mpurate;
9ad5897c TL	102
	103	extern int clk_init(struct clk_functions * custom_clocks);
	104	extern int clk_register(struct clk *clk);
	105	extern void clk_unregister(struct clk *clk);
	106	extern void propagate_rate(struct clk *clk);
6b8858a9	107	extern void recalculate_root_clocks(void);
9ad5897c TL	108	extern void followparent_recalc(struct clk * clk);
	109	extern void clk_allow_idle(struct clk *clk);
	110	extern void clk_deny_idle(struct clk *clk);
b824efae	111	extern int clk_get_usecount(struct clk *clk);
6b8858a9	112	extern void clk_enable_init_clocks(void);
9ad5897c TL	113
	114	/* Clock flags */
	115	#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
	116	#define RATE_FIXED (1 << 1) /* Fixed clock rate */
	117	#define RATE_PROPAGATES (1 << 2) /* Program children too */
	118	#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
	119	#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
	120	#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
	121	#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
	122	#define CLOCK_IDLE_CONTROL (1 << 7)
	123	#define CLOCK_NO_IDLE_PARENT (1 << 8)
	124	#define DELAYED_APP (1 << 9) /* Delay application of clock */
	125	#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
6b8858a9 PW	126	#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
	127	#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
	128	/* bits 13-20 are currently free */
b824efae TL	129	#define CLOCK_IN_OMAP310 (1 << 21)
	130	#define CLOCK_IN_OMAP730 (1 << 22)
	131	#define CLOCK_IN_OMAP1510 (1 << 23)
	132	#define CLOCK_IN_OMAP16XX (1 << 24)
	133	#define CLOCK_IN_OMAP242X (1 << 25)
	134	#define CLOCK_IN_OMAP243X (1 << 26)
6b8858a9 PW	135	#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
	136	#define PARENT_CONTROLS_CLOCK (1 << 28)
	137	#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
	138	#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
	139
	140	/* Clksel_rate flags */
	141	#define DEFAULT_RATE (1 << 0)
	142	#define RATE_IN_242X (1 << 1)
	143	#define RATE_IN_243X (1 << 2)
	144	#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
	145	#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
	146
	147	#define RATE_IN_24XX (RATE_IN_242X \| RATE_IN_243X)
	148
9ad5897c	149
44595982 PW	150	/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
	151	#define CORE_CLK_SRC_32K 0
	152	#define CORE_CLK_SRC_DPLL 1
	153	#define CORE_CLK_SRC_DPLL_X2 2
	154
9ad5897c	155	#endif