xen: events: use per-cpu variable for cpu_evtchn_mask
[linux-2.6-block.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
3b32f574 110
cb60d114
IC
111static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
112 cpu_evtchn_mask);
e46cdb66 113
e46cdb66
JF
114/* Xen will never allocate port zero for any purpose. */
115#define VALID_EVTCHN(chn) ((chn) != 0)
116
e46cdb66 117static struct irq_chip xen_dynamic_chip;
aaca4964 118static struct irq_chip xen_percpu_chip;
d46a78b0 119static struct irq_chip xen_pirq_chip;
e46cdb66
JF
120
121/* Constructor for packed IRQ information. */
ced40d0f
JF
122static struct irq_info mk_unbound_info(void)
123{
124 return (struct irq_info) { .type = IRQT_UNBOUND };
125}
126
127static struct irq_info mk_evtchn_info(unsigned short evtchn)
128{
90af9514
IC
129 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
130 .cpu = 0 };
ced40d0f
JF
131}
132
133static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 134{
ced40d0f 135 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 136 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
137}
138
139static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
140{
141 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 142 .cpu = 0, .u.virq = virq };
ced40d0f
JF
143}
144
7a043f11 145static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
146 unsigned short gsi, unsigned short vector)
147{
148 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
149 .cpu = 0,
150 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
151}
152
153/*
154 * Accessors for packed IRQ information.
155 */
ced40d0f 156static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 157{
ced40d0f 158 return &irq_info[irq];
e46cdb66
JF
159}
160
ced40d0f 161static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 162{
110e7c7e
JJ
163 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
164 return 0;
165
ced40d0f 166 return info_for_irq(irq)->evtchn;
e46cdb66
JF
167}
168
d4c04536
IC
169unsigned irq_from_evtchn(unsigned int evtchn)
170{
171 return evtchn_to_irq[evtchn];
172}
173EXPORT_SYMBOL_GPL(irq_from_evtchn);
174
ced40d0f 175static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 176{
ced40d0f
JF
177 struct irq_info *info = info_for_irq(irq);
178
179 BUG_ON(info == NULL);
180 BUG_ON(info->type != IRQT_IPI);
181
182 return info->u.ipi;
183}
184
185static unsigned virq_from_irq(unsigned irq)
186{
187 struct irq_info *info = info_for_irq(irq);
188
189 BUG_ON(info == NULL);
190 BUG_ON(info->type != IRQT_VIRQ);
191
192 return info->u.virq;
193}
194
7a043f11
SS
195static unsigned pirq_from_irq(unsigned irq)
196{
197 struct irq_info *info = info_for_irq(irq);
198
199 BUG_ON(info == NULL);
200 BUG_ON(info->type != IRQT_PIRQ);
201
202 return info->u.pirq.pirq;
203}
204
ced40d0f
JF
205static unsigned gsi_from_irq(unsigned irq)
206{
207 struct irq_info *info = info_for_irq(irq);
208
209 BUG_ON(info == NULL);
210 BUG_ON(info->type != IRQT_PIRQ);
211
212 return info->u.pirq.gsi;
213}
214
ced40d0f
JF
215static enum xen_irq_type type_from_irq(unsigned irq)
216{
217 return info_for_irq(irq)->type;
218}
219
220static unsigned cpu_from_irq(unsigned irq)
221{
222 return info_for_irq(irq)->cpu;
223}
224
225static unsigned int cpu_from_evtchn(unsigned int evtchn)
226{
227 int irq = evtchn_to_irq[evtchn];
228 unsigned ret = 0;
229
230 if (irq != -1)
231 ret = cpu_from_irq(irq);
232
233 return ret;
e46cdb66
JF
234}
235
d46a78b0
JF
236static bool pirq_needs_eoi(unsigned irq)
237{
238 struct irq_info *info = info_for_irq(irq);
239
240 BUG_ON(info->type != IRQT_PIRQ);
241
242 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
243}
244
e46cdb66
JF
245static inline unsigned long active_evtchns(unsigned int cpu,
246 struct shared_info *sh,
247 unsigned int idx)
248{
249 return (sh->evtchn_pending[idx] &
cb60d114 250 per_cpu(cpu_evtchn_mask, cpu)[idx] &
e46cdb66
JF
251 ~sh->evtchn_mask[idx]);
252}
253
254static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
255{
256 int irq = evtchn_to_irq[chn];
257
258 BUG_ON(irq == -1);
259#ifdef CONFIG_SMP
c9e265e0 260 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
261#endif
262
cb60d114
IC
263 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
264 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 265
ced40d0f 266 irq_info[irq].cpu = cpu;
e46cdb66
JF
267}
268
269static void init_evtchn_cpu_bindings(void)
270{
1c6969ec 271 int i;
e46cdb66 272#ifdef CONFIG_SMP
10e58084 273 struct irq_desc *desc;
10e58084 274
e46cdb66 275 /* By default all event channels notify CPU#0. */
0b8f1efa 276 for_each_irq_desc(i, desc) {
c9e265e0 277 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 278 }
e46cdb66
JF
279#endif
280
1c6969ec 281 for_each_possible_cpu(i)
cb60d114
IC
282 memset(per_cpu(cpu_evtchn_mask, i),
283 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
1c6969ec 284
e46cdb66
JF
285}
286
e46cdb66
JF
287static inline void clear_evtchn(int port)
288{
289 struct shared_info *s = HYPERVISOR_shared_info;
290 sync_clear_bit(port, &s->evtchn_pending[0]);
291}
292
293static inline void set_evtchn(int port)
294{
295 struct shared_info *s = HYPERVISOR_shared_info;
296 sync_set_bit(port, &s->evtchn_pending[0]);
297}
298
168d2f46
JF
299static inline int test_evtchn(int port)
300{
301 struct shared_info *s = HYPERVISOR_shared_info;
302 return sync_test_bit(port, &s->evtchn_pending[0]);
303}
304
e46cdb66
JF
305
306/**
307 * notify_remote_via_irq - send event to remote end of event channel via irq
308 * @irq: irq of event channel to send event to
309 *
310 * Unlike notify_remote_via_evtchn(), this is safe to use across
311 * save/restore. Notifications on a broken connection are silently
312 * dropped.
313 */
314void notify_remote_via_irq(int irq)
315{
316 int evtchn = evtchn_from_irq(irq);
317
318 if (VALID_EVTCHN(evtchn))
319 notify_remote_via_evtchn(evtchn);
320}
321EXPORT_SYMBOL_GPL(notify_remote_via_irq);
322
323static void mask_evtchn(int port)
324{
325 struct shared_info *s = HYPERVISOR_shared_info;
326 sync_set_bit(port, &s->evtchn_mask[0]);
327}
328
329static void unmask_evtchn(int port)
330{
331 struct shared_info *s = HYPERVISOR_shared_info;
332 unsigned int cpu = get_cpu();
333
334 BUG_ON(!irqs_disabled());
335
336 /* Slow path (hypercall) if this is a non-local port. */
337 if (unlikely(cpu != cpu_from_evtchn(port))) {
338 struct evtchn_unmask unmask = { .port = port };
339 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
340 } else {
780f36d8 341 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
342
343 sync_clear_bit(port, &s->evtchn_mask[0]);
344
345 /*
346 * The following is basically the equivalent of
347 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
348 * the interrupt edge' if the channel is masked.
349 */
350 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
351 !sync_test_and_set_bit(port / BITS_PER_LONG,
352 &vcpu_info->evtchn_pending_sel))
353 vcpu_info->evtchn_upcall_pending = 1;
354 }
355
356 put_cpu();
357}
358
89911501 359static int xen_allocate_irq_dynamic(void)
0794bfc7 360{
89911501
IC
361 int first = 0;
362 int irq;
0794bfc7
KRW
363
364#ifdef CONFIG_X86_IO_APIC
89911501
IC
365 /*
366 * For an HVM guest or domain 0 which see "real" (emulated or
367 * actual repectively) GSIs we allocate dynamic IRQs
368 * e.g. those corresponding to event channels or MSIs
369 * etc. from the range above those "real" GSIs to avoid
370 * collisions.
371 */
372 if (xen_initial_domain() || xen_hvm_domain())
373 first = get_nr_irqs_gsi();
0794bfc7
KRW
374#endif
375
89911501
IC
376retry:
377 irq = irq_alloc_desc_from(first, -1);
3a69e916 378
89911501
IC
379 if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
380 printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
381 first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
382 goto retry;
99ad198c 383 }
e46cdb66 384
89911501
IC
385 if (irq < 0)
386 panic("No available IRQ to bind to: increase nr_irqs!\n");
ced40d0f 387
e46cdb66 388 return irq;
d46a78b0
JF
389}
390
c9df1ce5
IC
391static int xen_allocate_irq_gsi(unsigned gsi)
392{
393 int irq;
394
89911501
IC
395 /*
396 * A PV guest has no concept of a GSI (since it has no ACPI
397 * nor access to/knowledge of the physical APICs). Therefore
398 * all IRQs are dynamically allocated from the entire IRQ
399 * space.
400 */
401 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
402 return xen_allocate_irq_dynamic();
403
404 /* Legacy IRQ descriptors are already allocated by the arch. */
405 if (gsi < NR_IRQS_LEGACY)
406 return gsi;
407
408 irq = irq_alloc_desc_at(gsi, -1);
409 if (irq < 0)
410 panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
411
412 return irq;
413}
414
415static void xen_free_irq(unsigned irq)
416{
72146104
IC
417 /* Legacy IRQ descriptors are managed by the arch. */
418 if (irq < NR_IRQS_LEGACY)
419 return;
420
c9df1ce5
IC
421 irq_free_desc(irq);
422}
423
d46a78b0
JF
424static void pirq_unmask_notify(int irq)
425{
7a043f11 426 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
427
428 if (unlikely(pirq_needs_eoi(irq))) {
429 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
430 WARN_ON(rc);
431 }
432}
433
434static void pirq_query_unmask(int irq)
435{
436 struct physdev_irq_status_query irq_status;
437 struct irq_info *info = info_for_irq(irq);
438
439 BUG_ON(info->type != IRQT_PIRQ);
440
7a043f11 441 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
442 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
443 irq_status.flags = 0;
444
445 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
446 if (irq_status.flags & XENIRQSTAT_needs_eoi)
447 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
448}
449
450static bool probing_irq(int irq)
451{
452 struct irq_desc *desc = irq_to_desc(irq);
453
454 return desc && desc->action == NULL;
455}
456
c9e265e0 457static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
458{
459 struct evtchn_bind_pirq bind_pirq;
460 struct irq_info *info = info_for_irq(irq);
461 int evtchn = evtchn_from_irq(irq);
15ebbb82 462 int rc;
d46a78b0
JF
463
464 BUG_ON(info->type != IRQT_PIRQ);
465
466 if (VALID_EVTCHN(evtchn))
467 goto out;
468
7a043f11 469 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 470 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
471 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
472 BIND_PIRQ__WILL_SHARE : 0;
473 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
474 if (rc != 0) {
d46a78b0
JF
475 if (!probing_irq(irq))
476 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
477 irq);
478 return 0;
479 }
480 evtchn = bind_pirq.port;
481
482 pirq_query_unmask(irq);
483
484 evtchn_to_irq[evtchn] = irq;
485 bind_evtchn_to_cpu(evtchn, 0);
486 info->evtchn = evtchn;
487
488out:
489 unmask_evtchn(evtchn);
490 pirq_unmask_notify(irq);
491
492 return 0;
493}
494
c9e265e0
TG
495static unsigned int startup_pirq(struct irq_data *data)
496{
497 return __startup_pirq(data->irq);
498}
499
500static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
501{
502 struct evtchn_close close;
c9e265e0 503 unsigned int irq = data->irq;
d46a78b0
JF
504 struct irq_info *info = info_for_irq(irq);
505 int evtchn = evtchn_from_irq(irq);
506
507 BUG_ON(info->type != IRQT_PIRQ);
508
509 if (!VALID_EVTCHN(evtchn))
510 return;
511
512 mask_evtchn(evtchn);
513
514 close.port = evtchn;
515 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
516 BUG();
517
518 bind_evtchn_to_cpu(evtchn, 0);
519 evtchn_to_irq[evtchn] = -1;
520 info->evtchn = 0;
521}
522
c9e265e0 523static void enable_pirq(struct irq_data *data)
d46a78b0 524{
c9e265e0 525 startup_pirq(data);
d46a78b0
JF
526}
527
c9e265e0 528static void disable_pirq(struct irq_data *data)
d46a78b0
JF
529{
530}
531
c9e265e0 532static void ack_pirq(struct irq_data *data)
d46a78b0 533{
c9e265e0 534 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 535
aa673c1c 536 move_native_irq(data->irq);
d46a78b0
JF
537
538 if (VALID_EVTCHN(evtchn)) {
539 mask_evtchn(evtchn);
540 clear_evtchn(evtchn);
541 }
542}
543
d46a78b0
JF
544static int find_irq_by_gsi(unsigned gsi)
545{
546 int irq;
547
b21ddbf5 548 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
549 struct irq_info *info = info_for_irq(irq);
550
551 if (info == NULL || info->type != IRQT_PIRQ)
552 continue;
553
554 if (gsi_from_irq(irq) == gsi)
555 return irq;
556 }
557
558 return -1;
559}
560
f4d0635b 561int xen_allocate_pirq_gsi(unsigned gsi)
7a043f11 562{
f4d0635b 563 return gsi;
7a043f11
SS
564}
565
653378ac
IC
566/*
567 * Do not make any assumptions regarding the relationship between the
568 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
569 *
570 * Note: We don't assign an event channel until the irq actually started
571 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 572 */
f4d0635b
IC
573int xen_bind_pirq_gsi_to_irq(unsigned gsi,
574 unsigned pirq, int shareable, char *name)
d46a78b0 575{
a0e18116 576 int irq = -1;
d46a78b0
JF
577 struct physdev_irq irq_op;
578
579 spin_lock(&irq_mapping_update_lock);
580
e5fc7345 581 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 582 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
583 pirq > nr_irqs ? "pirq" :"",
584 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
585 goto out;
586 }
587
d46a78b0
JF
588 irq = find_irq_by_gsi(gsi);
589 if (irq != -1) {
7a043f11 590 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
591 irq, gsi);
592 goto out; /* XXX need refcount? */
593 }
594
c9df1ce5 595 irq = xen_allocate_irq_gsi(gsi);
d46a78b0
JF
596
597 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 598 handle_level_irq, name);
d46a78b0
JF
599
600 irq_op.irq = irq;
b5401a96
AN
601 irq_op.vector = 0;
602
603 /* Only the privileged domain can do this. For non-priv, the pcifront
604 * driver provides a PCI bus that does the call to do exactly
605 * this in the priv domain. */
606 if (xen_initial_domain() &&
607 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 608 xen_free_irq(irq);
d46a78b0
JF
609 irq = -ENOSPC;
610 goto out;
611 }
612
7a043f11 613 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 614 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 615 pirq_to_irq[pirq] = irq;
d46a78b0
JF
616
617out:
618 spin_unlock(&irq_mapping_update_lock);
619
620 return irq;
621}
622
f731e3ef 623#ifdef CONFIG_PCI_MSI
bf480d95 624int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 625{
5cad61a6 626 int rc;
cbf6aa89 627 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 628
bf480d95 629 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 630 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 631
5cad61a6
IC
632 WARN_ONCE(rc == -ENOSYS,
633 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
634
635 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
636}
637
bf480d95 638int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
ca1d8fe9 639 int pirq, int vector, const char *name)
809f9267 640{
bf480d95 641 int irq, ret;
4b41df7f 642
809f9267
SS
643 spin_lock(&irq_mapping_update_lock);
644
4b41df7f
IC
645 irq = xen_allocate_irq_dynamic();
646 if (irq == -1)
bb5d079a 647 goto out;
809f9267 648
4b41df7f 649 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
809f9267
SS
650 handle_level_irq, name);
651
ca1d8fe9 652 irq_info[irq] = mk_pirq_info(0, pirq, 0, vector);
bf480d95
IC
653 pirq_to_irq[pirq] = irq;
654 ret = set_irq_msi(irq, msidesc);
655 if (ret < 0)
656 goto error_irq;
809f9267
SS
657out:
658 spin_unlock(&irq_mapping_update_lock);
4b41df7f 659 return irq;
bf480d95
IC
660error_irq:
661 spin_unlock(&irq_mapping_update_lock);
662 xen_free_irq(irq);
663 return -1;
809f9267 664}
f731e3ef
QH
665#endif
666
b5401a96
AN
667int xen_destroy_irq(int irq)
668{
669 struct irq_desc *desc;
38aa66fc
JF
670 struct physdev_unmap_pirq unmap_irq;
671 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
672 int rc = -ENOENT;
673
674 spin_lock(&irq_mapping_update_lock);
675
676 desc = irq_to_desc(irq);
677 if (!desc)
678 goto out;
679
38aa66fc 680 if (xen_initial_domain()) {
12334715 681 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
682 unmap_irq.domid = DOMID_SELF;
683 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
684 if (rc) {
685 printk(KERN_WARNING "unmap irq failed %d\n", rc);
686 goto out;
687 }
688 }
1aa0b51a
KRW
689 pirq_to_irq[info->u.pirq.pirq] = -1;
690
b5401a96
AN
691 irq_info[irq] = mk_unbound_info();
692
c9df1ce5 693 xen_free_irq(irq);
b5401a96
AN
694
695out:
696 spin_unlock(&irq_mapping_update_lock);
697 return rc;
698}
699
af42b8d1
SS
700int xen_irq_from_pirq(unsigned pirq)
701{
702 return pirq_to_irq[pirq];
703}
704
b536b4b9 705int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
706{
707 int irq;
708
709 spin_lock(&irq_mapping_update_lock);
710
711 irq = evtchn_to_irq[evtchn];
712
713 if (irq == -1) {
c9df1ce5 714 irq = xen_allocate_irq_dynamic();
e46cdb66 715
e46cdb66 716 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 717 handle_fasteoi_irq, "event");
e46cdb66
JF
718
719 evtchn_to_irq[evtchn] = irq;
ced40d0f 720 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
721 }
722
e46cdb66
JF
723 spin_unlock(&irq_mapping_update_lock);
724
725 return irq;
726}
b536b4b9 727EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 728
f87e4cac
JF
729static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
730{
731 struct evtchn_bind_ipi bind_ipi;
732 int evtchn, irq;
733
734 spin_lock(&irq_mapping_update_lock);
735
736 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 737
f87e4cac 738 if (irq == -1) {
c9df1ce5 739 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
740 if (irq < 0)
741 goto out;
742
aaca4964
JF
743 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
744 handle_percpu_irq, "ipi");
f87e4cac
JF
745
746 bind_ipi.vcpu = cpu;
747 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
748 &bind_ipi) != 0)
749 BUG();
750 evtchn = bind_ipi.port;
751
752 evtchn_to_irq[evtchn] = irq;
ced40d0f 753 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
754 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
755
756 bind_evtchn_to_cpu(evtchn, cpu);
757 }
758
f87e4cac
JF
759 out:
760 spin_unlock(&irq_mapping_update_lock);
761 return irq;
762}
763
764
4fe7d5a7 765int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
766{
767 struct evtchn_bind_virq bind_virq;
768 int evtchn, irq;
769
770 spin_lock(&irq_mapping_update_lock);
771
772 irq = per_cpu(virq_to_irq, cpu)[virq];
773
774 if (irq == -1) {
c9df1ce5 775 irq = xen_allocate_irq_dynamic();
a52521f1
JF
776
777 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
778 handle_percpu_irq, "virq");
779
e46cdb66
JF
780 bind_virq.virq = virq;
781 bind_virq.vcpu = cpu;
782 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
783 &bind_virq) != 0)
784 BUG();
785 evtchn = bind_virq.port;
786
e46cdb66 787 evtchn_to_irq[evtchn] = irq;
ced40d0f 788 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
789
790 per_cpu(virq_to_irq, cpu)[virq] = irq;
791
792 bind_evtchn_to_cpu(evtchn, cpu);
793 }
794
e46cdb66
JF
795 spin_unlock(&irq_mapping_update_lock);
796
797 return irq;
798}
799
800static void unbind_from_irq(unsigned int irq)
801{
802 struct evtchn_close close;
803 int evtchn = evtchn_from_irq(irq);
804
805 spin_lock(&irq_mapping_update_lock);
806
d77bbd4d 807 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
808 close.port = evtchn;
809 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
810 BUG();
811
812 switch (type_from_irq(irq)) {
813 case IRQT_VIRQ:
814 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 815 [virq_from_irq(irq)] = -1;
e46cdb66 816 break;
d68d82af
AN
817 case IRQT_IPI:
818 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 819 [ipi_from_irq(irq)] = -1;
d68d82af 820 break;
e46cdb66
JF
821 default:
822 break;
823 }
824
825 /* Closed ports are implicitly re-bound to VCPU0. */
826 bind_evtchn_to_cpu(evtchn, 0);
827
828 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
829 }
830
831 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 832 irq_info[irq] = mk_unbound_info();
e46cdb66 833
c9df1ce5 834 xen_free_irq(irq);
e46cdb66
JF
835 }
836
837 spin_unlock(&irq_mapping_update_lock);
838}
839
840int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 841 irq_handler_t handler,
e46cdb66
JF
842 unsigned long irqflags,
843 const char *devname, void *dev_id)
844{
845 unsigned int irq;
846 int retval;
847
848 irq = bind_evtchn_to_irq(evtchn);
849 retval = request_irq(irq, handler, irqflags, devname, dev_id);
850 if (retval != 0) {
851 unbind_from_irq(irq);
852 return retval;
853 }
854
855 return irq;
856}
857EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
858
859int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 860 irq_handler_t handler,
e46cdb66
JF
861 unsigned long irqflags, const char *devname, void *dev_id)
862{
863 unsigned int irq;
864 int retval;
865
866 irq = bind_virq_to_irq(virq, cpu);
867 retval = request_irq(irq, handler, irqflags, devname, dev_id);
868 if (retval != 0) {
869 unbind_from_irq(irq);
870 return retval;
871 }
872
873 return irq;
874}
875EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
876
f87e4cac
JF
877int bind_ipi_to_irqhandler(enum ipi_vector ipi,
878 unsigned int cpu,
879 irq_handler_t handler,
880 unsigned long irqflags,
881 const char *devname,
882 void *dev_id)
883{
884 int irq, retval;
885
886 irq = bind_ipi_to_irq(ipi, cpu);
887 if (irq < 0)
888 return irq;
889
676dc3cf 890 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
f87e4cac
JF
891 retval = request_irq(irq, handler, irqflags, devname, dev_id);
892 if (retval != 0) {
893 unbind_from_irq(irq);
894 return retval;
895 }
896
897 return irq;
898}
899
e46cdb66
JF
900void unbind_from_irqhandler(unsigned int irq, void *dev_id)
901{
902 free_irq(irq, dev_id);
903 unbind_from_irq(irq);
904}
905EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
906
f87e4cac
JF
907void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
908{
909 int irq = per_cpu(ipi_to_irq, cpu)[vector];
910 BUG_ON(irq < 0);
911 notify_remote_via_irq(irq);
912}
913
ee523ca1
JF
914irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
915{
916 struct shared_info *sh = HYPERVISOR_shared_info;
917 int cpu = smp_processor_id();
cb60d114 918 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
919 int i;
920 unsigned long flags;
921 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 922 struct vcpu_info *v;
ee523ca1
JF
923
924 spin_lock_irqsave(&debug_lock, flags);
925
cb52e6d9 926 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
927
928 for_each_online_cpu(i) {
cb52e6d9
IC
929 int pending;
930 v = per_cpu(xen_vcpu, i);
931 pending = (get_irq_regs() && i == cpu)
932 ? xen_irqs_disabled(get_irq_regs())
933 : v->evtchn_upcall_mask;
934 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
935 pending, v->evtchn_upcall_pending,
936 (int)(sizeof(v->evtchn_pending_sel)*2),
937 v->evtchn_pending_sel);
938 }
939 v = per_cpu(xen_vcpu, cpu);
940
941 printk("\npending:\n ");
942 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
943 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
944 sh->evtchn_pending[i],
945 i % 8 == 0 ? "\n " : " ");
946 printk("\nglobal mask:\n ");
947 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
948 printk("%0*lx%s",
949 (int)(sizeof(sh->evtchn_mask[0])*2),
950 sh->evtchn_mask[i],
951 i % 8 == 0 ? "\n " : " ");
952
953 printk("\nglobally unmasked:\n ");
954 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
955 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
956 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
957 i % 8 == 0 ? "\n " : " ");
958
959 printk("\nlocal cpu%d mask:\n ", cpu);
960 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
961 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
962 cpu_evtchn[i],
963 i % 8 == 0 ? "\n " : " ");
964
965 printk("\nlocally unmasked:\n ");
966 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
967 unsigned long pending = sh->evtchn_pending[i]
968 & ~sh->evtchn_mask[i]
969 & cpu_evtchn[i];
970 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
971 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 972 }
ee523ca1
JF
973
974 printk("\npending list:\n");
cb52e6d9 975 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 976 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
977 int word_idx = i / BITS_PER_LONG;
978 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 979 cpu_from_evtchn(i), i,
cb52e6d9
IC
980 evtchn_to_irq[i],
981 sync_test_bit(word_idx, &v->evtchn_pending_sel)
982 ? "" : " l2-clear",
983 !sync_test_bit(i, sh->evtchn_mask)
984 ? "" : " globally-masked",
985 sync_test_bit(i, cpu_evtchn)
986 ? "" : " locally-masked");
ee523ca1
JF
987 }
988 }
989
990 spin_unlock_irqrestore(&debug_lock, flags);
991
992 return IRQ_HANDLED;
993}
994
245b2e70
TH
995static DEFINE_PER_CPU(unsigned, xed_nesting_count);
996
e46cdb66
JF
997/*
998 * Search the CPUs pending events bitmasks. For each one found, map
999 * the event number to an irq, and feed it into do_IRQ() for
1000 * handling.
1001 *
1002 * Xen uses a two-level bitmap to speed searching. The first level is
1003 * a bitset of words which contain pending event bits. The second
1004 * level is a bitset of pending events themselves.
1005 */
38e20b07 1006static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1007{
1008 int cpu = get_cpu();
1009 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1010 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1011 unsigned count;
e46cdb66 1012
229664be
JF
1013 do {
1014 unsigned long pending_words;
e46cdb66 1015
229664be 1016 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1017
b2e4ae69 1018 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1019 goto out;
e46cdb66 1020
e849c3e9
IY
1021#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1022 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1023 wmb();
e849c3e9 1024#endif
229664be
JF
1025 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1026 while (pending_words != 0) {
1027 unsigned long pending_bits;
1028 int word_idx = __ffs(pending_words);
1029 pending_words &= ~(1UL << word_idx);
1030
1031 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1032 int bit_idx = __ffs(pending_bits);
1033 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1034 int irq = evtchn_to_irq[port];
ca4dbc66 1035 struct irq_desc *desc;
229664be 1036
3588fe2e
JF
1037 mask_evtchn(port);
1038 clear_evtchn(port);
1039
ca4dbc66
EB
1040 if (irq != -1) {
1041 desc = irq_to_desc(irq);
1042 if (desc)
1043 generic_handle_irq_desc(irq, desc);
1044 }
e46cdb66
JF
1045 }
1046 }
e46cdb66 1047
229664be
JF
1048 BUG_ON(!irqs_disabled());
1049
780f36d8
CL
1050 count = __this_cpu_read(xed_nesting_count);
1051 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1052 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1053
1054out:
38e20b07
SY
1055
1056 put_cpu();
1057}
1058
1059void xen_evtchn_do_upcall(struct pt_regs *regs)
1060{
1061 struct pt_regs *old_regs = set_irq_regs(regs);
1062
1063 exit_idle();
1064 irq_enter();
1065
1066 __xen_evtchn_do_upcall();
1067
3445a8fd
JF
1068 irq_exit();
1069 set_irq_regs(old_regs);
38e20b07 1070}
3445a8fd 1071
38e20b07
SY
1072void xen_hvm_evtchn_do_upcall(void)
1073{
1074 __xen_evtchn_do_upcall();
e46cdb66 1075}
183d03cc 1076EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1077
eb1e305f
JF
1078/* Rebind a new event channel to an existing irq. */
1079void rebind_evtchn_irq(int evtchn, int irq)
1080{
d77bbd4d
JF
1081 struct irq_info *info = info_for_irq(irq);
1082
eb1e305f
JF
1083 /* Make sure the irq is masked, since the new event channel
1084 will also be masked. */
1085 disable_irq(irq);
1086
1087 spin_lock(&irq_mapping_update_lock);
1088
1089 /* After resume the irq<->evtchn mappings are all cleared out */
1090 BUG_ON(evtchn_to_irq[evtchn] != -1);
1091 /* Expect irq to have been bound before,
d77bbd4d
JF
1092 so there should be a proper type */
1093 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1094
1095 evtchn_to_irq[evtchn] = irq;
ced40d0f 1096 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1097
1098 spin_unlock(&irq_mapping_update_lock);
1099
1100 /* new event channels are always bound to cpu 0 */
0de26520 1101 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1102
1103 /* Unmask the event channel. */
1104 enable_irq(irq);
1105}
1106
e46cdb66 1107/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1108static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1109{
1110 struct evtchn_bind_vcpu bind_vcpu;
1111 int evtchn = evtchn_from_irq(irq);
1112
be49472f
IC
1113 if (!VALID_EVTCHN(evtchn))
1114 return -1;
1115
1116 /*
1117 * Events delivered via platform PCI interrupts are always
1118 * routed to vcpu 0 and hence cannot be rebound.
1119 */
1120 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1121 return -1;
e46cdb66
JF
1122
1123 /* Send future instances of this interrupt to other vcpu. */
1124 bind_vcpu.port = evtchn;
1125 bind_vcpu.vcpu = tcpu;
1126
1127 /*
1128 * If this fails, it usually just indicates that we're dealing with a
1129 * virq or IPI channel, which don't actually need to be rebound. Ignore
1130 * it, but don't do the xenlinux-level rebind in that case.
1131 */
1132 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1133 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1134
d5dedd45
YL
1135 return 0;
1136}
e46cdb66 1137
c9e265e0
TG
1138static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1139 bool force)
e46cdb66 1140{
0de26520 1141 unsigned tcpu = cpumask_first(dest);
d5dedd45 1142
c9e265e0 1143 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1144}
1145
642e0c88
IY
1146int resend_irq_on_evtchn(unsigned int irq)
1147{
1148 int masked, evtchn = evtchn_from_irq(irq);
1149 struct shared_info *s = HYPERVISOR_shared_info;
1150
1151 if (!VALID_EVTCHN(evtchn))
1152 return 1;
1153
1154 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1155 sync_set_bit(evtchn, s->evtchn_pending);
1156 if (!masked)
1157 unmask_evtchn(evtchn);
1158
1159 return 1;
1160}
1161
c9e265e0 1162static void enable_dynirq(struct irq_data *data)
e46cdb66 1163{
c9e265e0 1164 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1165
1166 if (VALID_EVTCHN(evtchn))
1167 unmask_evtchn(evtchn);
1168}
1169
c9e265e0 1170static void disable_dynirq(struct irq_data *data)
e46cdb66 1171{
c9e265e0 1172 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1173
1174 if (VALID_EVTCHN(evtchn))
1175 mask_evtchn(evtchn);
1176}
1177
c9e265e0 1178static void ack_dynirq(struct irq_data *data)
e46cdb66 1179{
c9e265e0 1180 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1181
c9e265e0 1182 move_masked_irq(data->irq);
e46cdb66
JF
1183
1184 if (VALID_EVTCHN(evtchn))
3588fe2e 1185 unmask_evtchn(evtchn);
e46cdb66
JF
1186}
1187
c9e265e0 1188static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1189{
c9e265e0 1190 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1191 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1192 int ret = 0;
1193
1194 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1195 int masked;
1196
1197 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1198 sync_set_bit(evtchn, sh->evtchn_pending);
1199 if (!masked)
1200 unmask_evtchn(evtchn);
e46cdb66
JF
1201 ret = 1;
1202 }
1203
1204 return ret;
1205}
1206
0a85226f 1207static void restore_pirqs(void)
9a069c33
SS
1208{
1209 int pirq, rc, irq, gsi;
1210 struct physdev_map_pirq map_irq;
1211
1212 for (pirq = 0; pirq < nr_irqs; pirq++) {
1213 irq = pirq_to_irq[pirq];
1214 if (irq == -1)
1215 continue;
1216
1217 /* save/restore of PT devices doesn't work, so at this point the
1218 * only devices present are GSI based emulated devices */
1219 gsi = gsi_from_irq(irq);
1220 if (!gsi)
1221 continue;
1222
1223 map_irq.domid = DOMID_SELF;
1224 map_irq.type = MAP_PIRQ_TYPE_GSI;
1225 map_irq.index = gsi;
1226 map_irq.pirq = pirq;
1227
1228 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1229 if (rc) {
1230 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1231 gsi, irq, pirq, rc);
1232 irq_info[irq] = mk_unbound_info();
1233 pirq_to_irq[pirq] = -1;
1234 continue;
1235 }
1236
1237 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1238
c9e265e0 1239 __startup_pirq(irq);
9a069c33
SS
1240 }
1241}
1242
0e91398f
JF
1243static void restore_cpu_virqs(unsigned int cpu)
1244{
1245 struct evtchn_bind_virq bind_virq;
1246 int virq, irq, evtchn;
1247
1248 for (virq = 0; virq < NR_VIRQS; virq++) {
1249 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1250 continue;
1251
ced40d0f 1252 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1253
1254 /* Get a new binding from Xen. */
1255 bind_virq.virq = virq;
1256 bind_virq.vcpu = cpu;
1257 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1258 &bind_virq) != 0)
1259 BUG();
1260 evtchn = bind_virq.port;
1261
1262 /* Record the new mapping. */
1263 evtchn_to_irq[evtchn] = irq;
ced40d0f 1264 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1265 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1266 }
1267}
1268
1269static void restore_cpu_ipis(unsigned int cpu)
1270{
1271 struct evtchn_bind_ipi bind_ipi;
1272 int ipi, irq, evtchn;
1273
1274 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1275 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1276 continue;
1277
ced40d0f 1278 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1279
1280 /* Get a new binding from Xen. */
1281 bind_ipi.vcpu = cpu;
1282 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1283 &bind_ipi) != 0)
1284 BUG();
1285 evtchn = bind_ipi.port;
1286
1287 /* Record the new mapping. */
1288 evtchn_to_irq[evtchn] = irq;
ced40d0f 1289 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1290 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1291 }
1292}
1293
2d9e1e2f
JF
1294/* Clear an irq's pending state, in preparation for polling on it */
1295void xen_clear_irq_pending(int irq)
1296{
1297 int evtchn = evtchn_from_irq(irq);
1298
1299 if (VALID_EVTCHN(evtchn))
1300 clear_evtchn(evtchn);
1301}
d9a8814f 1302EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1303void xen_set_irq_pending(int irq)
1304{
1305 int evtchn = evtchn_from_irq(irq);
1306
1307 if (VALID_EVTCHN(evtchn))
1308 set_evtchn(evtchn);
1309}
1310
1311bool xen_test_irq_pending(int irq)
1312{
1313 int evtchn = evtchn_from_irq(irq);
1314 bool ret = false;
1315
1316 if (VALID_EVTCHN(evtchn))
1317 ret = test_evtchn(evtchn);
1318
1319 return ret;
1320}
1321
d9a8814f
KRW
1322/* Poll waiting for an irq to become pending with timeout. In the usual case,
1323 * the irq will be disabled so it won't deliver an interrupt. */
1324void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1325{
1326 evtchn_port_t evtchn = evtchn_from_irq(irq);
1327
1328 if (VALID_EVTCHN(evtchn)) {
1329 struct sched_poll poll;
1330
1331 poll.nr_ports = 1;
d9a8814f 1332 poll.timeout = timeout;
ff3c5362 1333 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1334
1335 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1336 BUG();
1337 }
1338}
d9a8814f
KRW
1339EXPORT_SYMBOL(xen_poll_irq_timeout);
1340/* Poll waiting for an irq to become pending. In the usual case, the
1341 * irq will be disabled so it won't deliver an interrupt. */
1342void xen_poll_irq(int irq)
1343{
1344 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1345}
2d9e1e2f 1346
0e91398f
JF
1347void xen_irq_resume(void)
1348{
1349 unsigned int cpu, irq, evtchn;
1350
1351 init_evtchn_cpu_bindings();
1352
1353 /* New event-channel space is not 'live' yet. */
1354 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1355 mask_evtchn(evtchn);
1356
1357 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1358 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1359 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1360
1361 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1362 evtchn_to_irq[evtchn] = -1;
1363
1364 for_each_possible_cpu(cpu) {
1365 restore_cpu_virqs(cpu);
1366 restore_cpu_ipis(cpu);
1367 }
6903591f 1368
0a85226f 1369 restore_pirqs();
0e91398f
JF
1370}
1371
e46cdb66 1372static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1373 .name = "xen-dyn",
54a353a0 1374
c9e265e0
TG
1375 .irq_disable = disable_dynirq,
1376 .irq_mask = disable_dynirq,
1377 .irq_unmask = enable_dynirq,
54a353a0 1378
c9e265e0
TG
1379 .irq_eoi = ack_dynirq,
1380 .irq_set_affinity = set_affinity_irq,
1381 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1382};
1383
d46a78b0 1384static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1385 .name = "xen-pirq",
d46a78b0 1386
c9e265e0
TG
1387 .irq_startup = startup_pirq,
1388 .irq_shutdown = shutdown_pirq,
d46a78b0 1389
c9e265e0
TG
1390 .irq_enable = enable_pirq,
1391 .irq_unmask = enable_pirq,
d46a78b0 1392
c9e265e0
TG
1393 .irq_disable = disable_pirq,
1394 .irq_mask = disable_pirq,
d46a78b0 1395
c9e265e0 1396 .irq_ack = ack_pirq,
d46a78b0 1397
c9e265e0 1398 .irq_set_affinity = set_affinity_irq,
d46a78b0 1399
c9e265e0 1400 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1401};
1402
aaca4964 1403static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1404 .name = "xen-percpu",
aaca4964 1405
c9e265e0
TG
1406 .irq_disable = disable_dynirq,
1407 .irq_mask = disable_dynirq,
1408 .irq_unmask = enable_dynirq,
aaca4964 1409
c9e265e0 1410 .irq_ack = ack_dynirq,
aaca4964
JF
1411};
1412
38e20b07
SY
1413int xen_set_callback_via(uint64_t via)
1414{
1415 struct xen_hvm_param a;
1416 a.domid = DOMID_SELF;
1417 a.index = HVM_PARAM_CALLBACK_IRQ;
1418 a.value = via;
1419 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1420}
1421EXPORT_SYMBOL_GPL(xen_set_callback_via);
1422
ca65f9fc 1423#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1424/* Vector callbacks are better than PCI interrupts to receive event
1425 * channel notifications because we can receive vector callbacks on any
1426 * vcpu and we don't need PCI support or APIC interactions. */
1427void xen_callback_vector(void)
1428{
1429 int rc;
1430 uint64_t callback_via;
1431 if (xen_have_vector_callback) {
1432 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1433 rc = xen_set_callback_via(callback_via);
1434 if (rc) {
1435 printk(KERN_ERR "Request for Xen HVM callback vector"
1436 " failed.\n");
1437 xen_have_vector_callback = 0;
1438 return;
1439 }
1440 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1441 "enabled\n");
1442 /* in the restore case the vector has already been allocated */
1443 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1444 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1445 }
1446}
ca65f9fc
SS
1447#else
1448void xen_callback_vector(void) {}
1449#endif
38e20b07 1450
e46cdb66
JF
1451void __init xen_init_IRQ(void)
1452{
e5fc7345 1453 int i;
c7a3589e 1454
b21ddbf5
JF
1455 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1456
e5fc7345
SS
1457 /* We are using nr_irqs as the maximum number of pirq available but
1458 * that number is actually chosen by Xen and we don't know exactly
1459 * what it is. Be careful choosing high pirq numbers. */
1460 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1461 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1462 pirq_to_irq[i] = -1;
1463
b21ddbf5
JF
1464 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1465 GFP_KERNEL);
1466 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1467 evtchn_to_irq[i] = -1;
e46cdb66
JF
1468
1469 init_evtchn_cpu_bindings();
1470
1471 /* No event channels are 'live' right now. */
1472 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1473 mask_evtchn(i);
1474
38e20b07
SY
1475 if (xen_hvm_domain()) {
1476 xen_callback_vector();
1477 native_init_IRQ();
3942b740
SS
1478 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1479 * __acpi_register_gsi can point at the right function */
1480 pci_xen_hvm_init();
38e20b07
SY
1481 } else {
1482 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1483 if (xen_initial_domain())
1484 xen_setup_pirqs();
38e20b07 1485 }
e46cdb66 1486}