xen/irq: Check if the PCI device is owned by a domain different than DOMID_SELF.
[linux-2.6-block.git] / drivers / xen / events.c
CommitLineData
e46cdb66
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1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
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20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
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35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
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47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
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53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
6cb6537d
IC
59static LIST_HEAD(xen_irq_list_head);
60
e46cdb66 61/* IRQ <-> VIRQ mapping. */
204fba4a 62static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 63
f87e4cac 64/* IRQ <-> IPI mapping */
204fba4a 65static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 66
ced40d0f
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67/* Interrupt types. */
68enum xen_irq_type {
d77bbd4d 69 IRQT_UNBOUND = 0,
f87e4cac
JF
70 IRQT_PIRQ,
71 IRQT_VIRQ,
72 IRQT_IPI,
73 IRQT_EVTCHN
74};
e46cdb66 75
ced40d0f
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76/*
77 * Packed IRQ information:
78 * type - enum xen_irq_type
79 * event channel - irq->event channel mapping
80 * cpu - cpu this event channel is bound to
81 * index - type-specific information:
42a1de56
SS
82 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
83 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
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84 * VIRQ - virq number
85 * IPI - IPI vector
86 * EVTCHN -
87 */
88struct irq_info
89{
6cb6537d 90 struct list_head list;
ced40d0f 91 enum xen_irq_type type; /* type */
6cb6537d 92 unsigned irq;
ced40d0f
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93 unsigned short evtchn; /* event channel */
94 unsigned short cpu; /* cpu bound */
95
96 union {
97 unsigned short virq;
98 enum ipi_vector ipi;
99 struct {
7a043f11 100 unsigned short pirq;
ced40d0f 101 unsigned short gsi;
d46a78b0
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102 unsigned char vector;
103 unsigned char flags;
beafbdc1 104 uint16_t domid;
ced40d0f
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105 } pirq;
106 } u;
107};
d46a78b0 108#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 109#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 110
b21ddbf5 111static int *evtchn_to_irq;
3b32f574 112
cb60d114
IC
113static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
114 cpu_evtchn_mask);
e46cdb66 115
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116/* Xen will never allocate port zero for any purpose. */
117#define VALID_EVTCHN(chn) ((chn) != 0)
118
e46cdb66 119static struct irq_chip xen_dynamic_chip;
aaca4964 120static struct irq_chip xen_percpu_chip;
d46a78b0 121static struct irq_chip xen_pirq_chip;
e46cdb66 122
9158c358
IC
123/* Get info for IRQ */
124static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 125{
c442b806 126 return irq_get_handler_data(irq);
ced40d0f
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127}
128
9158c358
IC
129/* Constructors for packed IRQ information. */
130static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 131 unsigned irq,
9158c358
IC
132 enum xen_irq_type type,
133 unsigned short evtchn,
134 unsigned short cpu)
ced40d0f 135{
9158c358
IC
136
137 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
138
139 info->type = type;
6cb6537d 140 info->irq = irq;
9158c358
IC
141 info->evtchn = evtchn;
142 info->cpu = cpu;
3d4cfa37
IC
143
144 evtchn_to_irq[evtchn] = irq;
ced40d0f
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145}
146
9158c358
IC
147static void xen_irq_info_evtchn_init(unsigned irq,
148 unsigned short evtchn)
ced40d0f 149{
9158c358
IC
150 struct irq_info *info = info_for_irq(irq);
151
3d4cfa37 152 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
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153}
154
3d4cfa37
IC
155static void xen_irq_info_ipi_init(unsigned cpu,
156 unsigned irq,
9158c358
IC
157 unsigned short evtchn,
158 enum ipi_vector ipi)
e46cdb66 159{
9158c358
IC
160 struct irq_info *info = info_for_irq(irq);
161
3d4cfa37 162 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
163
164 info->u.ipi = ipi;
3d4cfa37
IC
165
166 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
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167}
168
3d4cfa37
IC
169static void xen_irq_info_virq_init(unsigned cpu,
170 unsigned irq,
9158c358
IC
171 unsigned short evtchn,
172 unsigned short virq)
ced40d0f 173{
9158c358
IC
174 struct irq_info *info = info_for_irq(irq);
175
3d4cfa37 176 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
177
178 info->u.virq = virq;
3d4cfa37
IC
179
180 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
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181}
182
9158c358
IC
183static void xen_irq_info_pirq_init(unsigned irq,
184 unsigned short evtchn,
185 unsigned short pirq,
186 unsigned short gsi,
187 unsigned short vector,
beafbdc1 188 uint16_t domid,
9158c358 189 unsigned char flags)
ced40d0f 190{
9158c358
IC
191 struct irq_info *info = info_for_irq(irq);
192
3d4cfa37 193 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
194
195 info->u.pirq.pirq = pirq;
196 info->u.pirq.gsi = gsi;
197 info->u.pirq.vector = vector;
beafbdc1 198 info->u.pirq.domid = domid;
9158c358 199 info->u.pirq.flags = flags;
e46cdb66
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200}
201
202/*
203 * Accessors for packed IRQ information.
204 */
ced40d0f 205static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 206{
110e7c7e
JJ
207 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
208 return 0;
209
ced40d0f 210 return info_for_irq(irq)->evtchn;
e46cdb66
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211}
212
d4c04536
IC
213unsigned irq_from_evtchn(unsigned int evtchn)
214{
215 return evtchn_to_irq[evtchn];
216}
217EXPORT_SYMBOL_GPL(irq_from_evtchn);
218
ced40d0f 219static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 220{
ced40d0f
JF
221 struct irq_info *info = info_for_irq(irq);
222
223 BUG_ON(info == NULL);
224 BUG_ON(info->type != IRQT_IPI);
225
226 return info->u.ipi;
227}
228
229static unsigned virq_from_irq(unsigned irq)
230{
231 struct irq_info *info = info_for_irq(irq);
232
233 BUG_ON(info == NULL);
234 BUG_ON(info->type != IRQT_VIRQ);
235
236 return info->u.virq;
237}
238
7a043f11
SS
239static unsigned pirq_from_irq(unsigned irq)
240{
241 struct irq_info *info = info_for_irq(irq);
242
243 BUG_ON(info == NULL);
244 BUG_ON(info->type != IRQT_PIRQ);
245
246 return info->u.pirq.pirq;
247}
248
ced40d0f
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249static enum xen_irq_type type_from_irq(unsigned irq)
250{
251 return info_for_irq(irq)->type;
252}
253
254static unsigned cpu_from_irq(unsigned irq)
255{
256 return info_for_irq(irq)->cpu;
257}
258
259static unsigned int cpu_from_evtchn(unsigned int evtchn)
260{
261 int irq = evtchn_to_irq[evtchn];
262 unsigned ret = 0;
263
264 if (irq != -1)
265 ret = cpu_from_irq(irq);
266
267 return ret;
e46cdb66
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268}
269
d46a78b0
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270static bool pirq_needs_eoi(unsigned irq)
271{
272 struct irq_info *info = info_for_irq(irq);
273
274 BUG_ON(info->type != IRQT_PIRQ);
275
276 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
277}
278
e46cdb66
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279static inline unsigned long active_evtchns(unsigned int cpu,
280 struct shared_info *sh,
281 unsigned int idx)
282{
283 return (sh->evtchn_pending[idx] &
cb60d114 284 per_cpu(cpu_evtchn_mask, cpu)[idx] &
e46cdb66
JF
285 ~sh->evtchn_mask[idx]);
286}
287
288static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
289{
290 int irq = evtchn_to_irq[chn];
291
292 BUG_ON(irq == -1);
293#ifdef CONFIG_SMP
c9e265e0 294 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
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295#endif
296
cb60d114
IC
297 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
298 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 299
ca62ce8c 300 info_for_irq(irq)->cpu = cpu;
e46cdb66
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301}
302
303static void init_evtchn_cpu_bindings(void)
304{
1c6969ec 305 int i;
e46cdb66 306#ifdef CONFIG_SMP
6cb6537d 307 struct irq_info *info;
10e58084 308
e46cdb66 309 /* By default all event channels notify CPU#0. */
6cb6537d
IC
310 list_for_each_entry(info, &xen_irq_list_head, list) {
311 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 312 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 313 }
e46cdb66
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314#endif
315
1c6969ec 316 for_each_possible_cpu(i)
cb60d114
IC
317 memset(per_cpu(cpu_evtchn_mask, i),
318 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
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319}
320
e46cdb66
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321static inline void clear_evtchn(int port)
322{
323 struct shared_info *s = HYPERVISOR_shared_info;
324 sync_clear_bit(port, &s->evtchn_pending[0]);
325}
326
327static inline void set_evtchn(int port)
328{
329 struct shared_info *s = HYPERVISOR_shared_info;
330 sync_set_bit(port, &s->evtchn_pending[0]);
331}
332
168d2f46
JF
333static inline int test_evtchn(int port)
334{
335 struct shared_info *s = HYPERVISOR_shared_info;
336 return sync_test_bit(port, &s->evtchn_pending[0]);
337}
338
e46cdb66
JF
339
340/**
341 * notify_remote_via_irq - send event to remote end of event channel via irq
342 * @irq: irq of event channel to send event to
343 *
344 * Unlike notify_remote_via_evtchn(), this is safe to use across
345 * save/restore. Notifications on a broken connection are silently
346 * dropped.
347 */
348void notify_remote_via_irq(int irq)
349{
350 int evtchn = evtchn_from_irq(irq);
351
352 if (VALID_EVTCHN(evtchn))
353 notify_remote_via_evtchn(evtchn);
354}
355EXPORT_SYMBOL_GPL(notify_remote_via_irq);
356
357static void mask_evtchn(int port)
358{
359 struct shared_info *s = HYPERVISOR_shared_info;
360 sync_set_bit(port, &s->evtchn_mask[0]);
361}
362
363static void unmask_evtchn(int port)
364{
365 struct shared_info *s = HYPERVISOR_shared_info;
366 unsigned int cpu = get_cpu();
367
368 BUG_ON(!irqs_disabled());
369
370 /* Slow path (hypercall) if this is a non-local port. */
371 if (unlikely(cpu != cpu_from_evtchn(port))) {
372 struct evtchn_unmask unmask = { .port = port };
373 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
374 } else {
780f36d8 375 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
376
377 sync_clear_bit(port, &s->evtchn_mask[0]);
378
379 /*
380 * The following is basically the equivalent of
381 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
382 * the interrupt edge' if the channel is masked.
383 */
384 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
385 !sync_test_and_set_bit(port / BITS_PER_LONG,
386 &vcpu_info->evtchn_pending_sel))
387 vcpu_info->evtchn_upcall_pending = 1;
388 }
389
390 put_cpu();
391}
392
6cb6537d
IC
393static void xen_irq_init(unsigned irq)
394{
395 struct irq_info *info;
396 struct irq_desc *desc = irq_to_desc(irq);
397
44626e4a 398#ifdef CONFIG_SMP
6cb6537d
IC
399 /* By default all event channels notify CPU#0. */
400 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 401#endif
6cb6537d 402
ca62ce8c
IC
403 info = kzalloc(sizeof(*info), GFP_KERNEL);
404 if (info == NULL)
405 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
406
407 info->type = IRQT_UNBOUND;
408
c442b806 409 irq_set_handler_data(irq, info);
ca62ce8c 410
6cb6537d
IC
411 list_add_tail(&info->list, &xen_irq_list_head);
412}
413
7bee9768 414static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 415{
89911501
IC
416 int first = 0;
417 int irq;
0794bfc7
KRW
418
419#ifdef CONFIG_X86_IO_APIC
89911501
IC
420 /*
421 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 422 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
423 * e.g. those corresponding to event channels or MSIs
424 * etc. from the range above those "real" GSIs to avoid
425 * collisions.
426 */
427 if (xen_initial_domain() || xen_hvm_domain())
428 first = get_nr_irqs_gsi();
0794bfc7
KRW
429#endif
430
89911501 431 irq = irq_alloc_desc_from(first, -1);
3a69e916 432
6cb6537d 433 xen_irq_init(irq);
ced40d0f 434
e46cdb66 435 return irq;
d46a78b0
JF
436}
437
7bee9768 438static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
439{
440 int irq;
441
89911501
IC
442 /*
443 * A PV guest has no concept of a GSI (since it has no ACPI
444 * nor access to/knowledge of the physical APICs). Therefore
445 * all IRQs are dynamically allocated from the entire IRQ
446 * space.
447 */
448 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
449 return xen_allocate_irq_dynamic();
450
451 /* Legacy IRQ descriptors are already allocated by the arch. */
452 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
453 irq = gsi;
454 else
455 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 456
6cb6537d 457 xen_irq_init(irq);
c9df1ce5
IC
458
459 return irq;
460}
461
462static void xen_free_irq(unsigned irq)
463{
c442b806 464 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
465
466 list_del(&info->list);
9158c358 467
c442b806 468 irq_set_handler_data(irq, NULL);
ca62ce8c
IC
469
470 kfree(info);
471
72146104
IC
472 /* Legacy IRQ descriptors are managed by the arch. */
473 if (irq < NR_IRQS_LEGACY)
474 return;
475
c9df1ce5
IC
476 irq_free_desc(irq);
477}
478
d46a78b0
JF
479static void pirq_unmask_notify(int irq)
480{
7a043f11 481 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
482
483 if (unlikely(pirq_needs_eoi(irq))) {
484 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
485 WARN_ON(rc);
486 }
487}
488
489static void pirq_query_unmask(int irq)
490{
491 struct physdev_irq_status_query irq_status;
492 struct irq_info *info = info_for_irq(irq);
493
494 BUG_ON(info->type != IRQT_PIRQ);
495
7a043f11 496 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
497 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
498 irq_status.flags = 0;
499
500 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
501 if (irq_status.flags & XENIRQSTAT_needs_eoi)
502 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
503}
504
505static bool probing_irq(int irq)
506{
507 struct irq_desc *desc = irq_to_desc(irq);
508
509 return desc && desc->action == NULL;
510}
511
c9e265e0 512static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
513{
514 struct evtchn_bind_pirq bind_pirq;
515 struct irq_info *info = info_for_irq(irq);
516 int evtchn = evtchn_from_irq(irq);
15ebbb82 517 int rc;
d46a78b0
JF
518
519 BUG_ON(info->type != IRQT_PIRQ);
520
521 if (VALID_EVTCHN(evtchn))
522 goto out;
523
7a043f11 524 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 525 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
526 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
527 BIND_PIRQ__WILL_SHARE : 0;
528 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
529 if (rc != 0) {
d46a78b0
JF
530 if (!probing_irq(irq))
531 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
532 irq);
533 return 0;
534 }
535 evtchn = bind_pirq.port;
536
537 pirq_query_unmask(irq);
538
539 evtchn_to_irq[evtchn] = irq;
540 bind_evtchn_to_cpu(evtchn, 0);
541 info->evtchn = evtchn;
542
543out:
544 unmask_evtchn(evtchn);
545 pirq_unmask_notify(irq);
546
547 return 0;
548}
549
c9e265e0
TG
550static unsigned int startup_pirq(struct irq_data *data)
551{
552 return __startup_pirq(data->irq);
553}
554
555static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
556{
557 struct evtchn_close close;
c9e265e0 558 unsigned int irq = data->irq;
d46a78b0
JF
559 struct irq_info *info = info_for_irq(irq);
560 int evtchn = evtchn_from_irq(irq);
561
562 BUG_ON(info->type != IRQT_PIRQ);
563
564 if (!VALID_EVTCHN(evtchn))
565 return;
566
567 mask_evtchn(evtchn);
568
569 close.port = evtchn;
570 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
571 BUG();
572
573 bind_evtchn_to_cpu(evtchn, 0);
574 evtchn_to_irq[evtchn] = -1;
575 info->evtchn = 0;
576}
577
c9e265e0 578static void enable_pirq(struct irq_data *data)
d46a78b0 579{
c9e265e0 580 startup_pirq(data);
d46a78b0
JF
581}
582
c9e265e0 583static void disable_pirq(struct irq_data *data)
d46a78b0
JF
584{
585}
586
c9e265e0 587static void ack_pirq(struct irq_data *data)
d46a78b0 588{
c9e265e0 589 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 590
a3b975c4 591 irq_move_irq(data);
d46a78b0
JF
592
593 if (VALID_EVTCHN(evtchn)) {
594 mask_evtchn(evtchn);
595 clear_evtchn(evtchn);
596 }
597}
598
d46a78b0
JF
599static int find_irq_by_gsi(unsigned gsi)
600{
6cb6537d 601 struct irq_info *info;
d46a78b0 602
6cb6537d
IC
603 list_for_each_entry(info, &xen_irq_list_head, list) {
604 if (info->type != IRQT_PIRQ)
d46a78b0
JF
605 continue;
606
6cb6537d
IC
607 if (info->u.pirq.gsi == gsi)
608 return info->irq;
d46a78b0
JF
609 }
610
611 return -1;
612}
613
f4d0635b 614int xen_allocate_pirq_gsi(unsigned gsi)
7a043f11 615{
f4d0635b 616 return gsi;
7a043f11
SS
617}
618
653378ac
IC
619/*
620 * Do not make any assumptions regarding the relationship between the
621 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
622 *
623 * Note: We don't assign an event channel until the irq actually started
624 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 625 */
f4d0635b
IC
626int xen_bind_pirq_gsi_to_irq(unsigned gsi,
627 unsigned pirq, int shareable, char *name)
d46a78b0 628{
a0e18116 629 int irq = -1;
d46a78b0
JF
630 struct physdev_irq irq_op;
631
632 spin_lock(&irq_mapping_update_lock);
633
634 irq = find_irq_by_gsi(gsi);
635 if (irq != -1) {
7a043f11 636 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
637 irq, gsi);
638 goto out; /* XXX need refcount? */
639 }
640
c9df1ce5 641 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
642 if (irq < 0)
643 goto out;
d46a78b0 644
c442b806
TG
645 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
646 name);
d46a78b0
JF
647
648 irq_op.irq = irq;
b5401a96
AN
649 irq_op.vector = 0;
650
651 /* Only the privileged domain can do this. For non-priv, the pcifront
652 * driver provides a PCI bus that does the call to do exactly
653 * this in the priv domain. */
654 if (xen_initial_domain() &&
655 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 656 xen_free_irq(irq);
d46a78b0
JF
657 irq = -ENOSPC;
658 goto out;
659 }
660
beafbdc1 661 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 662 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0
JF
663
664out:
665 spin_unlock(&irq_mapping_update_lock);
666
667 return irq;
668}
669
f731e3ef 670#ifdef CONFIG_PCI_MSI
bf480d95 671int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 672{
5cad61a6 673 int rc;
cbf6aa89 674 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 675
bf480d95 676 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 677 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 678
5cad61a6
IC
679 WARN_ONCE(rc == -ENOSYS,
680 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
681
682 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
683}
684
bf480d95 685int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
686 int pirq, int vector, const char *name,
687 domid_t domid)
809f9267 688{
bf480d95 689 int irq, ret;
4b41df7f 690
809f9267
SS
691 spin_lock(&irq_mapping_update_lock);
692
4b41df7f
IC
693 irq = xen_allocate_irq_dynamic();
694 if (irq == -1)
bb5d079a 695 goto out;
809f9267 696
c442b806
TG
697 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
698 name);
809f9267 699
beafbdc1 700 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 701 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
702 if (ret < 0)
703 goto error_irq;
809f9267
SS
704out:
705 spin_unlock(&irq_mapping_update_lock);
4b41df7f 706 return irq;
bf480d95
IC
707error_irq:
708 spin_unlock(&irq_mapping_update_lock);
709 xen_free_irq(irq);
710 return -1;
809f9267 711}
f731e3ef
QH
712#endif
713
b5401a96
AN
714int xen_destroy_irq(int irq)
715{
716 struct irq_desc *desc;
38aa66fc
JF
717 struct physdev_unmap_pirq unmap_irq;
718 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
719 int rc = -ENOENT;
720
721 spin_lock(&irq_mapping_update_lock);
722
723 desc = irq_to_desc(irq);
724 if (!desc)
725 goto out;
726
38aa66fc 727 if (xen_initial_domain()) {
12334715 728 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 729 unmap_irq.domid = info->u.pirq.domid;
38aa66fc
JF
730 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
731 if (rc) {
732 printk(KERN_WARNING "unmap irq failed %d\n", rc);
733 goto out;
734 }
735 }
b5401a96 736
c9df1ce5 737 xen_free_irq(irq);
b5401a96
AN
738
739out:
740 spin_unlock(&irq_mapping_update_lock);
741 return rc;
742}
743
af42b8d1 744int xen_irq_from_pirq(unsigned pirq)
d46a78b0 745{
69c358ce 746 int irq;
d46a78b0 747
69c358ce 748 struct irq_info *info;
e46cdb66 749
69c358ce
IC
750 spin_lock(&irq_mapping_update_lock);
751
752 list_for_each_entry(info, &xen_irq_list_head, list) {
753 if (info == NULL || info->type != IRQT_PIRQ)
754 continue;
755 irq = info->irq;
756 if (info->u.pirq.pirq == pirq)
757 goto out;
758 }
759 irq = -1;
760out:
a7b807ce 761 spin_unlock(&irq_mapping_update_lock);
69c358ce
IC
762
763 return irq;
af42b8d1
SS
764}
765
b536b4b9 766int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
767{
768 int irq;
769
770 spin_lock(&irq_mapping_update_lock);
771
772 irq = evtchn_to_irq[evtchn];
773
774 if (irq == -1) {
c9df1ce5 775 irq = xen_allocate_irq_dynamic();
7bee9768
IC
776 if (irq == -1)
777 goto out;
e46cdb66 778
c442b806 779 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 780 handle_fasteoi_irq, "event");
e46cdb66 781
9158c358 782 xen_irq_info_evtchn_init(irq, evtchn);
e46cdb66
JF
783 }
784
7bee9768 785out:
e46cdb66
JF
786 spin_unlock(&irq_mapping_update_lock);
787
788 return irq;
789}
b536b4b9 790EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 791
f87e4cac
JF
792static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
793{
794 struct evtchn_bind_ipi bind_ipi;
795 int evtchn, irq;
796
797 spin_lock(&irq_mapping_update_lock);
798
799 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 800
f87e4cac 801 if (irq == -1) {
c9df1ce5 802 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
803 if (irq < 0)
804 goto out;
805
c442b806 806 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 807 handle_percpu_irq, "ipi");
f87e4cac
JF
808
809 bind_ipi.vcpu = cpu;
810 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
811 &bind_ipi) != 0)
812 BUG();
813 evtchn = bind_ipi.port;
814
3d4cfa37 815 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
816
817 bind_evtchn_to_cpu(evtchn, cpu);
818 }
819
f87e4cac
JF
820 out:
821 spin_unlock(&irq_mapping_update_lock);
822 return irq;
823}
824
2e820f58
IC
825static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
826 unsigned int remote_port)
827{
828 struct evtchn_bind_interdomain bind_interdomain;
829 int err;
830
831 bind_interdomain.remote_dom = remote_domain;
832 bind_interdomain.remote_port = remote_port;
833
834 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
835 &bind_interdomain);
836
837 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
838}
839
f87e4cac 840
4fe7d5a7 841int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
842{
843 struct evtchn_bind_virq bind_virq;
844 int evtchn, irq;
845
846 spin_lock(&irq_mapping_update_lock);
847
848 irq = per_cpu(virq_to_irq, cpu)[virq];
849
850 if (irq == -1) {
c9df1ce5 851 irq = xen_allocate_irq_dynamic();
7bee9768
IC
852 if (irq == -1)
853 goto out;
a52521f1 854
c442b806 855 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
856 handle_percpu_irq, "virq");
857
e46cdb66
JF
858 bind_virq.virq = virq;
859 bind_virq.vcpu = cpu;
860 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
861 &bind_virq) != 0)
862 BUG();
863 evtchn = bind_virq.port;
864
3d4cfa37 865 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
866
867 bind_evtchn_to_cpu(evtchn, cpu);
868 }
869
7bee9768 870out:
e46cdb66
JF
871 spin_unlock(&irq_mapping_update_lock);
872
873 return irq;
874}
875
876static void unbind_from_irq(unsigned int irq)
877{
878 struct evtchn_close close;
879 int evtchn = evtchn_from_irq(irq);
880
881 spin_lock(&irq_mapping_update_lock);
882
d77bbd4d 883 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
884 close.port = evtchn;
885 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
886 BUG();
887
888 switch (type_from_irq(irq)) {
889 case IRQT_VIRQ:
890 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 891 [virq_from_irq(irq)] = -1;
e46cdb66 892 break;
d68d82af
AN
893 case IRQT_IPI:
894 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 895 [ipi_from_irq(irq)] = -1;
d68d82af 896 break;
e46cdb66
JF
897 default:
898 break;
899 }
900
901 /* Closed ports are implicitly re-bound to VCPU0. */
902 bind_evtchn_to_cpu(evtchn, 0);
903
904 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
905 }
906
ca62ce8c 907 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 908
9158c358 909 xen_free_irq(irq);
e46cdb66
JF
910
911 spin_unlock(&irq_mapping_update_lock);
912}
913
914int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 915 irq_handler_t handler,
e46cdb66
JF
916 unsigned long irqflags,
917 const char *devname, void *dev_id)
918{
919 unsigned int irq;
920 int retval;
921
922 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
923 if (irq < 0)
924 return irq;
e46cdb66
JF
925 retval = request_irq(irq, handler, irqflags, devname, dev_id);
926 if (retval != 0) {
927 unbind_from_irq(irq);
928 return retval;
929 }
930
931 return irq;
932}
933EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
934
2e820f58
IC
935int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
936 unsigned int remote_port,
937 irq_handler_t handler,
938 unsigned long irqflags,
939 const char *devname,
940 void *dev_id)
941{
942 int irq, retval;
943
944 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
945 if (irq < 0)
946 return irq;
947
948 retval = request_irq(irq, handler, irqflags, devname, dev_id);
949 if (retval != 0) {
950 unbind_from_irq(irq);
951 return retval;
952 }
953
954 return irq;
955}
956EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
957
e46cdb66 958int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 959 irq_handler_t handler,
e46cdb66
JF
960 unsigned long irqflags, const char *devname, void *dev_id)
961{
962 unsigned int irq;
963 int retval;
964
965 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
966 if (irq < 0)
967 return irq;
e46cdb66
JF
968 retval = request_irq(irq, handler, irqflags, devname, dev_id);
969 if (retval != 0) {
970 unbind_from_irq(irq);
971 return retval;
972 }
973
974 return irq;
975}
976EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
977
f87e4cac
JF
978int bind_ipi_to_irqhandler(enum ipi_vector ipi,
979 unsigned int cpu,
980 irq_handler_t handler,
981 unsigned long irqflags,
982 const char *devname,
983 void *dev_id)
984{
985 int irq, retval;
986
987 irq = bind_ipi_to_irq(ipi, cpu);
988 if (irq < 0)
989 return irq;
990
676dc3cf 991 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
f87e4cac
JF
992 retval = request_irq(irq, handler, irqflags, devname, dev_id);
993 if (retval != 0) {
994 unbind_from_irq(irq);
995 return retval;
996 }
997
998 return irq;
999}
1000
e46cdb66
JF
1001void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1002{
1003 free_irq(irq, dev_id);
1004 unbind_from_irq(irq);
1005}
1006EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1007
f87e4cac
JF
1008void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1009{
1010 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1011 BUG_ON(irq < 0);
1012 notify_remote_via_irq(irq);
1013}
1014
ee523ca1
JF
1015irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1016{
1017 struct shared_info *sh = HYPERVISOR_shared_info;
1018 int cpu = smp_processor_id();
cb60d114 1019 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1020 int i;
1021 unsigned long flags;
1022 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1023 struct vcpu_info *v;
ee523ca1
JF
1024
1025 spin_lock_irqsave(&debug_lock, flags);
1026
cb52e6d9 1027 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1028
1029 for_each_online_cpu(i) {
cb52e6d9
IC
1030 int pending;
1031 v = per_cpu(xen_vcpu, i);
1032 pending = (get_irq_regs() && i == cpu)
1033 ? xen_irqs_disabled(get_irq_regs())
1034 : v->evtchn_upcall_mask;
1035 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1036 pending, v->evtchn_upcall_pending,
1037 (int)(sizeof(v->evtchn_pending_sel)*2),
1038 v->evtchn_pending_sel);
1039 }
1040 v = per_cpu(xen_vcpu, cpu);
1041
1042 printk("\npending:\n ");
1043 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1044 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1045 sh->evtchn_pending[i],
1046 i % 8 == 0 ? "\n " : " ");
1047 printk("\nglobal mask:\n ");
1048 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1049 printk("%0*lx%s",
1050 (int)(sizeof(sh->evtchn_mask[0])*2),
1051 sh->evtchn_mask[i],
1052 i % 8 == 0 ? "\n " : " ");
1053
1054 printk("\nglobally unmasked:\n ");
1055 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1056 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1057 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1058 i % 8 == 0 ? "\n " : " ");
1059
1060 printk("\nlocal cpu%d mask:\n ", cpu);
1061 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1062 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1063 cpu_evtchn[i],
1064 i % 8 == 0 ? "\n " : " ");
1065
1066 printk("\nlocally unmasked:\n ");
1067 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1068 unsigned long pending = sh->evtchn_pending[i]
1069 & ~sh->evtchn_mask[i]
1070 & cpu_evtchn[i];
1071 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1072 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1073 }
ee523ca1
JF
1074
1075 printk("\npending list:\n");
cb52e6d9 1076 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1077 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1078 int word_idx = i / BITS_PER_LONG;
1079 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1080 cpu_from_evtchn(i), i,
cb52e6d9
IC
1081 evtchn_to_irq[i],
1082 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1083 ? "" : " l2-clear",
1084 !sync_test_bit(i, sh->evtchn_mask)
1085 ? "" : " globally-masked",
1086 sync_test_bit(i, cpu_evtchn)
1087 ? "" : " locally-masked");
ee523ca1
JF
1088 }
1089 }
1090
1091 spin_unlock_irqrestore(&debug_lock, flags);
1092
1093 return IRQ_HANDLED;
1094}
1095
245b2e70 1096static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1097static DEFINE_PER_CPU(unsigned int, current_word_idx);
1098static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1099
ab7f863e
SR
1100/*
1101 * Mask out the i least significant bits of w
1102 */
1103#define MASK_LSBS(w, i) (w & ((~0UL) << i))
245b2e70 1104
e46cdb66
JF
1105/*
1106 * Search the CPUs pending events bitmasks. For each one found, map
1107 * the event number to an irq, and feed it into do_IRQ() for
1108 * handling.
1109 *
1110 * Xen uses a two-level bitmap to speed searching. The first level is
1111 * a bitset of words which contain pending event bits. The second
1112 * level is a bitset of pending events themselves.
1113 */
38e20b07 1114static void __xen_evtchn_do_upcall(void)
e46cdb66 1115{
24b51c2f 1116 int start_word_idx, start_bit_idx;
ab7f863e 1117 int word_idx, bit_idx;
24b51c2f 1118 int i;
e46cdb66
JF
1119 int cpu = get_cpu();
1120 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1121 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1122 unsigned count;
e46cdb66 1123
229664be
JF
1124 do {
1125 unsigned long pending_words;
e46cdb66 1126
229664be 1127 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1128
b2e4ae69 1129 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1130 goto out;
e46cdb66 1131
e849c3e9
IY
1132#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1133 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1134 wmb();
e849c3e9 1135#endif
229664be 1136 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1137
24b51c2f
KF
1138 start_word_idx = __this_cpu_read(current_word_idx);
1139 start_bit_idx = __this_cpu_read(current_bit_idx);
1140
1141 word_idx = start_word_idx;
ab7f863e 1142
24b51c2f 1143 for (i = 0; pending_words != 0; i++) {
229664be 1144 unsigned long pending_bits;
ab7f863e 1145 unsigned long words;
229664be 1146
ab7f863e
SR
1147 words = MASK_LSBS(pending_words, word_idx);
1148
1149 /*
ada6814c 1150 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1151 */
1152 if (words == 0) {
ada6814c
KF
1153 word_idx = 0;
1154 bit_idx = 0;
ab7f863e
SR
1155 continue;
1156 }
1157 word_idx = __ffs(words);
229664be 1158
24b51c2f
KF
1159 pending_bits = active_evtchns(cpu, s, word_idx);
1160 bit_idx = 0; /* usually scan entire word from start */
1161 if (word_idx == start_word_idx) {
1162 /* We scan the starting word in two parts */
1163 if (i == 0)
1164 /* 1st time: start in the middle */
1165 bit_idx = start_bit_idx;
1166 else
1167 /* 2nd time: mask bits done already */
1168 bit_idx &= (1UL << start_bit_idx) - 1;
1169 }
1170
ab7f863e
SR
1171 do {
1172 unsigned long bits;
1173 int port, irq;
ca4dbc66 1174 struct irq_desc *desc;
229664be 1175
ab7f863e
SR
1176 bits = MASK_LSBS(pending_bits, bit_idx);
1177
1178 /* If we masked out all events, move on. */
ada6814c 1179 if (bits == 0)
ab7f863e 1180 break;
ab7f863e
SR
1181
1182 bit_idx = __ffs(bits);
1183
1184 /* Process port. */
1185 port = (word_idx * BITS_PER_LONG) + bit_idx;
1186 irq = evtchn_to_irq[port];
1187
3588fe2e
JF
1188 mask_evtchn(port);
1189 clear_evtchn(port);
1190
ca4dbc66
EB
1191 if (irq != -1) {
1192 desc = irq_to_desc(irq);
1193 if (desc)
1194 generic_handle_irq_desc(irq, desc);
1195 }
ab7f863e 1196
ada6814c
KF
1197 bit_idx = (bit_idx + 1) % BITS_PER_LONG;
1198
1199 /* Next caller starts at last processed + 1 */
1200 __this_cpu_write(current_word_idx,
1201 bit_idx ? word_idx :
1202 (word_idx+1) % BITS_PER_LONG);
1203 __this_cpu_write(current_bit_idx, bit_idx);
1204 } while (bit_idx != 0);
ab7f863e 1205
24b51c2f
KF
1206 /* Scan start_l1i twice; all others once. */
1207 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1208 pending_words &= ~(1UL << word_idx);
ada6814c
KF
1209
1210 word_idx = (word_idx + 1) % BITS_PER_LONG;
e46cdb66 1211 }
e46cdb66 1212
229664be
JF
1213 BUG_ON(!irqs_disabled());
1214
780f36d8
CL
1215 count = __this_cpu_read(xed_nesting_count);
1216 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1217 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1218
1219out:
38e20b07
SY
1220
1221 put_cpu();
1222}
1223
1224void xen_evtchn_do_upcall(struct pt_regs *regs)
1225{
1226 struct pt_regs *old_regs = set_irq_regs(regs);
1227
1228 exit_idle();
1229 irq_enter();
1230
1231 __xen_evtchn_do_upcall();
1232
3445a8fd
JF
1233 irq_exit();
1234 set_irq_regs(old_regs);
38e20b07 1235}
3445a8fd 1236
38e20b07
SY
1237void xen_hvm_evtchn_do_upcall(void)
1238{
1239 __xen_evtchn_do_upcall();
e46cdb66 1240}
183d03cc 1241EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1242
eb1e305f
JF
1243/* Rebind a new event channel to an existing irq. */
1244void rebind_evtchn_irq(int evtchn, int irq)
1245{
d77bbd4d
JF
1246 struct irq_info *info = info_for_irq(irq);
1247
eb1e305f
JF
1248 /* Make sure the irq is masked, since the new event channel
1249 will also be masked. */
1250 disable_irq(irq);
1251
1252 spin_lock(&irq_mapping_update_lock);
1253
1254 /* After resume the irq<->evtchn mappings are all cleared out */
1255 BUG_ON(evtchn_to_irq[evtchn] != -1);
1256 /* Expect irq to have been bound before,
d77bbd4d
JF
1257 so there should be a proper type */
1258 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1259
9158c358 1260 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f
JF
1261
1262 spin_unlock(&irq_mapping_update_lock);
1263
1264 /* new event channels are always bound to cpu 0 */
0de26520 1265 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1266
1267 /* Unmask the event channel. */
1268 enable_irq(irq);
1269}
1270
e46cdb66 1271/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1272static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1273{
1274 struct evtchn_bind_vcpu bind_vcpu;
1275 int evtchn = evtchn_from_irq(irq);
1276
be49472f
IC
1277 if (!VALID_EVTCHN(evtchn))
1278 return -1;
1279
1280 /*
1281 * Events delivered via platform PCI interrupts are always
1282 * routed to vcpu 0 and hence cannot be rebound.
1283 */
1284 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1285 return -1;
e46cdb66
JF
1286
1287 /* Send future instances of this interrupt to other vcpu. */
1288 bind_vcpu.port = evtchn;
1289 bind_vcpu.vcpu = tcpu;
1290
1291 /*
1292 * If this fails, it usually just indicates that we're dealing with a
1293 * virq or IPI channel, which don't actually need to be rebound. Ignore
1294 * it, but don't do the xenlinux-level rebind in that case.
1295 */
1296 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1297 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1298
d5dedd45
YL
1299 return 0;
1300}
e46cdb66 1301
c9e265e0
TG
1302static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1303 bool force)
e46cdb66 1304{
0de26520 1305 unsigned tcpu = cpumask_first(dest);
d5dedd45 1306
c9e265e0 1307 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1308}
1309
642e0c88
IY
1310int resend_irq_on_evtchn(unsigned int irq)
1311{
1312 int masked, evtchn = evtchn_from_irq(irq);
1313 struct shared_info *s = HYPERVISOR_shared_info;
1314
1315 if (!VALID_EVTCHN(evtchn))
1316 return 1;
1317
1318 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1319 sync_set_bit(evtchn, s->evtchn_pending);
1320 if (!masked)
1321 unmask_evtchn(evtchn);
1322
1323 return 1;
1324}
1325
c9e265e0 1326static void enable_dynirq(struct irq_data *data)
e46cdb66 1327{
c9e265e0 1328 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1329
1330 if (VALID_EVTCHN(evtchn))
1331 unmask_evtchn(evtchn);
1332}
1333
c9e265e0 1334static void disable_dynirq(struct irq_data *data)
e46cdb66 1335{
c9e265e0 1336 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1337
1338 if (VALID_EVTCHN(evtchn))
1339 mask_evtchn(evtchn);
1340}
1341
c9e265e0 1342static void ack_dynirq(struct irq_data *data)
e46cdb66 1343{
c9e265e0 1344 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1345
a3b975c4 1346 irq_move_masked_irq(data);
e46cdb66
JF
1347
1348 if (VALID_EVTCHN(evtchn))
3588fe2e 1349 unmask_evtchn(evtchn);
e46cdb66
JF
1350}
1351
c9e265e0 1352static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1353{
c9e265e0 1354 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1355 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1356 int ret = 0;
1357
1358 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1359 int masked;
1360
1361 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1362 sync_set_bit(evtchn, sh->evtchn_pending);
1363 if (!masked)
1364 unmask_evtchn(evtchn);
e46cdb66
JF
1365 ret = 1;
1366 }
1367
1368 return ret;
1369}
1370
0a85226f 1371static void restore_pirqs(void)
9a069c33
SS
1372{
1373 int pirq, rc, irq, gsi;
1374 struct physdev_map_pirq map_irq;
69c358ce 1375 struct irq_info *info;
9a069c33 1376
69c358ce
IC
1377 list_for_each_entry(info, &xen_irq_list_head, list) {
1378 if (info->type != IRQT_PIRQ)
9a069c33
SS
1379 continue;
1380
69c358ce
IC
1381 pirq = info->u.pirq.pirq;
1382 gsi = info->u.pirq.gsi;
1383 irq = info->irq;
1384
9a069c33
SS
1385 /* save/restore of PT devices doesn't work, so at this point the
1386 * only devices present are GSI based emulated devices */
9a069c33
SS
1387 if (!gsi)
1388 continue;
1389
1390 map_irq.domid = DOMID_SELF;
1391 map_irq.type = MAP_PIRQ_TYPE_GSI;
1392 map_irq.index = gsi;
1393 map_irq.pirq = pirq;
1394
1395 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1396 if (rc) {
1397 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1398 gsi, irq, pirq, rc);
9158c358 1399 xen_free_irq(irq);
9a069c33
SS
1400 continue;
1401 }
1402
1403 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1404
c9e265e0 1405 __startup_pirq(irq);
9a069c33
SS
1406 }
1407}
1408
0e91398f
JF
1409static void restore_cpu_virqs(unsigned int cpu)
1410{
1411 struct evtchn_bind_virq bind_virq;
1412 int virq, irq, evtchn;
1413
1414 for (virq = 0; virq < NR_VIRQS; virq++) {
1415 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1416 continue;
1417
ced40d0f 1418 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1419
1420 /* Get a new binding from Xen. */
1421 bind_virq.virq = virq;
1422 bind_virq.vcpu = cpu;
1423 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1424 &bind_virq) != 0)
1425 BUG();
1426 evtchn = bind_virq.port;
1427
1428 /* Record the new mapping. */
3d4cfa37 1429 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1430 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1431 }
1432}
1433
1434static void restore_cpu_ipis(unsigned int cpu)
1435{
1436 struct evtchn_bind_ipi bind_ipi;
1437 int ipi, irq, evtchn;
1438
1439 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1440 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1441 continue;
1442
ced40d0f 1443 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1444
1445 /* Get a new binding from Xen. */
1446 bind_ipi.vcpu = cpu;
1447 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1448 &bind_ipi) != 0)
1449 BUG();
1450 evtchn = bind_ipi.port;
1451
1452 /* Record the new mapping. */
3d4cfa37 1453 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1454 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1455 }
1456}
1457
2d9e1e2f
JF
1458/* Clear an irq's pending state, in preparation for polling on it */
1459void xen_clear_irq_pending(int irq)
1460{
1461 int evtchn = evtchn_from_irq(irq);
1462
1463 if (VALID_EVTCHN(evtchn))
1464 clear_evtchn(evtchn);
1465}
d9a8814f 1466EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1467void xen_set_irq_pending(int irq)
1468{
1469 int evtchn = evtchn_from_irq(irq);
1470
1471 if (VALID_EVTCHN(evtchn))
1472 set_evtchn(evtchn);
1473}
1474
1475bool xen_test_irq_pending(int irq)
1476{
1477 int evtchn = evtchn_from_irq(irq);
1478 bool ret = false;
1479
1480 if (VALID_EVTCHN(evtchn))
1481 ret = test_evtchn(evtchn);
1482
1483 return ret;
1484}
1485
d9a8814f
KRW
1486/* Poll waiting for an irq to become pending with timeout. In the usual case,
1487 * the irq will be disabled so it won't deliver an interrupt. */
1488void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1489{
1490 evtchn_port_t evtchn = evtchn_from_irq(irq);
1491
1492 if (VALID_EVTCHN(evtchn)) {
1493 struct sched_poll poll;
1494
1495 poll.nr_ports = 1;
d9a8814f 1496 poll.timeout = timeout;
ff3c5362 1497 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1498
1499 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1500 BUG();
1501 }
1502}
d9a8814f
KRW
1503EXPORT_SYMBOL(xen_poll_irq_timeout);
1504/* Poll waiting for an irq to become pending. In the usual case, the
1505 * irq will be disabled so it won't deliver an interrupt. */
1506void xen_poll_irq(int irq)
1507{
1508 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1509}
2d9e1e2f 1510
0e91398f
JF
1511void xen_irq_resume(void)
1512{
6cb6537d
IC
1513 unsigned int cpu, evtchn;
1514 struct irq_info *info;
0e91398f
JF
1515
1516 init_evtchn_cpu_bindings();
1517
1518 /* New event-channel space is not 'live' yet. */
1519 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1520 mask_evtchn(evtchn);
1521
1522 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1523 list_for_each_entry(info, &xen_irq_list_head, list)
1524 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1525
1526 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1527 evtchn_to_irq[evtchn] = -1;
1528
1529 for_each_possible_cpu(cpu) {
1530 restore_cpu_virqs(cpu);
1531 restore_cpu_ipis(cpu);
1532 }
6903591f 1533
0a85226f 1534 restore_pirqs();
0e91398f
JF
1535}
1536
e46cdb66 1537static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1538 .name = "xen-dyn",
54a353a0 1539
c9e265e0
TG
1540 .irq_disable = disable_dynirq,
1541 .irq_mask = disable_dynirq,
1542 .irq_unmask = enable_dynirq,
54a353a0 1543
c9e265e0
TG
1544 .irq_eoi = ack_dynirq,
1545 .irq_set_affinity = set_affinity_irq,
1546 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1547};
1548
d46a78b0 1549static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1550 .name = "xen-pirq",
d46a78b0 1551
c9e265e0
TG
1552 .irq_startup = startup_pirq,
1553 .irq_shutdown = shutdown_pirq,
d46a78b0 1554
c9e265e0
TG
1555 .irq_enable = enable_pirq,
1556 .irq_unmask = enable_pirq,
d46a78b0 1557
c9e265e0
TG
1558 .irq_disable = disable_pirq,
1559 .irq_mask = disable_pirq,
d46a78b0 1560
c9e265e0 1561 .irq_ack = ack_pirq,
d46a78b0 1562
c9e265e0 1563 .irq_set_affinity = set_affinity_irq,
d46a78b0 1564
c9e265e0 1565 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1566};
1567
aaca4964 1568static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1569 .name = "xen-percpu",
aaca4964 1570
c9e265e0
TG
1571 .irq_disable = disable_dynirq,
1572 .irq_mask = disable_dynirq,
1573 .irq_unmask = enable_dynirq,
aaca4964 1574
c9e265e0 1575 .irq_ack = ack_dynirq,
aaca4964
JF
1576};
1577
38e20b07
SY
1578int xen_set_callback_via(uint64_t via)
1579{
1580 struct xen_hvm_param a;
1581 a.domid = DOMID_SELF;
1582 a.index = HVM_PARAM_CALLBACK_IRQ;
1583 a.value = via;
1584 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1585}
1586EXPORT_SYMBOL_GPL(xen_set_callback_via);
1587
ca65f9fc 1588#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1589/* Vector callbacks are better than PCI interrupts to receive event
1590 * channel notifications because we can receive vector callbacks on any
1591 * vcpu and we don't need PCI support or APIC interactions. */
1592void xen_callback_vector(void)
1593{
1594 int rc;
1595 uint64_t callback_via;
1596 if (xen_have_vector_callback) {
1597 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1598 rc = xen_set_callback_via(callback_via);
1599 if (rc) {
1600 printk(KERN_ERR "Request for Xen HVM callback vector"
1601 " failed.\n");
1602 xen_have_vector_callback = 0;
1603 return;
1604 }
1605 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1606 "enabled\n");
1607 /* in the restore case the vector has already been allocated */
1608 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1609 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1610 }
1611}
ca65f9fc
SS
1612#else
1613void xen_callback_vector(void) {}
1614#endif
38e20b07 1615
e46cdb66
JF
1616void __init xen_init_IRQ(void)
1617{
e5fc7345 1618 int i;
c7a3589e 1619
b21ddbf5
JF
1620 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1621 GFP_KERNEL);
1622 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1623 evtchn_to_irq[i] = -1;
e46cdb66
JF
1624
1625 init_evtchn_cpu_bindings();
1626
1627 /* No event channels are 'live' right now. */
1628 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1629 mask_evtchn(i);
1630
38e20b07
SY
1631 if (xen_hvm_domain()) {
1632 xen_callback_vector();
1633 native_init_IRQ();
3942b740
SS
1634 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1635 * __acpi_register_gsi can point at the right function */
1636 pci_xen_hvm_init();
38e20b07
SY
1637 } else {
1638 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1639 if (xen_initial_domain())
1640 xen_setup_pirqs();
38e20b07 1641 }
e46cdb66 1642}