Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
f731e3ef | 32 | #include <linux/pci.h> |
e46cdb66 | 33 | |
38e20b07 | 34 | #include <asm/desc.h> |
e46cdb66 JF |
35 | #include <asm/ptrace.h> |
36 | #include <asm/irq.h> | |
792dc4f6 | 37 | #include <asm/idle.h> |
0794bfc7 | 38 | #include <asm/io_apic.h> |
e46cdb66 | 39 | #include <asm/sync_bitops.h> |
42a1de56 | 40 | #include <asm/xen/pci.h> |
e46cdb66 | 41 | #include <asm/xen/hypercall.h> |
8d1b8753 | 42 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 43 | |
38e20b07 SY |
44 | #include <xen/xen.h> |
45 | #include <xen/hvm.h> | |
e04d0d07 | 46 | #include <xen/xen-ops.h> |
e46cdb66 JF |
47 | #include <xen/events.h> |
48 | #include <xen/interface/xen.h> | |
49 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
50 | #include <xen/interface/hvm/hvm_op.h> |
51 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 52 | |
e46cdb66 JF |
53 | /* |
54 | * This lock protects updates to the following mapping and reference-count | |
55 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
56 | */ | |
57 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
58 | ||
6cb6537d IC |
59 | static LIST_HEAD(xen_irq_list_head); |
60 | ||
e46cdb66 | 61 | /* IRQ <-> VIRQ mapping. */ |
204fba4a | 62 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 63 | |
f87e4cac | 64 | /* IRQ <-> IPI mapping */ |
204fba4a | 65 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 66 | |
ced40d0f JF |
67 | /* Interrupt types. */ |
68 | enum xen_irq_type { | |
d77bbd4d | 69 | IRQT_UNBOUND = 0, |
f87e4cac JF |
70 | IRQT_PIRQ, |
71 | IRQT_VIRQ, | |
72 | IRQT_IPI, | |
73 | IRQT_EVTCHN | |
74 | }; | |
e46cdb66 | 75 | |
ced40d0f JF |
76 | /* |
77 | * Packed IRQ information: | |
78 | * type - enum xen_irq_type | |
79 | * event channel - irq->event channel mapping | |
80 | * cpu - cpu this event channel is bound to | |
81 | * index - type-specific information: | |
42a1de56 SS |
82 | * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM |
83 | * guest, or GSI (real passthrough IRQ) of the device. | |
ced40d0f JF |
84 | * VIRQ - virq number |
85 | * IPI - IPI vector | |
86 | * EVTCHN - | |
87 | */ | |
88 | struct irq_info | |
89 | { | |
6cb6537d | 90 | struct list_head list; |
ced40d0f | 91 | enum xen_irq_type type; /* type */ |
6cb6537d | 92 | unsigned irq; |
ced40d0f JF |
93 | unsigned short evtchn; /* event channel */ |
94 | unsigned short cpu; /* cpu bound */ | |
95 | ||
96 | union { | |
97 | unsigned short virq; | |
98 | enum ipi_vector ipi; | |
99 | struct { | |
7a043f11 | 100 | unsigned short pirq; |
ced40d0f | 101 | unsigned short gsi; |
d46a78b0 JF |
102 | unsigned char vector; |
103 | unsigned char flags; | |
ced40d0f JF |
104 | } pirq; |
105 | } u; | |
106 | }; | |
d46a78b0 | 107 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 108 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 109 | |
b21ddbf5 | 110 | static int *evtchn_to_irq; |
3b32f574 | 111 | |
cb60d114 IC |
112 | static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG], |
113 | cpu_evtchn_mask); | |
e46cdb66 | 114 | |
e46cdb66 JF |
115 | /* Xen will never allocate port zero for any purpose. */ |
116 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
117 | ||
e46cdb66 | 118 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 119 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 120 | static struct irq_chip xen_pirq_chip; |
e46cdb66 | 121 | |
9158c358 IC |
122 | /* Get info for IRQ */ |
123 | static struct irq_info *info_for_irq(unsigned irq) | |
ced40d0f | 124 | { |
ca62ce8c | 125 | return get_irq_data(irq); |
ced40d0f JF |
126 | } |
127 | ||
9158c358 IC |
128 | /* Constructors for packed IRQ information. */ |
129 | static void xen_irq_info_common_init(struct irq_info *info, | |
3d4cfa37 | 130 | unsigned irq, |
9158c358 IC |
131 | enum xen_irq_type type, |
132 | unsigned short evtchn, | |
133 | unsigned short cpu) | |
ced40d0f | 134 | { |
9158c358 IC |
135 | |
136 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
137 | ||
138 | info->type = type; | |
6cb6537d | 139 | info->irq = irq; |
9158c358 IC |
140 | info->evtchn = evtchn; |
141 | info->cpu = cpu; | |
3d4cfa37 IC |
142 | |
143 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f JF |
144 | } |
145 | ||
9158c358 IC |
146 | static void xen_irq_info_evtchn_init(unsigned irq, |
147 | unsigned short evtchn) | |
e46cdb66 | 148 | { |
9158c358 IC |
149 | struct irq_info *info = info_for_irq(irq); |
150 | ||
3d4cfa37 | 151 | xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0); |
ced40d0f JF |
152 | } |
153 | ||
3d4cfa37 IC |
154 | static void xen_irq_info_ipi_init(unsigned cpu, |
155 | unsigned irq, | |
9158c358 IC |
156 | unsigned short evtchn, |
157 | enum ipi_vector ipi) | |
ced40d0f | 158 | { |
9158c358 IC |
159 | struct irq_info *info = info_for_irq(irq); |
160 | ||
3d4cfa37 | 161 | xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0); |
9158c358 IC |
162 | |
163 | info->u.ipi = ipi; | |
3d4cfa37 IC |
164 | |
165 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
ced40d0f JF |
166 | } |
167 | ||
3d4cfa37 IC |
168 | static void xen_irq_info_virq_init(unsigned cpu, |
169 | unsigned irq, | |
9158c358 IC |
170 | unsigned short evtchn, |
171 | unsigned short virq) | |
ced40d0f | 172 | { |
9158c358 IC |
173 | struct irq_info *info = info_for_irq(irq); |
174 | ||
3d4cfa37 | 175 | xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0); |
9158c358 IC |
176 | |
177 | info->u.virq = virq; | |
3d4cfa37 IC |
178 | |
179 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
e46cdb66 JF |
180 | } |
181 | ||
9158c358 IC |
182 | static void xen_irq_info_pirq_init(unsigned irq, |
183 | unsigned short evtchn, | |
184 | unsigned short pirq, | |
185 | unsigned short gsi, | |
186 | unsigned short vector, | |
187 | unsigned char flags) | |
e46cdb66 | 188 | { |
9158c358 IC |
189 | struct irq_info *info = info_for_irq(irq); |
190 | ||
3d4cfa37 | 191 | xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0); |
9158c358 IC |
192 | |
193 | info->u.pirq.pirq = pirq; | |
194 | info->u.pirq.gsi = gsi; | |
195 | info->u.pirq.vector = vector; | |
196 | info->u.pirq.flags = flags; | |
e46cdb66 JF |
197 | } |
198 | ||
9158c358 IC |
199 | /* |
200 | * Accessors for packed IRQ information. | |
201 | */ | |
ced40d0f | 202 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 203 | { |
110e7c7e JJ |
204 | if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
205 | return 0; | |
206 | ||
ced40d0f | 207 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
208 | } |
209 | ||
d4c04536 IC |
210 | unsigned irq_from_evtchn(unsigned int evtchn) |
211 | { | |
212 | return evtchn_to_irq[evtchn]; | |
213 | } | |
214 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
215 | ||
ced40d0f | 216 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 217 | { |
ced40d0f JF |
218 | struct irq_info *info = info_for_irq(irq); |
219 | ||
220 | BUG_ON(info == NULL); | |
221 | BUG_ON(info->type != IRQT_IPI); | |
222 | ||
223 | return info->u.ipi; | |
224 | } | |
225 | ||
226 | static unsigned virq_from_irq(unsigned irq) | |
227 | { | |
228 | struct irq_info *info = info_for_irq(irq); | |
229 | ||
230 | BUG_ON(info == NULL); | |
231 | BUG_ON(info->type != IRQT_VIRQ); | |
232 | ||
233 | return info->u.virq; | |
234 | } | |
235 | ||
7a043f11 SS |
236 | static unsigned pirq_from_irq(unsigned irq) |
237 | { | |
238 | struct irq_info *info = info_for_irq(irq); | |
239 | ||
240 | BUG_ON(info == NULL); | |
241 | BUG_ON(info->type != IRQT_PIRQ); | |
242 | ||
243 | return info->u.pirq.pirq; | |
244 | } | |
245 | ||
ced40d0f JF |
246 | static enum xen_irq_type type_from_irq(unsigned irq) |
247 | { | |
248 | return info_for_irq(irq)->type; | |
249 | } | |
250 | ||
251 | static unsigned cpu_from_irq(unsigned irq) | |
252 | { | |
253 | return info_for_irq(irq)->cpu; | |
254 | } | |
255 | ||
256 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
257 | { | |
258 | int irq = evtchn_to_irq[evtchn]; | |
259 | unsigned ret = 0; | |
260 | ||
261 | if (irq != -1) | |
262 | ret = cpu_from_irq(irq); | |
263 | ||
264 | return ret; | |
e46cdb66 JF |
265 | } |
266 | ||
d46a78b0 JF |
267 | static bool pirq_needs_eoi(unsigned irq) |
268 | { | |
269 | struct irq_info *info = info_for_irq(irq); | |
270 | ||
271 | BUG_ON(info->type != IRQT_PIRQ); | |
272 | ||
273 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
274 | } | |
275 | ||
e46cdb66 JF |
276 | static inline unsigned long active_evtchns(unsigned int cpu, |
277 | struct shared_info *sh, | |
278 | unsigned int idx) | |
279 | { | |
280 | return (sh->evtchn_pending[idx] & | |
cb60d114 | 281 | per_cpu(cpu_evtchn_mask, cpu)[idx] & |
e46cdb66 JF |
282 | ~sh->evtchn_mask[idx]); |
283 | } | |
284 | ||
285 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
286 | { | |
287 | int irq = evtchn_to_irq[chn]; | |
288 | ||
289 | BUG_ON(irq == -1); | |
290 | #ifdef CONFIG_SMP | |
c9e265e0 | 291 | cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu)); |
e46cdb66 JF |
292 | #endif |
293 | ||
cb60d114 IC |
294 | clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))); |
295 | set_bit(chn, per_cpu(cpu_evtchn_mask, cpu)); | |
e46cdb66 | 296 | |
ca62ce8c | 297 | info_for_irq(irq)->cpu = cpu; |
e46cdb66 JF |
298 | } |
299 | ||
300 | static void init_evtchn_cpu_bindings(void) | |
301 | { | |
1c6969ec | 302 | int i; |
e46cdb66 | 303 | #ifdef CONFIG_SMP |
6cb6537d | 304 | struct irq_info *info; |
10e58084 | 305 | |
e46cdb66 | 306 | /* By default all event channels notify CPU#0. */ |
6cb6537d IC |
307 | list_for_each_entry(info, &xen_irq_list_head, list) { |
308 | struct irq_desc *desc = irq_to_desc(info->irq); | |
c9e265e0 | 309 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); |
0b8f1efa | 310 | } |
e46cdb66 JF |
311 | #endif |
312 | ||
1c6969ec | 313 | for_each_possible_cpu(i) |
cb60d114 IC |
314 | memset(per_cpu(cpu_evtchn_mask, i), |
315 | (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i))); | |
e46cdb66 JF |
316 | } |
317 | ||
e46cdb66 JF |
318 | static inline void clear_evtchn(int port) |
319 | { | |
320 | struct shared_info *s = HYPERVISOR_shared_info; | |
321 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
322 | } | |
323 | ||
324 | static inline void set_evtchn(int port) | |
325 | { | |
326 | struct shared_info *s = HYPERVISOR_shared_info; | |
327 | sync_set_bit(port, &s->evtchn_pending[0]); | |
328 | } | |
329 | ||
168d2f46 JF |
330 | static inline int test_evtchn(int port) |
331 | { | |
332 | struct shared_info *s = HYPERVISOR_shared_info; | |
333 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
334 | } | |
335 | ||
e46cdb66 JF |
336 | |
337 | /** | |
338 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
339 | * @irq: irq of event channel to send event to | |
340 | * | |
341 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
342 | * save/restore. Notifications on a broken connection are silently | |
343 | * dropped. | |
344 | */ | |
345 | void notify_remote_via_irq(int irq) | |
346 | { | |
347 | int evtchn = evtchn_from_irq(irq); | |
348 | ||
349 | if (VALID_EVTCHN(evtchn)) | |
350 | notify_remote_via_evtchn(evtchn); | |
351 | } | |
352 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
353 | ||
354 | static void mask_evtchn(int port) | |
355 | { | |
356 | struct shared_info *s = HYPERVISOR_shared_info; | |
357 | sync_set_bit(port, &s->evtchn_mask[0]); | |
358 | } | |
359 | ||
360 | static void unmask_evtchn(int port) | |
361 | { | |
362 | struct shared_info *s = HYPERVISOR_shared_info; | |
363 | unsigned int cpu = get_cpu(); | |
364 | ||
365 | BUG_ON(!irqs_disabled()); | |
366 | ||
367 | /* Slow path (hypercall) if this is a non-local port. */ | |
368 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
369 | struct evtchn_unmask unmask = { .port = port }; | |
370 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
371 | } else { | |
780f36d8 | 372 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
e46cdb66 JF |
373 | |
374 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
375 | ||
376 | /* | |
377 | * The following is basically the equivalent of | |
378 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
379 | * the interrupt edge' if the channel is masked. | |
380 | */ | |
381 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
382 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
383 | &vcpu_info->evtchn_pending_sel)) | |
384 | vcpu_info->evtchn_upcall_pending = 1; | |
385 | } | |
386 | ||
387 | put_cpu(); | |
388 | } | |
389 | ||
6cb6537d IC |
390 | static void xen_irq_init(unsigned irq) |
391 | { | |
392 | struct irq_info *info; | |
393 | struct irq_desc *desc = irq_to_desc(irq); | |
394 | ||
395 | /* By default all event channels notify CPU#0. */ | |
396 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); | |
397 | ||
ca62ce8c IC |
398 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
399 | if (info == NULL) | |
400 | panic("Unable to allocate metadata for IRQ%d\n", irq); | |
6cb6537d IC |
401 | |
402 | info->type = IRQT_UNBOUND; | |
403 | ||
ca62ce8c IC |
404 | set_irq_data(irq, info); |
405 | ||
6cb6537d IC |
406 | list_add_tail(&info->list, &xen_irq_list_head); |
407 | } | |
408 | ||
89911501 | 409 | static int xen_allocate_irq_dynamic(void) |
0794bfc7 | 410 | { |
89911501 IC |
411 | int first = 0; |
412 | int irq; | |
0794bfc7 KRW |
413 | |
414 | #ifdef CONFIG_X86_IO_APIC | |
89911501 IC |
415 | /* |
416 | * For an HVM guest or domain 0 which see "real" (emulated or | |
417 | * actual repectively) GSIs we allocate dynamic IRQs | |
418 | * e.g. those corresponding to event channels or MSIs | |
419 | * etc. from the range above those "real" GSIs to avoid | |
420 | * collisions. | |
421 | */ | |
422 | if (xen_initial_domain() || xen_hvm_domain()) | |
423 | first = get_nr_irqs_gsi(); | |
0794bfc7 KRW |
424 | #endif |
425 | ||
89911501 | 426 | irq = irq_alloc_desc_from(first, -1); |
3a69e916 | 427 | |
89911501 IC |
428 | if (irq < 0) |
429 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
ced40d0f | 430 | |
6cb6537d IC |
431 | xen_irq_init(irq); |
432 | ||
e46cdb66 | 433 | return irq; |
d46a78b0 JF |
434 | } |
435 | ||
c9df1ce5 IC |
436 | static int xen_allocate_irq_gsi(unsigned gsi) |
437 | { | |
438 | int irq; | |
439 | ||
89911501 IC |
440 | /* |
441 | * A PV guest has no concept of a GSI (since it has no ACPI | |
442 | * nor access to/knowledge of the physical APICs). Therefore | |
443 | * all IRQs are dynamically allocated from the entire IRQ | |
444 | * space. | |
445 | */ | |
446 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
447 | return xen_allocate_irq_dynamic(); |
448 | ||
449 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
450 | if (gsi < NR_IRQS_LEGACY) | |
6cb6537d IC |
451 | irq = gsi; |
452 | else | |
453 | irq = irq_alloc_desc_at(gsi, -1); | |
c9df1ce5 | 454 | |
c9df1ce5 IC |
455 | if (irq < 0) |
456 | panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq); | |
457 | ||
6cb6537d IC |
458 | xen_irq_init(irq); |
459 | ||
c9df1ce5 IC |
460 | return irq; |
461 | } | |
462 | ||
463 | static void xen_free_irq(unsigned irq) | |
464 | { | |
ca62ce8c | 465 | struct irq_info *info = get_irq_data(irq); |
6cb6537d IC |
466 | |
467 | list_del(&info->list); | |
9158c358 | 468 | |
ca62ce8c IC |
469 | set_irq_data(irq, NULL); |
470 | ||
471 | kfree(info); | |
472 | ||
72146104 IC |
473 | /* Legacy IRQ descriptors are managed by the arch. */ |
474 | if (irq < NR_IRQS_LEGACY) | |
475 | return; | |
476 | ||
c9df1ce5 IC |
477 | irq_free_desc(irq); |
478 | } | |
479 | ||
d46a78b0 JF |
480 | static void pirq_unmask_notify(int irq) |
481 | { | |
7a043f11 | 482 | struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) }; |
d46a78b0 JF |
483 | |
484 | if (unlikely(pirq_needs_eoi(irq))) { | |
485 | int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
486 | WARN_ON(rc); | |
487 | } | |
488 | } | |
489 | ||
490 | static void pirq_query_unmask(int irq) | |
491 | { | |
492 | struct physdev_irq_status_query irq_status; | |
493 | struct irq_info *info = info_for_irq(irq); | |
494 | ||
495 | BUG_ON(info->type != IRQT_PIRQ); | |
496 | ||
7a043f11 | 497 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
498 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
499 | irq_status.flags = 0; | |
500 | ||
501 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
502 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
503 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
504 | } | |
505 | ||
506 | static bool probing_irq(int irq) | |
507 | { | |
508 | struct irq_desc *desc = irq_to_desc(irq); | |
509 | ||
510 | return desc && desc->action == NULL; | |
511 | } | |
512 | ||
c9e265e0 | 513 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
514 | { |
515 | struct evtchn_bind_pirq bind_pirq; | |
516 | struct irq_info *info = info_for_irq(irq); | |
517 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 518 | int rc; |
d46a78b0 JF |
519 | |
520 | BUG_ON(info->type != IRQT_PIRQ); | |
521 | ||
522 | if (VALID_EVTCHN(evtchn)) | |
523 | goto out; | |
524 | ||
7a043f11 | 525 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 526 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
527 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
528 | BIND_PIRQ__WILL_SHARE : 0; | |
529 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
530 | if (rc != 0) { | |
d46a78b0 JF |
531 | if (!probing_irq(irq)) |
532 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
533 | irq); | |
534 | return 0; | |
535 | } | |
536 | evtchn = bind_pirq.port; | |
537 | ||
538 | pirq_query_unmask(irq); | |
539 | ||
540 | evtchn_to_irq[evtchn] = irq; | |
541 | bind_evtchn_to_cpu(evtchn, 0); | |
542 | info->evtchn = evtchn; | |
543 | ||
544 | out: | |
545 | unmask_evtchn(evtchn); | |
546 | pirq_unmask_notify(irq); | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
c9e265e0 TG |
551 | static unsigned int startup_pirq(struct irq_data *data) |
552 | { | |
553 | return __startup_pirq(data->irq); | |
554 | } | |
555 | ||
556 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 JF |
557 | { |
558 | struct evtchn_close close; | |
c9e265e0 | 559 | unsigned int irq = data->irq; |
d46a78b0 JF |
560 | struct irq_info *info = info_for_irq(irq); |
561 | int evtchn = evtchn_from_irq(irq); | |
562 | ||
563 | BUG_ON(info->type != IRQT_PIRQ); | |
564 | ||
565 | if (!VALID_EVTCHN(evtchn)) | |
566 | return; | |
567 | ||
568 | mask_evtchn(evtchn); | |
569 | ||
570 | close.port = evtchn; | |
571 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
572 | BUG(); | |
573 | ||
574 | bind_evtchn_to_cpu(evtchn, 0); | |
575 | evtchn_to_irq[evtchn] = -1; | |
576 | info->evtchn = 0; | |
577 | } | |
578 | ||
c9e265e0 | 579 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 580 | { |
c9e265e0 | 581 | startup_pirq(data); |
d46a78b0 JF |
582 | } |
583 | ||
c9e265e0 | 584 | static void disable_pirq(struct irq_data *data) |
d46a78b0 JF |
585 | { |
586 | } | |
587 | ||
c9e265e0 | 588 | static void ack_pirq(struct irq_data *data) |
d46a78b0 | 589 | { |
c9e265e0 | 590 | int evtchn = evtchn_from_irq(data->irq); |
d46a78b0 | 591 | |
aa673c1c | 592 | move_native_irq(data->irq); |
d46a78b0 JF |
593 | |
594 | if (VALID_EVTCHN(evtchn)) { | |
595 | mask_evtchn(evtchn); | |
596 | clear_evtchn(evtchn); | |
597 | } | |
598 | } | |
599 | ||
d46a78b0 JF |
600 | static int find_irq_by_gsi(unsigned gsi) |
601 | { | |
6cb6537d | 602 | struct irq_info *info; |
d46a78b0 | 603 | |
6cb6537d IC |
604 | list_for_each_entry(info, &xen_irq_list_head, list) { |
605 | if (info->type != IRQT_PIRQ) | |
d46a78b0 JF |
606 | continue; |
607 | ||
6cb6537d IC |
608 | if (info->u.pirq.gsi == gsi) |
609 | return info->irq; | |
d46a78b0 JF |
610 | } |
611 | ||
612 | return -1; | |
613 | } | |
614 | ||
f4d0635b | 615 | int xen_allocate_pirq_gsi(unsigned gsi) |
7a043f11 | 616 | { |
f4d0635b | 617 | return gsi; |
7a043f11 SS |
618 | } |
619 | ||
653378ac IC |
620 | /* |
621 | * Do not make any assumptions regarding the relationship between the | |
622 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
623 | * |
624 | * Note: We don't assign an event channel until the irq actually started | |
625 | * up. Return an existing irq if we've already got one for the gsi. | |
d46a78b0 | 626 | */ |
f4d0635b IC |
627 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
628 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 629 | { |
a0e18116 | 630 | int irq = -1; |
d46a78b0 JF |
631 | struct physdev_irq irq_op; |
632 | ||
633 | spin_lock(&irq_mapping_update_lock); | |
634 | ||
635 | irq = find_irq_by_gsi(gsi); | |
636 | if (irq != -1) { | |
7a043f11 | 637 | printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n", |
d46a78b0 JF |
638 | irq, gsi); |
639 | goto out; /* XXX need refcount? */ | |
640 | } | |
641 | ||
c9df1ce5 | 642 | irq = xen_allocate_irq_gsi(gsi); |
d46a78b0 JF |
643 | |
644 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, | |
1a60d05f | 645 | handle_level_irq, name); |
d46a78b0 JF |
646 | |
647 | irq_op.irq = irq; | |
b5401a96 AN |
648 | irq_op.vector = 0; |
649 | ||
650 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
651 | * driver provides a PCI bus that does the call to do exactly | |
652 | * this in the priv domain. */ | |
653 | if (xen_initial_domain() && | |
654 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 655 | xen_free_irq(irq); |
d46a78b0 JF |
656 | irq = -ENOSPC; |
657 | goto out; | |
658 | } | |
659 | ||
9158c358 IC |
660 | xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, |
661 | shareable ? PIRQ_SHAREABLE : 0); | |
d46a78b0 JF |
662 | |
663 | out: | |
664 | spin_unlock(&irq_mapping_update_lock); | |
665 | ||
666 | return irq; | |
667 | } | |
668 | ||
f731e3ef | 669 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 670 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 671 | { |
5cad61a6 | 672 | int rc; |
cbf6aa89 | 673 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 674 | |
bf480d95 | 675 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 676 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 677 | |
5cad61a6 IC |
678 | WARN_ONCE(rc == -ENOSYS, |
679 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
680 | ||
681 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
682 | } |
683 | ||
bf480d95 | 684 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
ca1d8fe9 | 685 | int pirq, int vector, const char *name) |
809f9267 | 686 | { |
bf480d95 | 687 | int irq, ret; |
4b41df7f | 688 | |
809f9267 SS |
689 | spin_lock(&irq_mapping_update_lock); |
690 | ||
4b41df7f IC |
691 | irq = xen_allocate_irq_dynamic(); |
692 | if (irq == -1) | |
bb5d079a | 693 | goto out; |
809f9267 | 694 | |
4b41df7f | 695 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, |
809f9267 SS |
696 | handle_level_irq, name); |
697 | ||
9158c358 | 698 | xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, 0); |
bf480d95 IC |
699 | ret = set_irq_msi(irq, msidesc); |
700 | if (ret < 0) | |
701 | goto error_irq; | |
809f9267 SS |
702 | out: |
703 | spin_unlock(&irq_mapping_update_lock); | |
4b41df7f | 704 | return irq; |
bf480d95 IC |
705 | error_irq: |
706 | spin_unlock(&irq_mapping_update_lock); | |
707 | xen_free_irq(irq); | |
708 | return -1; | |
809f9267 | 709 | } |
f731e3ef QH |
710 | #endif |
711 | ||
b5401a96 AN |
712 | int xen_destroy_irq(int irq) |
713 | { | |
714 | struct irq_desc *desc; | |
38aa66fc JF |
715 | struct physdev_unmap_pirq unmap_irq; |
716 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
717 | int rc = -ENOENT; |
718 | ||
719 | spin_lock(&irq_mapping_update_lock); | |
720 | ||
721 | desc = irq_to_desc(irq); | |
722 | if (!desc) | |
723 | goto out; | |
724 | ||
38aa66fc | 725 | if (xen_initial_domain()) { |
12334715 | 726 | unmap_irq.pirq = info->u.pirq.pirq; |
38aa66fc JF |
727 | unmap_irq.domid = DOMID_SELF; |
728 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); | |
729 | if (rc) { | |
730 | printk(KERN_WARNING "unmap irq failed %d\n", rc); | |
731 | goto out; | |
732 | } | |
733 | } | |
1aa0b51a | 734 | |
c9df1ce5 | 735 | xen_free_irq(irq); |
b5401a96 AN |
736 | |
737 | out: | |
738 | spin_unlock(&irq_mapping_update_lock); | |
739 | return rc; | |
740 | } | |
741 | ||
af42b8d1 SS |
742 | int xen_irq_from_pirq(unsigned pirq) |
743 | { | |
69c358ce IC |
744 | int irq; |
745 | ||
746 | struct irq_info *info; | |
747 | ||
748 | spin_lock(&irq_mapping_update_lock); | |
749 | ||
750 | list_for_each_entry(info, &xen_irq_list_head, list) { | |
751 | if (info == NULL || info->type != IRQT_PIRQ) | |
752 | continue; | |
753 | irq = info->irq; | |
754 | if (info->u.pirq.pirq == pirq) | |
755 | goto out; | |
756 | } | |
757 | irq = -1; | |
758 | out: | |
759 | spin_lock(&irq_mapping_update_lock); | |
760 | ||
761 | return irq; | |
af42b8d1 SS |
762 | } |
763 | ||
b536b4b9 | 764 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
765 | { |
766 | int irq; | |
767 | ||
768 | spin_lock(&irq_mapping_update_lock); | |
769 | ||
770 | irq = evtchn_to_irq[evtchn]; | |
771 | ||
772 | if (irq == -1) { | |
c9df1ce5 | 773 | irq = xen_allocate_irq_dynamic(); |
e46cdb66 | 774 | |
e46cdb66 | 775 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
3588fe2e | 776 | handle_fasteoi_irq, "event"); |
e46cdb66 | 777 | |
9158c358 | 778 | xen_irq_info_evtchn_init(irq, evtchn); |
e46cdb66 JF |
779 | } |
780 | ||
e46cdb66 JF |
781 | spin_unlock(&irq_mapping_update_lock); |
782 | ||
783 | return irq; | |
784 | } | |
b536b4b9 | 785 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 786 | |
f87e4cac JF |
787 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
788 | { | |
789 | struct evtchn_bind_ipi bind_ipi; | |
790 | int evtchn, irq; | |
791 | ||
792 | spin_lock(&irq_mapping_update_lock); | |
793 | ||
794 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 795 | |
f87e4cac | 796 | if (irq == -1) { |
c9df1ce5 | 797 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
798 | if (irq < 0) |
799 | goto out; | |
800 | ||
aaca4964 JF |
801 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
802 | handle_percpu_irq, "ipi"); | |
f87e4cac JF |
803 | |
804 | bind_ipi.vcpu = cpu; | |
805 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
806 | &bind_ipi) != 0) | |
807 | BUG(); | |
808 | evtchn = bind_ipi.port; | |
809 | ||
3d4cfa37 | 810 | xen_irq_info_ipi_init(cpu, irq, evtchn, ipi); |
f87e4cac JF |
811 | |
812 | bind_evtchn_to_cpu(evtchn, cpu); | |
813 | } | |
814 | ||
f87e4cac JF |
815 | out: |
816 | spin_unlock(&irq_mapping_update_lock); | |
817 | return irq; | |
818 | } | |
819 | ||
820 | ||
4fe7d5a7 | 821 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
e46cdb66 JF |
822 | { |
823 | struct evtchn_bind_virq bind_virq; | |
824 | int evtchn, irq; | |
825 | ||
826 | spin_lock(&irq_mapping_update_lock); | |
827 | ||
828 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
829 | ||
830 | if (irq == -1) { | |
c9df1ce5 | 831 | irq = xen_allocate_irq_dynamic(); |
a52521f1 JF |
832 | |
833 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, | |
834 | handle_percpu_irq, "virq"); | |
835 | ||
e46cdb66 JF |
836 | bind_virq.virq = virq; |
837 | bind_virq.vcpu = cpu; | |
838 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
839 | &bind_virq) != 0) | |
840 | BUG(); | |
841 | evtchn = bind_virq.port; | |
842 | ||
3d4cfa37 | 843 | xen_irq_info_virq_init(cpu, irq, evtchn, virq); |
e46cdb66 JF |
844 | |
845 | bind_evtchn_to_cpu(evtchn, cpu); | |
846 | } | |
847 | ||
e46cdb66 JF |
848 | spin_unlock(&irq_mapping_update_lock); |
849 | ||
850 | return irq; | |
851 | } | |
852 | ||
853 | static void unbind_from_irq(unsigned int irq) | |
854 | { | |
855 | struct evtchn_close close; | |
856 | int evtchn = evtchn_from_irq(irq); | |
857 | ||
858 | spin_lock(&irq_mapping_update_lock); | |
859 | ||
d77bbd4d | 860 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
861 | close.port = evtchn; |
862 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
863 | BUG(); | |
864 | ||
865 | switch (type_from_irq(irq)) { | |
866 | case IRQT_VIRQ: | |
867 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 868 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 869 | break; |
d68d82af AN |
870 | case IRQT_IPI: |
871 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 872 | [ipi_from_irq(irq)] = -1; |
d68d82af | 873 | break; |
e46cdb66 JF |
874 | default: |
875 | break; | |
876 | } | |
877 | ||
878 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
879 | bind_evtchn_to_cpu(evtchn, 0); | |
880 | ||
881 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
882 | } |
883 | ||
ca62ce8c | 884 | BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND); |
e46cdb66 | 885 | |
9158c358 | 886 | xen_free_irq(irq); |
e46cdb66 JF |
887 | |
888 | spin_unlock(&irq_mapping_update_lock); | |
889 | } | |
890 | ||
891 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 892 | irq_handler_t handler, |
e46cdb66 JF |
893 | unsigned long irqflags, |
894 | const char *devname, void *dev_id) | |
895 | { | |
896 | unsigned int irq; | |
897 | int retval; | |
898 | ||
899 | irq = bind_evtchn_to_irq(evtchn); | |
900 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
901 | if (retval != 0) { | |
902 | unbind_from_irq(irq); | |
903 | return retval; | |
904 | } | |
905 | ||
906 | return irq; | |
907 | } | |
908 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
909 | ||
910 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 911 | irq_handler_t handler, |
e46cdb66 JF |
912 | unsigned long irqflags, const char *devname, void *dev_id) |
913 | { | |
914 | unsigned int irq; | |
915 | int retval; | |
916 | ||
917 | irq = bind_virq_to_irq(virq, cpu); | |
918 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
919 | if (retval != 0) { | |
920 | unbind_from_irq(irq); | |
921 | return retval; | |
922 | } | |
923 | ||
924 | return irq; | |
925 | } | |
926 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
927 | ||
f87e4cac JF |
928 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
929 | unsigned int cpu, | |
930 | irq_handler_t handler, | |
931 | unsigned long irqflags, | |
932 | const char *devname, | |
933 | void *dev_id) | |
934 | { | |
935 | int irq, retval; | |
936 | ||
937 | irq = bind_ipi_to_irq(ipi, cpu); | |
938 | if (irq < 0) | |
939 | return irq; | |
940 | ||
676dc3cf | 941 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME; |
f87e4cac JF |
942 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
943 | if (retval != 0) { | |
944 | unbind_from_irq(irq); | |
945 | return retval; | |
946 | } | |
947 | ||
948 | return irq; | |
949 | } | |
950 | ||
e46cdb66 JF |
951 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
952 | { | |
953 | free_irq(irq, dev_id); | |
954 | unbind_from_irq(irq); | |
955 | } | |
956 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
957 | ||
f87e4cac JF |
958 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
959 | { | |
960 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
961 | BUG_ON(irq < 0); | |
962 | notify_remote_via_irq(irq); | |
963 | } | |
964 | ||
ee523ca1 JF |
965 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
966 | { | |
967 | struct shared_info *sh = HYPERVISOR_shared_info; | |
968 | int cpu = smp_processor_id(); | |
cb60d114 | 969 | unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu); |
ee523ca1 JF |
970 | int i; |
971 | unsigned long flags; | |
972 | static DEFINE_SPINLOCK(debug_lock); | |
cb52e6d9 | 973 | struct vcpu_info *v; |
ee523ca1 JF |
974 | |
975 | spin_lock_irqsave(&debug_lock, flags); | |
976 | ||
cb52e6d9 | 977 | printk("\nvcpu %d\n ", cpu); |
ee523ca1 JF |
978 | |
979 | for_each_online_cpu(i) { | |
cb52e6d9 IC |
980 | int pending; |
981 | v = per_cpu(xen_vcpu, i); | |
982 | pending = (get_irq_regs() && i == cpu) | |
983 | ? xen_irqs_disabled(get_irq_regs()) | |
984 | : v->evtchn_upcall_mask; | |
985 | printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i, | |
986 | pending, v->evtchn_upcall_pending, | |
987 | (int)(sizeof(v->evtchn_pending_sel)*2), | |
988 | v->evtchn_pending_sel); | |
989 | } | |
990 | v = per_cpu(xen_vcpu, cpu); | |
991 | ||
992 | printk("\npending:\n "); | |
993 | for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
994 | printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2, | |
995 | sh->evtchn_pending[i], | |
996 | i % 8 == 0 ? "\n " : " "); | |
997 | printk("\nglobal mask:\n "); | |
998 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
999 | printk("%0*lx%s", | |
1000 | (int)(sizeof(sh->evtchn_mask[0])*2), | |
1001 | sh->evtchn_mask[i], | |
1002 | i % 8 == 0 ? "\n " : " "); | |
1003 | ||
1004 | printk("\nglobally unmasked:\n "); | |
1005 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1006 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1007 | sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
1008 | i % 8 == 0 ? "\n " : " "); | |
1009 | ||
1010 | printk("\nlocal cpu%d mask:\n ", cpu); | |
1011 | for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--) | |
1012 | printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2), | |
1013 | cpu_evtchn[i], | |
1014 | i % 8 == 0 ? "\n " : " "); | |
1015 | ||
1016 | printk("\nlocally unmasked:\n "); | |
1017 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) { | |
1018 | unsigned long pending = sh->evtchn_pending[i] | |
1019 | & ~sh->evtchn_mask[i] | |
1020 | & cpu_evtchn[i]; | |
1021 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1022 | pending, i % 8 == 0 ? "\n " : " "); | |
ee523ca1 | 1023 | } |
ee523ca1 JF |
1024 | |
1025 | printk("\npending list:\n"); | |
cb52e6d9 | 1026 | for (i = 0; i < NR_EVENT_CHANNELS; i++) { |
ee523ca1 | 1027 | if (sync_test_bit(i, sh->evtchn_pending)) { |
cb52e6d9 IC |
1028 | int word_idx = i / BITS_PER_LONG; |
1029 | printk(" %d: event %d -> irq %d%s%s%s\n", | |
ced40d0f | 1030 | cpu_from_evtchn(i), i, |
cb52e6d9 IC |
1031 | evtchn_to_irq[i], |
1032 | sync_test_bit(word_idx, &v->evtchn_pending_sel) | |
1033 | ? "" : " l2-clear", | |
1034 | !sync_test_bit(i, sh->evtchn_mask) | |
1035 | ? "" : " globally-masked", | |
1036 | sync_test_bit(i, cpu_evtchn) | |
1037 | ? "" : " locally-masked"); | |
ee523ca1 JF |
1038 | } |
1039 | } | |
1040 | ||
1041 | spin_unlock_irqrestore(&debug_lock, flags); | |
1042 | ||
1043 | return IRQ_HANDLED; | |
1044 | } | |
1045 | ||
245b2e70 TH |
1046 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
1047 | ||
e46cdb66 JF |
1048 | /* |
1049 | * Search the CPUs pending events bitmasks. For each one found, map | |
1050 | * the event number to an irq, and feed it into do_IRQ() for | |
1051 | * handling. | |
1052 | * | |
1053 | * Xen uses a two-level bitmap to speed searching. The first level is | |
1054 | * a bitset of words which contain pending event bits. The second | |
1055 | * level is a bitset of pending events themselves. | |
1056 | */ | |
38e20b07 | 1057 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 JF |
1058 | { |
1059 | int cpu = get_cpu(); | |
1060 | struct shared_info *s = HYPERVISOR_shared_info; | |
780f36d8 | 1061 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
229664be | 1062 | unsigned count; |
e46cdb66 | 1063 | |
229664be JF |
1064 | do { |
1065 | unsigned long pending_words; | |
e46cdb66 | 1066 | |
229664be | 1067 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1068 | |
b2e4ae69 | 1069 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1070 | goto out; |
e46cdb66 | 1071 | |
e849c3e9 IY |
1072 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
1073 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 1074 | wmb(); |
e849c3e9 | 1075 | #endif |
229664be JF |
1076 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
1077 | while (pending_words != 0) { | |
1078 | unsigned long pending_bits; | |
1079 | int word_idx = __ffs(pending_words); | |
1080 | pending_words &= ~(1UL << word_idx); | |
1081 | ||
1082 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
1083 | int bit_idx = __ffs(pending_bits); | |
1084 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
1085 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 1086 | struct irq_desc *desc; |
229664be | 1087 | |
3588fe2e JF |
1088 | mask_evtchn(port); |
1089 | clear_evtchn(port); | |
1090 | ||
ca4dbc66 EB |
1091 | if (irq != -1) { |
1092 | desc = irq_to_desc(irq); | |
1093 | if (desc) | |
1094 | generic_handle_irq_desc(irq, desc); | |
1095 | } | |
e46cdb66 JF |
1096 | } |
1097 | } | |
e46cdb66 | 1098 | |
229664be JF |
1099 | BUG_ON(!irqs_disabled()); |
1100 | ||
780f36d8 CL |
1101 | count = __this_cpu_read(xed_nesting_count); |
1102 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1103 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1104 | |
1105 | out: | |
38e20b07 SY |
1106 | |
1107 | put_cpu(); | |
1108 | } | |
1109 | ||
1110 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1111 | { | |
1112 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1113 | ||
1114 | exit_idle(); | |
1115 | irq_enter(); | |
1116 | ||
1117 | __xen_evtchn_do_upcall(); | |
1118 | ||
3445a8fd JF |
1119 | irq_exit(); |
1120 | set_irq_regs(old_regs); | |
38e20b07 | 1121 | } |
3445a8fd | 1122 | |
38e20b07 SY |
1123 | void xen_hvm_evtchn_do_upcall(void) |
1124 | { | |
1125 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1126 | } |
183d03cc | 1127 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1128 | |
eb1e305f JF |
1129 | /* Rebind a new event channel to an existing irq. */ |
1130 | void rebind_evtchn_irq(int evtchn, int irq) | |
1131 | { | |
d77bbd4d JF |
1132 | struct irq_info *info = info_for_irq(irq); |
1133 | ||
eb1e305f JF |
1134 | /* Make sure the irq is masked, since the new event channel |
1135 | will also be masked. */ | |
1136 | disable_irq(irq); | |
1137 | ||
1138 | spin_lock(&irq_mapping_update_lock); | |
1139 | ||
1140 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
1141 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
1142 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
1143 | so there should be a proper type */ |
1144 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f | 1145 | |
9158c358 | 1146 | xen_irq_info_evtchn_init(irq, evtchn); |
eb1e305f JF |
1147 | |
1148 | spin_unlock(&irq_mapping_update_lock); | |
1149 | ||
1150 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1151 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1152 | |
1153 | /* Unmask the event channel. */ | |
1154 | enable_irq(irq); | |
1155 | } | |
1156 | ||
e46cdb66 | 1157 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1158 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1159 | { |
1160 | struct evtchn_bind_vcpu bind_vcpu; | |
1161 | int evtchn = evtchn_from_irq(irq); | |
1162 | ||
be49472f IC |
1163 | if (!VALID_EVTCHN(evtchn)) |
1164 | return -1; | |
1165 | ||
1166 | /* | |
1167 | * Events delivered via platform PCI interrupts are always | |
1168 | * routed to vcpu 0 and hence cannot be rebound. | |
1169 | */ | |
1170 | if (xen_hvm_domain() && !xen_have_vector_callback) | |
d5dedd45 | 1171 | return -1; |
e46cdb66 JF |
1172 | |
1173 | /* Send future instances of this interrupt to other vcpu. */ | |
1174 | bind_vcpu.port = evtchn; | |
1175 | bind_vcpu.vcpu = tcpu; | |
1176 | ||
1177 | /* | |
1178 | * If this fails, it usually just indicates that we're dealing with a | |
1179 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1180 | * it, but don't do the xenlinux-level rebind in that case. | |
1181 | */ | |
1182 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1183 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1184 | |
d5dedd45 YL |
1185 | return 0; |
1186 | } | |
e46cdb66 | 1187 | |
c9e265e0 TG |
1188 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1189 | bool force) | |
e46cdb66 | 1190 | { |
0de26520 | 1191 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 | 1192 | |
c9e265e0 | 1193 | return rebind_irq_to_cpu(data->irq, tcpu); |
e46cdb66 JF |
1194 | } |
1195 | ||
642e0c88 IY |
1196 | int resend_irq_on_evtchn(unsigned int irq) |
1197 | { | |
1198 | int masked, evtchn = evtchn_from_irq(irq); | |
1199 | struct shared_info *s = HYPERVISOR_shared_info; | |
1200 | ||
1201 | if (!VALID_EVTCHN(evtchn)) | |
1202 | return 1; | |
1203 | ||
1204 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
1205 | sync_set_bit(evtchn, s->evtchn_pending); | |
1206 | if (!masked) | |
1207 | unmask_evtchn(evtchn); | |
1208 | ||
1209 | return 1; | |
1210 | } | |
1211 | ||
c9e265e0 | 1212 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1213 | { |
c9e265e0 | 1214 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1215 | |
1216 | if (VALID_EVTCHN(evtchn)) | |
1217 | unmask_evtchn(evtchn); | |
1218 | } | |
1219 | ||
c9e265e0 | 1220 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1221 | { |
c9e265e0 | 1222 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1223 | |
1224 | if (VALID_EVTCHN(evtchn)) | |
1225 | mask_evtchn(evtchn); | |
1226 | } | |
1227 | ||
c9e265e0 | 1228 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1229 | { |
c9e265e0 | 1230 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1231 | |
c9e265e0 | 1232 | move_masked_irq(data->irq); |
e46cdb66 JF |
1233 | |
1234 | if (VALID_EVTCHN(evtchn)) | |
3588fe2e | 1235 | unmask_evtchn(evtchn); |
e46cdb66 JF |
1236 | } |
1237 | ||
c9e265e0 | 1238 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1239 | { |
c9e265e0 | 1240 | int evtchn = evtchn_from_irq(data->irq); |
ee8fa1c6 | 1241 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1242 | int ret = 0; |
1243 | ||
1244 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1245 | int masked; |
1246 | ||
1247 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
1248 | sync_set_bit(evtchn, sh->evtchn_pending); | |
1249 | if (!masked) | |
1250 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1251 | ret = 1; |
1252 | } | |
1253 | ||
1254 | return ret; | |
1255 | } | |
1256 | ||
0a85226f | 1257 | static void restore_pirqs(void) |
9a069c33 SS |
1258 | { |
1259 | int pirq, rc, irq, gsi; | |
1260 | struct physdev_map_pirq map_irq; | |
69c358ce | 1261 | struct irq_info *info; |
9a069c33 | 1262 | |
69c358ce IC |
1263 | list_for_each_entry(info, &xen_irq_list_head, list) { |
1264 | if (info->type != IRQT_PIRQ) | |
9a069c33 SS |
1265 | continue; |
1266 | ||
69c358ce IC |
1267 | pirq = info->u.pirq.pirq; |
1268 | gsi = info->u.pirq.gsi; | |
1269 | irq = info->irq; | |
1270 | ||
9a069c33 SS |
1271 | /* save/restore of PT devices doesn't work, so at this point the |
1272 | * only devices present are GSI based emulated devices */ | |
9a069c33 SS |
1273 | if (!gsi) |
1274 | continue; | |
1275 | ||
1276 | map_irq.domid = DOMID_SELF; | |
1277 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1278 | map_irq.index = gsi; | |
1279 | map_irq.pirq = pirq; | |
1280 | ||
1281 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1282 | if (rc) { | |
1283 | printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", | |
1284 | gsi, irq, pirq, rc); | |
9158c358 | 1285 | xen_free_irq(irq); |
9a069c33 SS |
1286 | continue; |
1287 | } | |
1288 | ||
1289 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1290 | ||
c9e265e0 | 1291 | __startup_pirq(irq); |
9a069c33 SS |
1292 | } |
1293 | } | |
1294 | ||
0e91398f JF |
1295 | static void restore_cpu_virqs(unsigned int cpu) |
1296 | { | |
1297 | struct evtchn_bind_virq bind_virq; | |
1298 | int virq, irq, evtchn; | |
1299 | ||
1300 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1301 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1302 | continue; | |
1303 | ||
ced40d0f | 1304 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1305 | |
1306 | /* Get a new binding from Xen. */ | |
1307 | bind_virq.virq = virq; | |
1308 | bind_virq.vcpu = cpu; | |
1309 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1310 | &bind_virq) != 0) | |
1311 | BUG(); | |
1312 | evtchn = bind_virq.port; | |
1313 | ||
1314 | /* Record the new mapping. */ | |
3d4cfa37 | 1315 | xen_irq_info_virq_init(cpu, irq, evtchn, virq); |
0e91398f | 1316 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1317 | } |
1318 | } | |
1319 | ||
1320 | static void restore_cpu_ipis(unsigned int cpu) | |
1321 | { | |
1322 | struct evtchn_bind_ipi bind_ipi; | |
1323 | int ipi, irq, evtchn; | |
1324 | ||
1325 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1326 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1327 | continue; | |
1328 | ||
ced40d0f | 1329 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1330 | |
1331 | /* Get a new binding from Xen. */ | |
1332 | bind_ipi.vcpu = cpu; | |
1333 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1334 | &bind_ipi) != 0) | |
1335 | BUG(); | |
1336 | evtchn = bind_ipi.port; | |
1337 | ||
1338 | /* Record the new mapping. */ | |
3d4cfa37 | 1339 | xen_irq_info_ipi_init(cpu, irq, evtchn, ipi); |
0e91398f | 1340 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1341 | } |
1342 | } | |
1343 | ||
2d9e1e2f JF |
1344 | /* Clear an irq's pending state, in preparation for polling on it */ |
1345 | void xen_clear_irq_pending(int irq) | |
1346 | { | |
1347 | int evtchn = evtchn_from_irq(irq); | |
1348 | ||
1349 | if (VALID_EVTCHN(evtchn)) | |
1350 | clear_evtchn(evtchn); | |
1351 | } | |
d9a8814f | 1352 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1353 | void xen_set_irq_pending(int irq) |
1354 | { | |
1355 | int evtchn = evtchn_from_irq(irq); | |
1356 | ||
1357 | if (VALID_EVTCHN(evtchn)) | |
1358 | set_evtchn(evtchn); | |
1359 | } | |
1360 | ||
1361 | bool xen_test_irq_pending(int irq) | |
1362 | { | |
1363 | int evtchn = evtchn_from_irq(irq); | |
1364 | bool ret = false; | |
1365 | ||
1366 | if (VALID_EVTCHN(evtchn)) | |
1367 | ret = test_evtchn(evtchn); | |
1368 | ||
1369 | return ret; | |
1370 | } | |
1371 | ||
d9a8814f KRW |
1372 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1373 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1374 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1375 | { |
1376 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1377 | ||
1378 | if (VALID_EVTCHN(evtchn)) { | |
1379 | struct sched_poll poll; | |
1380 | ||
1381 | poll.nr_ports = 1; | |
d9a8814f | 1382 | poll.timeout = timeout; |
ff3c5362 | 1383 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1384 | |
1385 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1386 | BUG(); | |
1387 | } | |
1388 | } | |
d9a8814f KRW |
1389 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1390 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1391 | * irq will be disabled so it won't deliver an interrupt. */ | |
1392 | void xen_poll_irq(int irq) | |
1393 | { | |
1394 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1395 | } | |
2d9e1e2f | 1396 | |
0e91398f JF |
1397 | void xen_irq_resume(void) |
1398 | { | |
6cb6537d IC |
1399 | unsigned int cpu, evtchn; |
1400 | struct irq_info *info; | |
0e91398f JF |
1401 | |
1402 | init_evtchn_cpu_bindings(); | |
1403 | ||
1404 | /* New event-channel space is not 'live' yet. */ | |
1405 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1406 | mask_evtchn(evtchn); | |
1407 | ||
1408 | /* No IRQ <-> event-channel mappings. */ | |
6cb6537d IC |
1409 | list_for_each_entry(info, &xen_irq_list_head, list) |
1410 | info->evtchn = 0; /* zap event-channel binding */ | |
0e91398f JF |
1411 | |
1412 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1413 | evtchn_to_irq[evtchn] = -1; | |
1414 | ||
1415 | for_each_possible_cpu(cpu) { | |
1416 | restore_cpu_virqs(cpu); | |
1417 | restore_cpu_ipis(cpu); | |
1418 | } | |
6903591f | 1419 | |
0a85226f | 1420 | restore_pirqs(); |
0e91398f JF |
1421 | } |
1422 | ||
e46cdb66 | 1423 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1424 | .name = "xen-dyn", |
54a353a0 | 1425 | |
c9e265e0 TG |
1426 | .irq_disable = disable_dynirq, |
1427 | .irq_mask = disable_dynirq, | |
1428 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1429 | |
c9e265e0 TG |
1430 | .irq_eoi = ack_dynirq, |
1431 | .irq_set_affinity = set_affinity_irq, | |
1432 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1433 | }; |
1434 | ||
d46a78b0 | 1435 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1436 | .name = "xen-pirq", |
d46a78b0 | 1437 | |
c9e265e0 TG |
1438 | .irq_startup = startup_pirq, |
1439 | .irq_shutdown = shutdown_pirq, | |
d46a78b0 | 1440 | |
c9e265e0 TG |
1441 | .irq_enable = enable_pirq, |
1442 | .irq_unmask = enable_pirq, | |
d46a78b0 | 1443 | |
c9e265e0 TG |
1444 | .irq_disable = disable_pirq, |
1445 | .irq_mask = disable_pirq, | |
d46a78b0 | 1446 | |
c9e265e0 | 1447 | .irq_ack = ack_pirq, |
d46a78b0 | 1448 | |
c9e265e0 | 1449 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1450 | |
c9e265e0 | 1451 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1452 | }; |
1453 | ||
aaca4964 | 1454 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1455 | .name = "xen-percpu", |
aaca4964 | 1456 | |
c9e265e0 TG |
1457 | .irq_disable = disable_dynirq, |
1458 | .irq_mask = disable_dynirq, | |
1459 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1460 | |
c9e265e0 | 1461 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1462 | }; |
1463 | ||
38e20b07 SY |
1464 | int xen_set_callback_via(uint64_t via) |
1465 | { | |
1466 | struct xen_hvm_param a; | |
1467 | a.domid = DOMID_SELF; | |
1468 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1469 | a.value = via; | |
1470 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1471 | } | |
1472 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1473 | ||
ca65f9fc | 1474 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1475 | /* Vector callbacks are better than PCI interrupts to receive event |
1476 | * channel notifications because we can receive vector callbacks on any | |
1477 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1478 | void xen_callback_vector(void) | |
1479 | { | |
1480 | int rc; | |
1481 | uint64_t callback_via; | |
1482 | if (xen_have_vector_callback) { | |
1483 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1484 | rc = xen_set_callback_via(callback_via); | |
1485 | if (rc) { | |
1486 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1487 | " failed.\n"); | |
1488 | xen_have_vector_callback = 0; | |
1489 | return; | |
1490 | } | |
1491 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1492 | "enabled\n"); | |
1493 | /* in the restore case the vector has already been allocated */ | |
1494 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1495 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1496 | } | |
1497 | } | |
ca65f9fc SS |
1498 | #else |
1499 | void xen_callback_vector(void) {} | |
1500 | #endif | |
38e20b07 | 1501 | |
e46cdb66 JF |
1502 | void __init xen_init_IRQ(void) |
1503 | { | |
e5fc7345 | 1504 | int i; |
c7a3589e | 1505 | |
b21ddbf5 JF |
1506 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), |
1507 | GFP_KERNEL); | |
1508 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1509 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1510 | |
1511 | init_evtchn_cpu_bindings(); | |
1512 | ||
1513 | /* No event channels are 'live' right now. */ | |
1514 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1515 | mask_evtchn(i); | |
1516 | ||
38e20b07 SY |
1517 | if (xen_hvm_domain()) { |
1518 | xen_callback_vector(); | |
1519 | native_init_IRQ(); | |
3942b740 SS |
1520 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1521 | * __acpi_register_gsi can point at the right function */ | |
1522 | pci_xen_hvm_init(); | |
38e20b07 SY |
1523 | } else { |
1524 | irq_ctx_init(smp_processor_id()); | |
38aa66fc JF |
1525 | if (xen_initial_domain()) |
1526 | xen_setup_pirqs(); | |
38e20b07 | 1527 | } |
e46cdb66 | 1528 | } |