Merge tag 'metag-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan...
[linux-2.6-block.git] / drivers / xen / events.c
CommitLineData
e46cdb66
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1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
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9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
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20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
283c0972
JP
24#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
25
e46cdb66
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26#include <linux/linkage.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/module.h>
30#include <linux/string.h>
28e08861 31#include <linux/bootmem.h>
5a0e3ad6 32#include <linux/slab.h>
b21ddbf5 33#include <linux/irqnr.h>
f731e3ef 34#include <linux/pci.h>
e46cdb66 35
0ec53ecf 36#ifdef CONFIG_X86
38e20b07 37#include <asm/desc.h>
e46cdb66
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38#include <asm/ptrace.h>
39#include <asm/irq.h>
792dc4f6 40#include <asm/idle.h>
0794bfc7 41#include <asm/io_apic.h>
9846ff10 42#include <asm/xen/page.h>
42a1de56 43#include <asm/xen/pci.h>
0ec53ecf
SS
44#endif
45#include <asm/sync_bitops.h>
e46cdb66 46#include <asm/xen/hypercall.h>
8d1b8753 47#include <asm/xen/hypervisor.h>
e46cdb66 48
38e20b07
SY
49#include <xen/xen.h>
50#include <xen/hvm.h>
e04d0d07 51#include <xen/xen-ops.h>
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52#include <xen/events.h>
53#include <xen/interface/xen.h>
54#include <xen/interface/event_channel.h>
38e20b07
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55#include <xen/interface/hvm/hvm_op.h>
56#include <xen/interface/hvm/params.h>
0ec53ecf
SS
57#include <xen/interface/physdev.h>
58#include <xen/interface/sched.h>
59#include <asm/hw_irq.h>
e46cdb66 60
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61/*
62 * This lock protects updates to the following mapping and reference-count
63 * arrays. The lock does not need to be acquired to read the mapping tables.
64 */
77365948 65static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 66
6cb6537d
IC
67static LIST_HEAD(xen_irq_list_head);
68
e46cdb66 69/* IRQ <-> VIRQ mapping. */
204fba4a 70static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 71
f87e4cac 72/* IRQ <-> IPI mapping */
204fba4a 73static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 74
ced40d0f
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75/* Interrupt types. */
76enum xen_irq_type {
d77bbd4d 77 IRQT_UNBOUND = 0,
f87e4cac
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78 IRQT_PIRQ,
79 IRQT_VIRQ,
80 IRQT_IPI,
81 IRQT_EVTCHN
82};
e46cdb66 83
ced40d0f
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84/*
85 * Packed IRQ information:
86 * type - enum xen_irq_type
87 * event channel - irq->event channel mapping
88 * cpu - cpu this event channel is bound to
89 * index - type-specific information:
dec02dea 90 * PIRQ - physical IRQ, GSI, flags, and owner domain
ced40d0f
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91 * VIRQ - virq number
92 * IPI - IPI vector
93 * EVTCHN -
94 */
088c05a8 95struct irq_info {
6cb6537d 96 struct list_head list;
420eb554 97 int refcnt;
ced40d0f 98 enum xen_irq_type type; /* type */
6cb6537d 99 unsigned irq;
ced40d0f
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100 unsigned short evtchn; /* event channel */
101 unsigned short cpu; /* cpu bound */
102
103 union {
104 unsigned short virq;
105 enum ipi_vector ipi;
106 struct {
7a043f11 107 unsigned short pirq;
ced40d0f 108 unsigned short gsi;
d46a78b0 109 unsigned char flags;
beafbdc1 110 uint16_t domid;
ced40d0f
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111 } pirq;
112 } u;
113};
d46a78b0 114#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 115#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 116
b21ddbf5 117static int *evtchn_to_irq;
bf86ad80 118#ifdef CONFIG_X86
9846ff10 119static unsigned long *pirq_eoi_map;
bf86ad80 120#endif
9846ff10 121static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 122
c81611c4
IC
123/*
124 * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
125 * careful to only use bitops which allow for this (e.g
126 * test_bit/find_first_bit and friends but not __ffs) and to pass
127 * BITS_PER_EVTCHN_WORD as the bitmask length.
128 */
129#define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
130/*
131 * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
132 * array. Primarily to avoid long lines (hence the terse name).
133 */
134#define BM(x) (unsigned long *)(x)
135/* Find the first set bit in a evtchn mask */
136#define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
137
138static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
cb60d114 139 cpu_evtchn_mask);
e46cdb66 140
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141/* Xen will never allocate port zero for any purpose. */
142#define VALID_EVTCHN(chn) ((chn) != 0)
143
e46cdb66 144static struct irq_chip xen_dynamic_chip;
aaca4964 145static struct irq_chip xen_percpu_chip;
d46a78b0 146static struct irq_chip xen_pirq_chip;
7e186bdd
SS
147static void enable_dynirq(struct irq_data *data);
148static void disable_dynirq(struct irq_data *data);
e46cdb66 149
9158c358
IC
150/* Get info for IRQ */
151static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 152{
c442b806 153 return irq_get_handler_data(irq);
ced40d0f
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154}
155
9158c358
IC
156/* Constructors for packed IRQ information. */
157static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 158 unsigned irq,
9158c358
IC
159 enum xen_irq_type type,
160 unsigned short evtchn,
161 unsigned short cpu)
ced40d0f 162{
9158c358
IC
163
164 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
165
166 info->type = type;
6cb6537d 167 info->irq = irq;
9158c358
IC
168 info->evtchn = evtchn;
169 info->cpu = cpu;
3d4cfa37
IC
170
171 evtchn_to_irq[evtchn] = irq;
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172
173 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
ced40d0f
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174}
175
9158c358
IC
176static void xen_irq_info_evtchn_init(unsigned irq,
177 unsigned short evtchn)
ced40d0f 178{
9158c358
IC
179 struct irq_info *info = info_for_irq(irq);
180
3d4cfa37 181 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
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182}
183
3d4cfa37
IC
184static void xen_irq_info_ipi_init(unsigned cpu,
185 unsigned irq,
9158c358
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186 unsigned short evtchn,
187 enum ipi_vector ipi)
e46cdb66 188{
9158c358
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189 struct irq_info *info = info_for_irq(irq);
190
3d4cfa37 191 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
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192
193 info->u.ipi = ipi;
3d4cfa37
IC
194
195 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
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196}
197
3d4cfa37
IC
198static void xen_irq_info_virq_init(unsigned cpu,
199 unsigned irq,
9158c358
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200 unsigned short evtchn,
201 unsigned short virq)
ced40d0f 202{
9158c358
IC
203 struct irq_info *info = info_for_irq(irq);
204
3d4cfa37 205 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
206
207 info->u.virq = virq;
3d4cfa37
IC
208
209 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
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210}
211
9158c358
IC
212static void xen_irq_info_pirq_init(unsigned irq,
213 unsigned short evtchn,
214 unsigned short pirq,
215 unsigned short gsi,
beafbdc1 216 uint16_t domid,
9158c358 217 unsigned char flags)
ced40d0f 218{
9158c358
IC
219 struct irq_info *info = info_for_irq(irq);
220
3d4cfa37 221 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
222
223 info->u.pirq.pirq = pirq;
224 info->u.pirq.gsi = gsi;
beafbdc1 225 info->u.pirq.domid = domid;
9158c358 226 info->u.pirq.flags = flags;
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227}
228
229/*
230 * Accessors for packed IRQ information.
231 */
ced40d0f 232static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 233{
110e7c7e
JJ
234 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
235 return 0;
236
ced40d0f 237 return info_for_irq(irq)->evtchn;
e46cdb66
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238}
239
d4c04536
IC
240unsigned irq_from_evtchn(unsigned int evtchn)
241{
242 return evtchn_to_irq[evtchn];
243}
244EXPORT_SYMBOL_GPL(irq_from_evtchn);
245
ced40d0f 246static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 247{
ced40d0f
JF
248 struct irq_info *info = info_for_irq(irq);
249
250 BUG_ON(info == NULL);
251 BUG_ON(info->type != IRQT_IPI);
252
253 return info->u.ipi;
254}
255
256static unsigned virq_from_irq(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
259
260 BUG_ON(info == NULL);
261 BUG_ON(info->type != IRQT_VIRQ);
262
263 return info->u.virq;
264}
265
7a043f11
SS
266static unsigned pirq_from_irq(unsigned irq)
267{
268 struct irq_info *info = info_for_irq(irq);
269
270 BUG_ON(info == NULL);
271 BUG_ON(info->type != IRQT_PIRQ);
272
273 return info->u.pirq.pirq;
274}
275
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276static enum xen_irq_type type_from_irq(unsigned irq)
277{
278 return info_for_irq(irq)->type;
279}
280
281static unsigned cpu_from_irq(unsigned irq)
282{
283 return info_for_irq(irq)->cpu;
284}
285
286static unsigned int cpu_from_evtchn(unsigned int evtchn)
287{
288 int irq = evtchn_to_irq[evtchn];
289 unsigned ret = 0;
290
291 if (irq != -1)
292 ret = cpu_from_irq(irq);
293
294 return ret;
e46cdb66
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295}
296
bf86ad80 297#ifdef CONFIG_X86
9846ff10 298static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 299{
521394e4 300 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 301}
bf86ad80 302#endif
d46a78b0 303
9846ff10
SS
304static bool pirq_needs_eoi_flag(unsigned irq)
305{
306 struct irq_info *info = info_for_irq(irq);
d46a78b0
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307 BUG_ON(info->type != IRQT_PIRQ);
308
309 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
310}
311
c81611c4
IC
312static inline xen_ulong_t active_evtchns(unsigned int cpu,
313 struct shared_info *sh,
314 unsigned int idx)
e46cdb66 315{
088c05a8 316 return sh->evtchn_pending[idx] &
cb60d114 317 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 318 ~sh->evtchn_mask[idx];
e46cdb66
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319}
320
321static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
322{
323 int irq = evtchn_to_irq[chn];
324
325 BUG_ON(irq == -1);
326#ifdef CONFIG_SMP
c9e265e0 327 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
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328#endif
329
c81611c4
IC
330 clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
331 set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
e46cdb66 332
ca62ce8c 333 info_for_irq(irq)->cpu = cpu;
e46cdb66
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334}
335
336static void init_evtchn_cpu_bindings(void)
337{
1c6969ec 338 int i;
e46cdb66 339#ifdef CONFIG_SMP
6cb6537d 340 struct irq_info *info;
10e58084 341
e46cdb66 342 /* By default all event channels notify CPU#0. */
6cb6537d
IC
343 list_for_each_entry(info, &xen_irq_list_head, list) {
344 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 345 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 346 }
e46cdb66
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347#endif
348
1c6969ec 349 for_each_possible_cpu(i)
cb60d114
IC
350 memset(per_cpu(cpu_evtchn_mask, i),
351 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
352}
353
e46cdb66
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354static inline void clear_evtchn(int port)
355{
356 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 357 sync_clear_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
358}
359
360static inline void set_evtchn(int port)
361{
362 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 363 sync_set_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
364}
365
168d2f46
JF
366static inline int test_evtchn(int port)
367{
368 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 369 return sync_test_bit(port, BM(&s->evtchn_pending[0]));
168d2f46
JF
370}
371
e46cdb66
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372
373/**
374 * notify_remote_via_irq - send event to remote end of event channel via irq
375 * @irq: irq of event channel to send event to
376 *
377 * Unlike notify_remote_via_evtchn(), this is safe to use across
378 * save/restore. Notifications on a broken connection are silently
379 * dropped.
380 */
381void notify_remote_via_irq(int irq)
382{
383 int evtchn = evtchn_from_irq(irq);
384
385 if (VALID_EVTCHN(evtchn))
386 notify_remote_via_evtchn(evtchn);
387}
388EXPORT_SYMBOL_GPL(notify_remote_via_irq);
389
390static void mask_evtchn(int port)
391{
392 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 393 sync_set_bit(port, BM(&s->evtchn_mask[0]));
e46cdb66
JF
394}
395
396static void unmask_evtchn(int port)
397{
398 struct shared_info *s = HYPERVISOR_shared_info;
399 unsigned int cpu = get_cpu();
b5e57923 400 int do_hypercall = 0, evtchn_pending = 0;
e46cdb66
JF
401
402 BUG_ON(!irqs_disabled());
403
b5e57923
SS
404 if (unlikely((cpu != cpu_from_evtchn(port))))
405 do_hypercall = 1;
c26377e6
DV
406 else {
407 /*
408 * Need to clear the mask before checking pending to
409 * avoid a race with an event becoming pending.
410 *
411 * EVTCHNOP_unmask will only trigger an upcall if the
412 * mask bit was set, so if a hypercall is needed
413 * remask the event.
414 */
415 sync_clear_bit(port, BM(&s->evtchn_mask[0]));
c81611c4 416 evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
b5e57923 417
c26377e6
DV
418 if (unlikely(evtchn_pending && xen_hvm_domain())) {
419 sync_set_bit(port, BM(&s->evtchn_mask[0]));
420 do_hypercall = 1;
421 }
422 }
b5e57923
SS
423
424 /* Slow path (hypercall) if this is a non-local port or if this is
425 * an hvm domain and an event is pending (hvm domains don't have
426 * their own implementation of irq_enable). */
427 if (do_hypercall) {
e46cdb66
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428 struct evtchn_unmask unmask = { .port = port };
429 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
430 } else {
780f36d8 431 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66 432
e46cdb66
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433 /*
434 * The following is basically the equivalent of
435 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
436 * the interrupt edge' if the channel is masked.
437 */
b5e57923 438 if (evtchn_pending &&
c81611c4
IC
439 !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
440 BM(&vcpu_info->evtchn_pending_sel)))
e46cdb66
JF
441 vcpu_info->evtchn_upcall_pending = 1;
442 }
443
444 put_cpu();
445}
446
6cb6537d
IC
447static void xen_irq_init(unsigned irq)
448{
449 struct irq_info *info;
b5328cd1 450#ifdef CONFIG_SMP
6cb6537d
IC
451 struct irq_desc *desc = irq_to_desc(irq);
452
453 /* By default all event channels notify CPU#0. */
454 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 455#endif
6cb6537d 456
ca62ce8c
IC
457 info = kzalloc(sizeof(*info), GFP_KERNEL);
458 if (info == NULL)
459 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
460
461 info->type = IRQT_UNBOUND;
420eb554 462 info->refcnt = -1;
6cb6537d 463
c442b806 464 irq_set_handler_data(irq, info);
ca62ce8c 465
6cb6537d
IC
466 list_add_tail(&info->list, &xen_irq_list_head);
467}
468
7bee9768 469static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 470{
89911501
IC
471 int first = 0;
472 int irq;
0794bfc7
KRW
473
474#ifdef CONFIG_X86_IO_APIC
89911501
IC
475 /*
476 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 477 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
478 * e.g. those corresponding to event channels or MSIs
479 * etc. from the range above those "real" GSIs to avoid
480 * collisions.
481 */
482 if (xen_initial_domain() || xen_hvm_domain())
483 first = get_nr_irqs_gsi();
0794bfc7
KRW
484#endif
485
89911501 486 irq = irq_alloc_desc_from(first, -1);
3a69e916 487
e6599225
KRW
488 if (irq >= 0)
489 xen_irq_init(irq);
ced40d0f 490
e46cdb66 491 return irq;
d46a78b0
JF
492}
493
7bee9768 494static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
495{
496 int irq;
497
89911501
IC
498 /*
499 * A PV guest has no concept of a GSI (since it has no ACPI
500 * nor access to/knowledge of the physical APICs). Therefore
501 * all IRQs are dynamically allocated from the entire IRQ
502 * space.
503 */
504 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
505 return xen_allocate_irq_dynamic();
506
507 /* Legacy IRQ descriptors are already allocated by the arch. */
508 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
509 irq = gsi;
510 else
511 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 512
6cb6537d 513 xen_irq_init(irq);
c9df1ce5
IC
514
515 return irq;
516}
517
518static void xen_free_irq(unsigned irq)
519{
c442b806 520 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 521
94032c50
KRW
522 if (WARN_ON(!info))
523 return;
524
6cb6537d 525 list_del(&info->list);
9158c358 526
c442b806 527 irq_set_handler_data(irq, NULL);
ca62ce8c 528
420eb554
DDG
529 WARN_ON(info->refcnt > 0);
530
ca62ce8c
IC
531 kfree(info);
532
72146104
IC
533 /* Legacy IRQ descriptors are managed by the arch. */
534 if (irq < NR_IRQS_LEGACY)
535 return;
536
c9df1ce5
IC
537 irq_free_desc(irq);
538}
539
d46a78b0
JF
540static void pirq_query_unmask(int irq)
541{
542 struct physdev_irq_status_query irq_status;
543 struct irq_info *info = info_for_irq(irq);
544
545 BUG_ON(info->type != IRQT_PIRQ);
546
7a043f11 547 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
548 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
549 irq_status.flags = 0;
550
551 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
552 if (irq_status.flags & XENIRQSTAT_needs_eoi)
553 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
554}
555
556static bool probing_irq(int irq)
557{
558 struct irq_desc *desc = irq_to_desc(irq);
559
560 return desc && desc->action == NULL;
561}
562
7e186bdd
SS
563static void eoi_pirq(struct irq_data *data)
564{
565 int evtchn = evtchn_from_irq(data->irq);
566 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
567 int rc = 0;
568
569 irq_move_irq(data);
570
571 if (VALID_EVTCHN(evtchn))
572 clear_evtchn(evtchn);
573
574 if (pirq_needs_eoi(data->irq)) {
575 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
576 WARN_ON(rc);
577 }
578}
579
580static void mask_ack_pirq(struct irq_data *data)
581{
582 disable_dynirq(data);
583 eoi_pirq(data);
584}
585
c9e265e0 586static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
587{
588 struct evtchn_bind_pirq bind_pirq;
589 struct irq_info *info = info_for_irq(irq);
590 int evtchn = evtchn_from_irq(irq);
15ebbb82 591 int rc;
d46a78b0
JF
592
593 BUG_ON(info->type != IRQT_PIRQ);
594
595 if (VALID_EVTCHN(evtchn))
596 goto out;
597
7a043f11 598 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 599 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
600 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
601 BIND_PIRQ__WILL_SHARE : 0;
602 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
603 if (rc != 0) {
d46a78b0 604 if (!probing_irq(irq))
283c0972 605 pr_info("Failed to obtain physical IRQ %d\n", irq);
d46a78b0
JF
606 return 0;
607 }
608 evtchn = bind_pirq.port;
609
610 pirq_query_unmask(irq);
611
612 evtchn_to_irq[evtchn] = irq;
613 bind_evtchn_to_cpu(evtchn, 0);
614 info->evtchn = evtchn;
615
616out:
617 unmask_evtchn(evtchn);
7e186bdd 618 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
619
620 return 0;
621}
622
c9e265e0
TG
623static unsigned int startup_pirq(struct irq_data *data)
624{
625 return __startup_pirq(data->irq);
626}
627
628static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
629{
630 struct evtchn_close close;
c9e265e0 631 unsigned int irq = data->irq;
d46a78b0
JF
632 struct irq_info *info = info_for_irq(irq);
633 int evtchn = evtchn_from_irq(irq);
634
635 BUG_ON(info->type != IRQT_PIRQ);
636
637 if (!VALID_EVTCHN(evtchn))
638 return;
639
640 mask_evtchn(evtchn);
641
642 close.port = evtchn;
643 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
644 BUG();
645
646 bind_evtchn_to_cpu(evtchn, 0);
647 evtchn_to_irq[evtchn] = -1;
648 info->evtchn = 0;
649}
650
c9e265e0 651static void enable_pirq(struct irq_data *data)
d46a78b0 652{
c9e265e0 653 startup_pirq(data);
d46a78b0
JF
654}
655
c9e265e0 656static void disable_pirq(struct irq_data *data)
d46a78b0 657{
7e186bdd 658 disable_dynirq(data);
d46a78b0
JF
659}
660
68c2c39a 661int xen_irq_from_gsi(unsigned gsi)
d46a78b0 662{
6cb6537d 663 struct irq_info *info;
d46a78b0 664
6cb6537d
IC
665 list_for_each_entry(info, &xen_irq_list_head, list) {
666 if (info->type != IRQT_PIRQ)
d46a78b0
JF
667 continue;
668
6cb6537d
IC
669 if (info->u.pirq.gsi == gsi)
670 return info->irq;
d46a78b0
JF
671 }
672
673 return -1;
674}
68c2c39a 675EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 676
653378ac
IC
677/*
678 * Do not make any assumptions regarding the relationship between the
679 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
680 *
681 * Note: We don't assign an event channel until the irq actually started
682 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
683 *
684 * Shareable implies level triggered, not shareable implies edge
685 * triggered here.
d46a78b0 686 */
f4d0635b
IC
687int xen_bind_pirq_gsi_to_irq(unsigned gsi,
688 unsigned pirq, int shareable, char *name)
d46a78b0 689{
a0e18116 690 int irq = -1;
d46a78b0
JF
691 struct physdev_irq irq_op;
692
77365948 693 mutex_lock(&irq_mapping_update_lock);
d46a78b0 694
68c2c39a 695 irq = xen_irq_from_gsi(gsi);
d46a78b0 696 if (irq != -1) {
283c0972
JP
697 pr_info("%s: returning irq %d for gsi %u\n",
698 __func__, irq, gsi);
420eb554 699 goto out;
d46a78b0
JF
700 }
701
c9df1ce5 702 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
703 if (irq < 0)
704 goto out;
d46a78b0 705
d46a78b0 706 irq_op.irq = irq;
b5401a96
AN
707 irq_op.vector = 0;
708
709 /* Only the privileged domain can do this. For non-priv, the pcifront
710 * driver provides a PCI bus that does the call to do exactly
711 * this in the priv domain. */
712 if (xen_initial_domain() &&
713 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 714 xen_free_irq(irq);
d46a78b0
JF
715 irq = -ENOSPC;
716 goto out;
717 }
718
dec02dea 719 xen_irq_info_pirq_init(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 720 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 721
7e186bdd
SS
722 pirq_query_unmask(irq);
723 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
724 * type of interrupt: if the interrupt is an edge triggered
725 * interrupt we use handle_edge_irq.
7e186bdd 726 *
e5ac0bda
SS
727 * On the other hand if the interrupt is level triggered we use
728 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 729 * interrupts.
e5ac0bda 730 *
7e186bdd
SS
731 * Depending on the Xen version, pirq_needs_eoi might return true
732 * not only for level triggered interrupts but for edge triggered
733 * interrupts too. In any case Xen always honors the eoi mechanism,
734 * not injecting any more pirqs of the same kind if the first one
735 * hasn't received an eoi yet. Therefore using the fasteoi handler
736 * is the right choice either way.
737 */
e5ac0bda 738 if (shareable)
7e186bdd
SS
739 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
740 handle_fasteoi_irq, name);
741 else
742 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
743 handle_edge_irq, name);
744
d46a78b0 745out:
77365948 746 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
747
748 return irq;
749}
750
f731e3ef 751#ifdef CONFIG_PCI_MSI
bf480d95 752int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 753{
5cad61a6 754 int rc;
cbf6aa89 755 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 756
bf480d95 757 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 758 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 759
5cad61a6
IC
760 WARN_ONCE(rc == -ENOSYS,
761 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
762
763 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
764}
765
bf480d95 766int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
dec02dea 767 int pirq, const char *name, domid_t domid)
809f9267 768{
bf480d95 769 int irq, ret;
4b41df7f 770
77365948 771 mutex_lock(&irq_mapping_update_lock);
809f9267 772
4b41df7f 773 irq = xen_allocate_irq_dynamic();
e6599225 774 if (irq < 0)
bb5d079a 775 goto out;
809f9267 776
7e186bdd
SS
777 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
778 name);
809f9267 779
dec02dea 780 xen_irq_info_pirq_init(irq, 0, pirq, 0, domid, 0);
5f6fb454 781 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
782 if (ret < 0)
783 goto error_irq;
809f9267 784out:
77365948 785 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 786 return irq;
bf480d95 787error_irq:
77365948 788 mutex_unlock(&irq_mapping_update_lock);
bf480d95 789 xen_free_irq(irq);
e6599225 790 return ret;
809f9267 791}
f731e3ef
QH
792#endif
793
b5401a96
AN
794int xen_destroy_irq(int irq)
795{
796 struct irq_desc *desc;
38aa66fc
JF
797 struct physdev_unmap_pirq unmap_irq;
798 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
799 int rc = -ENOENT;
800
77365948 801 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
802
803 desc = irq_to_desc(irq);
804 if (!desc)
805 goto out;
806
38aa66fc 807 if (xen_initial_domain()) {
12334715 808 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 809 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 810 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
811 /* If another domain quits without making the pci_disable_msix
812 * call, the Xen hypervisor takes care of freeing the PIRQs
813 * (free_domain_pirqs).
814 */
815 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
283c0972 816 pr_info("domain %d does not have %d anymore\n",
1eff1ad0
KRW
817 info->u.pirq.domid, info->u.pirq.pirq);
818 else if (rc) {
283c0972 819 pr_warn("unmap irq failed %d\n", rc);
38aa66fc
JF
820 goto out;
821 }
822 }
b5401a96 823
c9df1ce5 824 xen_free_irq(irq);
b5401a96
AN
825
826out:
77365948 827 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
828 return rc;
829}
830
af42b8d1 831int xen_irq_from_pirq(unsigned pirq)
d46a78b0 832{
69c358ce 833 int irq;
d46a78b0 834
69c358ce 835 struct irq_info *info;
e46cdb66 836
77365948 837 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
838
839 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 840 if (info->type != IRQT_PIRQ)
69c358ce
IC
841 continue;
842 irq = info->irq;
843 if (info->u.pirq.pirq == pirq)
844 goto out;
845 }
846 irq = -1;
847out:
77365948 848 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
849
850 return irq;
af42b8d1
SS
851}
852
e6197acc
KRW
853
854int xen_pirq_from_irq(unsigned irq)
855{
856 return pirq_from_irq(irq);
857}
858EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 859int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
860{
861 int irq;
862
77365948 863 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
864
865 irq = evtchn_to_irq[evtchn];
866
867 if (irq == -1) {
c9df1ce5 868 irq = xen_allocate_irq_dynamic();
68ba45ff 869 if (irq < 0)
7bee9768 870 goto out;
e46cdb66 871
c442b806 872 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 873 handle_edge_irq, "event");
e46cdb66 874
9158c358 875 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
876 } else {
877 struct irq_info *info = info_for_irq(irq);
878 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
879 }
880
7bee9768 881out:
77365948 882 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
883
884 return irq;
885}
b536b4b9 886EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 887
f87e4cac
JF
888static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
889{
890 struct evtchn_bind_ipi bind_ipi;
891 int evtchn, irq;
892
77365948 893 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
894
895 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 896
f87e4cac 897 if (irq == -1) {
c9df1ce5 898 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
899 if (irq < 0)
900 goto out;
901
c442b806 902 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 903 handle_percpu_irq, "ipi");
f87e4cac
JF
904
905 bind_ipi.vcpu = cpu;
906 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
907 &bind_ipi) != 0)
908 BUG();
909 evtchn = bind_ipi.port;
910
3d4cfa37 911 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
912
913 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
914 } else {
915 struct irq_info *info = info_for_irq(irq);
916 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
917 }
918
f87e4cac 919 out:
77365948 920 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
921 return irq;
922}
923
2e820f58
IC
924static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
925 unsigned int remote_port)
926{
927 struct evtchn_bind_interdomain bind_interdomain;
928 int err;
929
930 bind_interdomain.remote_dom = remote_domain;
931 bind_interdomain.remote_port = remote_port;
932
933 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
934 &bind_interdomain);
935
936 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
937}
938
62cc5fc7
OH
939static int find_virq(unsigned int virq, unsigned int cpu)
940{
941 struct evtchn_status status;
942 int port, rc = -ENOENT;
943
944 memset(&status, 0, sizeof(status));
945 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
946 status.dom = DOMID_SELF;
947 status.port = port;
948 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
949 if (rc < 0)
950 continue;
951 if (status.status != EVTCHNSTAT_virq)
952 continue;
953 if (status.u.virq == virq && status.vcpu == cpu) {
954 rc = port;
955 break;
956 }
957 }
958 return rc;
959}
f87e4cac 960
4fe7d5a7 961int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
962{
963 struct evtchn_bind_virq bind_virq;
62cc5fc7 964 int evtchn, irq, ret;
e46cdb66 965
77365948 966 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
967
968 irq = per_cpu(virq_to_irq, cpu)[virq];
969
970 if (irq == -1) {
c9df1ce5 971 irq = xen_allocate_irq_dynamic();
68ba45ff 972 if (irq < 0)
7bee9768 973 goto out;
a52521f1 974
c442b806 975 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
976 handle_percpu_irq, "virq");
977
e46cdb66
JF
978 bind_virq.virq = virq;
979 bind_virq.vcpu = cpu;
62cc5fc7
OH
980 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
981 &bind_virq);
982 if (ret == 0)
983 evtchn = bind_virq.port;
984 else {
985 if (ret == -EEXIST)
986 ret = find_virq(virq, cpu);
987 BUG_ON(ret < 0);
988 evtchn = ret;
989 }
e46cdb66 990
3d4cfa37 991 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
992
993 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
994 } else {
995 struct irq_info *info = info_for_irq(irq);
996 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
997 }
998
7bee9768 999out:
77365948 1000 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1001
1002 return irq;
1003}
1004
1005static void unbind_from_irq(unsigned int irq)
1006{
1007 struct evtchn_close close;
1008 int evtchn = evtchn_from_irq(irq);
420eb554 1009 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 1010
94032c50
KRW
1011 if (WARN_ON(!info))
1012 return;
1013
77365948 1014 mutex_lock(&irq_mapping_update_lock);
e46cdb66 1015
420eb554
DDG
1016 if (info->refcnt > 0) {
1017 info->refcnt--;
1018 if (info->refcnt != 0)
1019 goto done;
1020 }
1021
d77bbd4d 1022 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
1023 close.port = evtchn;
1024 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
1025 BUG();
1026
1027 switch (type_from_irq(irq)) {
1028 case IRQT_VIRQ:
1029 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1030 [virq_from_irq(irq)] = -1;
e46cdb66 1031 break;
d68d82af
AN
1032 case IRQT_IPI:
1033 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1034 [ipi_from_irq(irq)] = -1;
d68d82af 1035 break;
e46cdb66
JF
1036 default:
1037 break;
1038 }
1039
1040 /* Closed ports are implicitly re-bound to VCPU0. */
1041 bind_evtchn_to_cpu(evtchn, 0);
1042
1043 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
1044 }
1045
ca62ce8c 1046 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 1047
9158c358 1048 xen_free_irq(irq);
e46cdb66 1049
420eb554 1050 done:
77365948 1051 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1052}
1053
1054int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1055 irq_handler_t handler,
e46cdb66
JF
1056 unsigned long irqflags,
1057 const char *devname, void *dev_id)
1058{
361ae8cb 1059 int irq, retval;
e46cdb66
JF
1060
1061 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1062 if (irq < 0)
1063 return irq;
e46cdb66
JF
1064 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1065 if (retval != 0) {
1066 unbind_from_irq(irq);
1067 return retval;
1068 }
1069
1070 return irq;
1071}
1072EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1073
2e820f58
IC
1074int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1075 unsigned int remote_port,
1076 irq_handler_t handler,
1077 unsigned long irqflags,
1078 const char *devname,
1079 void *dev_id)
1080{
1081 int irq, retval;
1082
1083 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1084 if (irq < 0)
1085 return irq;
1086
1087 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1088 if (retval != 0) {
1089 unbind_from_irq(irq);
1090 return retval;
1091 }
1092
1093 return irq;
1094}
1095EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1096
e46cdb66 1097int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1098 irq_handler_t handler,
e46cdb66
JF
1099 unsigned long irqflags, const char *devname, void *dev_id)
1100{
361ae8cb 1101 int irq, retval;
e46cdb66
JF
1102
1103 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1104 if (irq < 0)
1105 return irq;
e46cdb66
JF
1106 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1107 if (retval != 0) {
1108 unbind_from_irq(irq);
1109 return retval;
1110 }
1111
1112 return irq;
1113}
1114EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1115
f87e4cac
JF
1116int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1117 unsigned int cpu,
1118 irq_handler_t handler,
1119 unsigned long irqflags,
1120 const char *devname,
1121 void *dev_id)
1122{
1123 int irq, retval;
1124
1125 irq = bind_ipi_to_irq(ipi, cpu);
1126 if (irq < 0)
1127 return irq;
1128
9bab0b7f 1129 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1130 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1131 if (retval != 0) {
1132 unbind_from_irq(irq);
1133 return retval;
1134 }
1135
1136 return irq;
1137}
1138
e46cdb66
JF
1139void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1140{
94032c50
KRW
1141 struct irq_info *info = irq_get_handler_data(irq);
1142
1143 if (WARN_ON(!info))
1144 return;
e46cdb66
JF
1145 free_irq(irq, dev_id);
1146 unbind_from_irq(irq);
1147}
1148EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1149
420eb554
DDG
1150int evtchn_make_refcounted(unsigned int evtchn)
1151{
1152 int irq = evtchn_to_irq[evtchn];
1153 struct irq_info *info;
1154
1155 if (irq == -1)
1156 return -ENOENT;
1157
1158 info = irq_get_handler_data(irq);
1159
1160 if (!info)
1161 return -ENOENT;
1162
1163 WARN_ON(info->refcnt != -1);
1164
1165 info->refcnt = 1;
1166
1167 return 0;
1168}
1169EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1170
1171int evtchn_get(unsigned int evtchn)
1172{
1173 int irq;
1174 struct irq_info *info;
1175 int err = -ENOENT;
1176
c3b3f16d
DDG
1177 if (evtchn >= NR_EVENT_CHANNELS)
1178 return -EINVAL;
1179
420eb554
DDG
1180 mutex_lock(&irq_mapping_update_lock);
1181
1182 irq = evtchn_to_irq[evtchn];
1183 if (irq == -1)
1184 goto done;
1185
1186 info = irq_get_handler_data(irq);
1187
1188 if (!info)
1189 goto done;
1190
1191 err = -EINVAL;
1192 if (info->refcnt <= 0)
1193 goto done;
1194
1195 info->refcnt++;
1196 err = 0;
1197 done:
1198 mutex_unlock(&irq_mapping_update_lock);
1199
1200 return err;
1201}
1202EXPORT_SYMBOL_GPL(evtchn_get);
1203
1204void evtchn_put(unsigned int evtchn)
1205{
1206 int irq = evtchn_to_irq[evtchn];
1207 if (WARN_ON(irq == -1))
1208 return;
1209 unbind_from_irq(irq);
1210}
1211EXPORT_SYMBOL_GPL(evtchn_put);
1212
f87e4cac
JF
1213void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1214{
1215 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1216 BUG_ON(irq < 0);
1217 notify_remote_via_irq(irq);
1218}
1219
ee523ca1
JF
1220irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1221{
1222 struct shared_info *sh = HYPERVISOR_shared_info;
1223 int cpu = smp_processor_id();
c81611c4 1224 xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1225 int i;
1226 unsigned long flags;
1227 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1228 struct vcpu_info *v;
ee523ca1
JF
1229
1230 spin_lock_irqsave(&debug_lock, flags);
1231
cb52e6d9 1232 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1233
1234 for_each_online_cpu(i) {
cb52e6d9
IC
1235 int pending;
1236 v = per_cpu(xen_vcpu, i);
1237 pending = (get_irq_regs() && i == cpu)
1238 ? xen_irqs_disabled(get_irq_regs())
1239 : v->evtchn_upcall_mask;
c81611c4 1240 printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
cb52e6d9
IC
1241 pending, v->evtchn_upcall_pending,
1242 (int)(sizeof(v->evtchn_pending_sel)*2),
1243 v->evtchn_pending_sel);
1244 }
1245 v = per_cpu(xen_vcpu, cpu);
1246
1247 printk("\npending:\n ");
1248 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
c81611c4
IC
1249 printk("%0*"PRI_xen_ulong"%s",
1250 (int)sizeof(sh->evtchn_pending[0])*2,
cb52e6d9
IC
1251 sh->evtchn_pending[i],
1252 i % 8 == 0 ? "\n " : " ");
1253 printk("\nglobal mask:\n ");
1254 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4 1255 printk("%0*"PRI_xen_ulong"%s",
cb52e6d9
IC
1256 (int)(sizeof(sh->evtchn_mask[0])*2),
1257 sh->evtchn_mask[i],
1258 i % 8 == 0 ? "\n " : " ");
1259
1260 printk("\nglobally unmasked:\n ");
1261 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4
IC
1262 printk("%0*"PRI_xen_ulong"%s",
1263 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9
IC
1264 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1265 i % 8 == 0 ? "\n " : " ");
1266
1267 printk("\nlocal cpu%d mask:\n ", cpu);
c81611c4
IC
1268 for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
1269 printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
cb52e6d9
IC
1270 cpu_evtchn[i],
1271 i % 8 == 0 ? "\n " : " ");
1272
1273 printk("\nlocally unmasked:\n ");
1274 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
c81611c4 1275 xen_ulong_t pending = sh->evtchn_pending[i]
cb52e6d9
IC
1276 & ~sh->evtchn_mask[i]
1277 & cpu_evtchn[i];
c81611c4
IC
1278 printk("%0*"PRI_xen_ulong"%s",
1279 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9 1280 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1281 }
ee523ca1
JF
1282
1283 printk("\npending list:\n");
cb52e6d9 1284 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
c81611c4
IC
1285 if (sync_test_bit(i, BM(sh->evtchn_pending))) {
1286 int word_idx = i / BITS_PER_EVTCHN_WORD;
cb52e6d9 1287 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1288 cpu_from_evtchn(i), i,
cb52e6d9 1289 evtchn_to_irq[i],
c81611c4 1290 sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
cb52e6d9 1291 ? "" : " l2-clear",
c81611c4 1292 !sync_test_bit(i, BM(sh->evtchn_mask))
cb52e6d9 1293 ? "" : " globally-masked",
c81611c4 1294 sync_test_bit(i, BM(cpu_evtchn))
cb52e6d9 1295 ? "" : " locally-masked");
ee523ca1
JF
1296 }
1297 }
1298
1299 spin_unlock_irqrestore(&debug_lock, flags);
1300
1301 return IRQ_HANDLED;
1302}
1303
245b2e70 1304static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1305static DEFINE_PER_CPU(unsigned int, current_word_idx);
1306static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1307
ab7f863e
SR
1308/*
1309 * Mask out the i least significant bits of w
1310 */
c81611c4 1311#define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
245b2e70 1312
e46cdb66
JF
1313/*
1314 * Search the CPUs pending events bitmasks. For each one found, map
1315 * the event number to an irq, and feed it into do_IRQ() for
1316 * handling.
1317 *
1318 * Xen uses a two-level bitmap to speed searching. The first level is
1319 * a bitset of words which contain pending event bits. The second
1320 * level is a bitset of pending events themselves.
1321 */
38e20b07 1322static void __xen_evtchn_do_upcall(void)
e46cdb66 1323{
24b51c2f 1324 int start_word_idx, start_bit_idx;
ab7f863e 1325 int word_idx, bit_idx;
bee980d9 1326 int i, irq;
e46cdb66
JF
1327 int cpu = get_cpu();
1328 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1329 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1330 unsigned count;
e46cdb66 1331
229664be 1332 do {
c81611c4 1333 xen_ulong_t pending_words;
bee980d9
KF
1334 xen_ulong_t pending_bits;
1335 struct irq_desc *desc;
e46cdb66 1336
229664be 1337 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1338
b2e4ae69 1339 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1340 goto out;
e46cdb66 1341
c81611c4
IC
1342 /*
1343 * Master flag must be cleared /before/ clearing
1344 * selector flag. xchg_xen_ulong must contain an
1345 * appropriate barrier.
1346 */
bee980d9
KF
1347 if ((irq = per_cpu(virq_to_irq, cpu)[VIRQ_TIMER]) != -1) {
1348 int evtchn = evtchn_from_irq(irq);
1349 word_idx = evtchn / BITS_PER_LONG;
1350 pending_bits = evtchn % BITS_PER_LONG;
1351 if (active_evtchns(cpu, s, word_idx) & (1ULL << pending_bits)) {
1352 desc = irq_to_desc(irq);
1353 if (desc)
1354 generic_handle_irq_desc(irq, desc);
1355 }
1356 }
1357
c81611c4 1358 pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1359
24b51c2f
KF
1360 start_word_idx = __this_cpu_read(current_word_idx);
1361 start_bit_idx = __this_cpu_read(current_bit_idx);
1362
1363 word_idx = start_word_idx;
ab7f863e 1364
24b51c2f 1365 for (i = 0; pending_words != 0; i++) {
c81611c4 1366 xen_ulong_t words;
229664be 1367
ab7f863e
SR
1368 words = MASK_LSBS(pending_words, word_idx);
1369
1370 /*
ada6814c 1371 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1372 */
1373 if (words == 0) {
ada6814c
KF
1374 word_idx = 0;
1375 bit_idx = 0;
ab7f863e
SR
1376 continue;
1377 }
c81611c4 1378 word_idx = EVTCHN_FIRST_BIT(words);
229664be 1379
24b51c2f
KF
1380 pending_bits = active_evtchns(cpu, s, word_idx);
1381 bit_idx = 0; /* usually scan entire word from start */
1382 if (word_idx == start_word_idx) {
1383 /* We scan the starting word in two parts */
1384 if (i == 0)
1385 /* 1st time: start in the middle */
1386 bit_idx = start_bit_idx;
1387 else
1388 /* 2nd time: mask bits done already */
1389 bit_idx &= (1UL << start_bit_idx) - 1;
1390 }
1391
ab7f863e 1392 do {
c81611c4 1393 xen_ulong_t bits;
bee980d9 1394 int port;
229664be 1395
ab7f863e
SR
1396 bits = MASK_LSBS(pending_bits, bit_idx);
1397
1398 /* If we masked out all events, move on. */
ada6814c 1399 if (bits == 0)
ab7f863e 1400 break;
ab7f863e 1401
c81611c4 1402 bit_idx = EVTCHN_FIRST_BIT(bits);
ab7f863e
SR
1403
1404 /* Process port. */
c81611c4 1405 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
ab7f863e
SR
1406 irq = evtchn_to_irq[port];
1407
ca4dbc66
EB
1408 if (irq != -1) {
1409 desc = irq_to_desc(irq);
1410 if (desc)
1411 generic_handle_irq_desc(irq, desc);
1412 }
ab7f863e 1413
c81611c4 1414 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
ada6814c
KF
1415
1416 /* Next caller starts at last processed + 1 */
1417 __this_cpu_write(current_word_idx,
1418 bit_idx ? word_idx :
c81611c4 1419 (word_idx+1) % BITS_PER_EVTCHN_WORD);
ada6814c
KF
1420 __this_cpu_write(current_bit_idx, bit_idx);
1421 } while (bit_idx != 0);
ab7f863e 1422
24b51c2f
KF
1423 /* Scan start_l1i twice; all others once. */
1424 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1425 pending_words &= ~(1UL << word_idx);
ada6814c 1426
c81611c4 1427 word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
e46cdb66 1428 }
e46cdb66 1429
229664be
JF
1430 BUG_ON(!irqs_disabled());
1431
780f36d8
CL
1432 count = __this_cpu_read(xed_nesting_count);
1433 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1434 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1435
1436out:
38e20b07
SY
1437
1438 put_cpu();
1439}
1440
1441void xen_evtchn_do_upcall(struct pt_regs *regs)
1442{
1443 struct pt_regs *old_regs = set_irq_regs(regs);
1444
772aebce 1445 irq_enter();
0ec53ecf 1446#ifdef CONFIG_X86
38e20b07 1447 exit_idle();
0ec53ecf 1448#endif
38e20b07
SY
1449
1450 __xen_evtchn_do_upcall();
1451
3445a8fd
JF
1452 irq_exit();
1453 set_irq_regs(old_regs);
38e20b07 1454}
3445a8fd 1455
38e20b07
SY
1456void xen_hvm_evtchn_do_upcall(void)
1457{
1458 __xen_evtchn_do_upcall();
e46cdb66 1459}
183d03cc 1460EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1461
eb1e305f
JF
1462/* Rebind a new event channel to an existing irq. */
1463void rebind_evtchn_irq(int evtchn, int irq)
1464{
d77bbd4d
JF
1465 struct irq_info *info = info_for_irq(irq);
1466
94032c50
KRW
1467 if (WARN_ON(!info))
1468 return;
1469
eb1e305f
JF
1470 /* Make sure the irq is masked, since the new event channel
1471 will also be masked. */
1472 disable_irq(irq);
1473
77365948 1474 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1475
1476 /* After resume the irq<->evtchn mappings are all cleared out */
1477 BUG_ON(evtchn_to_irq[evtchn] != -1);
1478 /* Expect irq to have been bound before,
d77bbd4d
JF
1479 so there should be a proper type */
1480 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1481
9158c358 1482 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1483
77365948 1484 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1485
1486 /* new event channels are always bound to cpu 0 */
0de26520 1487 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1488
1489 /* Unmask the event channel. */
1490 enable_irq(irq);
1491}
1492
e46cdb66 1493/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1494static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1495{
1496 struct evtchn_bind_vcpu bind_vcpu;
1497 int evtchn = evtchn_from_irq(irq);
1498
be49472f
IC
1499 if (!VALID_EVTCHN(evtchn))
1500 return -1;
1501
1502 /*
1503 * Events delivered via platform PCI interrupts are always
1504 * routed to vcpu 0 and hence cannot be rebound.
1505 */
1506 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1507 return -1;
e46cdb66
JF
1508
1509 /* Send future instances of this interrupt to other vcpu. */
1510 bind_vcpu.port = evtchn;
1511 bind_vcpu.vcpu = tcpu;
1512
1513 /*
1514 * If this fails, it usually just indicates that we're dealing with a
1515 * virq or IPI channel, which don't actually need to be rebound. Ignore
1516 * it, but don't do the xenlinux-level rebind in that case.
1517 */
1518 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1519 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1520
d5dedd45
YL
1521 return 0;
1522}
e46cdb66 1523
c9e265e0
TG
1524static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1525 bool force)
e46cdb66 1526{
0de26520 1527 unsigned tcpu = cpumask_first(dest);
d5dedd45 1528
c9e265e0 1529 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1530}
1531
642e0c88
IY
1532int resend_irq_on_evtchn(unsigned int irq)
1533{
1534 int masked, evtchn = evtchn_from_irq(irq);
1535 struct shared_info *s = HYPERVISOR_shared_info;
1536
1537 if (!VALID_EVTCHN(evtchn))
1538 return 1;
1539
c81611c4
IC
1540 masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
1541 sync_set_bit(evtchn, BM(s->evtchn_pending));
642e0c88
IY
1542 if (!masked)
1543 unmask_evtchn(evtchn);
1544
1545 return 1;
1546}
1547
c9e265e0 1548static void enable_dynirq(struct irq_data *data)
e46cdb66 1549{
c9e265e0 1550 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1551
1552 if (VALID_EVTCHN(evtchn))
1553 unmask_evtchn(evtchn);
1554}
1555
c9e265e0 1556static void disable_dynirq(struct irq_data *data)
e46cdb66 1557{
c9e265e0 1558 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1559
1560 if (VALID_EVTCHN(evtchn))
1561 mask_evtchn(evtchn);
1562}
1563
c9e265e0 1564static void ack_dynirq(struct irq_data *data)
e46cdb66 1565{
c9e265e0 1566 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1567
7e186bdd 1568 irq_move_irq(data);
e46cdb66
JF
1569
1570 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1571 clear_evtchn(evtchn);
1572}
1573
1574static void mask_ack_dynirq(struct irq_data *data)
1575{
1576 disable_dynirq(data);
1577 ack_dynirq(data);
e46cdb66
JF
1578}
1579
c9e265e0 1580static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1581{
c9e265e0 1582 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1583 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1584 int ret = 0;
1585
1586 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1587 int masked;
1588
c81611c4
IC
1589 masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask));
1590 sync_set_bit(evtchn, BM(sh->evtchn_pending));
ee8fa1c6
JF
1591 if (!masked)
1592 unmask_evtchn(evtchn);
e46cdb66
JF
1593 ret = 1;
1594 }
1595
1596 return ret;
1597}
1598
0a85226f 1599static void restore_pirqs(void)
9a069c33
SS
1600{
1601 int pirq, rc, irq, gsi;
1602 struct physdev_map_pirq map_irq;
69c358ce 1603 struct irq_info *info;
9a069c33 1604
69c358ce
IC
1605 list_for_each_entry(info, &xen_irq_list_head, list) {
1606 if (info->type != IRQT_PIRQ)
9a069c33
SS
1607 continue;
1608
69c358ce
IC
1609 pirq = info->u.pirq.pirq;
1610 gsi = info->u.pirq.gsi;
1611 irq = info->irq;
1612
9a069c33
SS
1613 /* save/restore of PT devices doesn't work, so at this point the
1614 * only devices present are GSI based emulated devices */
9a069c33
SS
1615 if (!gsi)
1616 continue;
1617
1618 map_irq.domid = DOMID_SELF;
1619 map_irq.type = MAP_PIRQ_TYPE_GSI;
1620 map_irq.index = gsi;
1621 map_irq.pirq = pirq;
1622
1623 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1624 if (rc) {
283c0972
JP
1625 pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1626 gsi, irq, pirq, rc);
9158c358 1627 xen_free_irq(irq);
9a069c33
SS
1628 continue;
1629 }
1630
1631 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1632
c9e265e0 1633 __startup_pirq(irq);
9a069c33
SS
1634 }
1635}
1636
0e91398f
JF
1637static void restore_cpu_virqs(unsigned int cpu)
1638{
1639 struct evtchn_bind_virq bind_virq;
1640 int virq, irq, evtchn;
1641
1642 for (virq = 0; virq < NR_VIRQS; virq++) {
1643 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1644 continue;
1645
ced40d0f 1646 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1647
1648 /* Get a new binding from Xen. */
1649 bind_virq.virq = virq;
1650 bind_virq.vcpu = cpu;
1651 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1652 &bind_virq) != 0)
1653 BUG();
1654 evtchn = bind_virq.port;
1655
1656 /* Record the new mapping. */
3d4cfa37 1657 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1658 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1659 }
1660}
1661
1662static void restore_cpu_ipis(unsigned int cpu)
1663{
1664 struct evtchn_bind_ipi bind_ipi;
1665 int ipi, irq, evtchn;
1666
1667 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1668 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1669 continue;
1670
ced40d0f 1671 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1672
1673 /* Get a new binding from Xen. */
1674 bind_ipi.vcpu = cpu;
1675 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1676 &bind_ipi) != 0)
1677 BUG();
1678 evtchn = bind_ipi.port;
1679
1680 /* Record the new mapping. */
3d4cfa37 1681 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1682 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1683 }
1684}
1685
2d9e1e2f
JF
1686/* Clear an irq's pending state, in preparation for polling on it */
1687void xen_clear_irq_pending(int irq)
1688{
1689 int evtchn = evtchn_from_irq(irq);
1690
1691 if (VALID_EVTCHN(evtchn))
1692 clear_evtchn(evtchn);
1693}
d9a8814f 1694EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1695void xen_set_irq_pending(int irq)
1696{
1697 int evtchn = evtchn_from_irq(irq);
1698
1699 if (VALID_EVTCHN(evtchn))
1700 set_evtchn(evtchn);
1701}
1702
1703bool xen_test_irq_pending(int irq)
1704{
1705 int evtchn = evtchn_from_irq(irq);
1706 bool ret = false;
1707
1708 if (VALID_EVTCHN(evtchn))
1709 ret = test_evtchn(evtchn);
1710
1711 return ret;
1712}
1713
d9a8814f
KRW
1714/* Poll waiting for an irq to become pending with timeout. In the usual case,
1715 * the irq will be disabled so it won't deliver an interrupt. */
1716void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1717{
1718 evtchn_port_t evtchn = evtchn_from_irq(irq);
1719
1720 if (VALID_EVTCHN(evtchn)) {
1721 struct sched_poll poll;
1722
1723 poll.nr_ports = 1;
d9a8814f 1724 poll.timeout = timeout;
ff3c5362 1725 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1726
1727 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1728 BUG();
1729 }
1730}
d9a8814f
KRW
1731EXPORT_SYMBOL(xen_poll_irq_timeout);
1732/* Poll waiting for an irq to become pending. In the usual case, the
1733 * irq will be disabled so it won't deliver an interrupt. */
1734void xen_poll_irq(int irq)
1735{
1736 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1737}
2d9e1e2f 1738
c7c2c3a2
KRW
1739/* Check whether the IRQ line is shared with other guests. */
1740int xen_test_irq_shared(int irq)
1741{
1742 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1743 struct physdev_irq_status_query irq_status;
1744
1745 if (WARN_ON(!info))
1746 return -ENOENT;
1747
1748 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1749
1750 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1751 return 0;
1752 return !(irq_status.flags & XENIRQSTAT_shared);
1753}
1754EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1755
0e91398f
JF
1756void xen_irq_resume(void)
1757{
6cb6537d
IC
1758 unsigned int cpu, evtchn;
1759 struct irq_info *info;
0e91398f
JF
1760
1761 init_evtchn_cpu_bindings();
1762
1763 /* New event-channel space is not 'live' yet. */
1764 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1765 mask_evtchn(evtchn);
1766
1767 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1768 list_for_each_entry(info, &xen_irq_list_head, list)
1769 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1770
1771 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1772 evtchn_to_irq[evtchn] = -1;
1773
1774 for_each_possible_cpu(cpu) {
1775 restore_cpu_virqs(cpu);
1776 restore_cpu_ipis(cpu);
1777 }
6903591f 1778
0a85226f 1779 restore_pirqs();
0e91398f
JF
1780}
1781
e46cdb66 1782static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1783 .name = "xen-dyn",
54a353a0 1784
c9e265e0
TG
1785 .irq_disable = disable_dynirq,
1786 .irq_mask = disable_dynirq,
1787 .irq_unmask = enable_dynirq,
54a353a0 1788
7e186bdd
SS
1789 .irq_ack = ack_dynirq,
1790 .irq_mask_ack = mask_ack_dynirq,
1791
c9e265e0
TG
1792 .irq_set_affinity = set_affinity_irq,
1793 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1794};
1795
d46a78b0 1796static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1797 .name = "xen-pirq",
d46a78b0 1798
c9e265e0
TG
1799 .irq_startup = startup_pirq,
1800 .irq_shutdown = shutdown_pirq,
c9e265e0 1801 .irq_enable = enable_pirq,
c9e265e0 1802 .irq_disable = disable_pirq,
d46a78b0 1803
7e186bdd
SS
1804 .irq_mask = disable_dynirq,
1805 .irq_unmask = enable_dynirq,
1806
1807 .irq_ack = eoi_pirq,
1808 .irq_eoi = eoi_pirq,
1809 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1810
c9e265e0 1811 .irq_set_affinity = set_affinity_irq,
d46a78b0 1812
c9e265e0 1813 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1814};
1815
aaca4964 1816static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1817 .name = "xen-percpu",
aaca4964 1818
c9e265e0
TG
1819 .irq_disable = disable_dynirq,
1820 .irq_mask = disable_dynirq,
1821 .irq_unmask = enable_dynirq,
aaca4964 1822
c9e265e0 1823 .irq_ack = ack_dynirq,
aaca4964
JF
1824};
1825
38e20b07
SY
1826int xen_set_callback_via(uint64_t via)
1827{
1828 struct xen_hvm_param a;
1829 a.domid = DOMID_SELF;
1830 a.index = HVM_PARAM_CALLBACK_IRQ;
1831 a.value = via;
1832 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1833}
1834EXPORT_SYMBOL_GPL(xen_set_callback_via);
1835
ca65f9fc 1836#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1837/* Vector callbacks are better than PCI interrupts to receive event
1838 * channel notifications because we can receive vector callbacks on any
1839 * vcpu and we don't need PCI support or APIC interactions. */
1840void xen_callback_vector(void)
1841{
1842 int rc;
1843 uint64_t callback_via;
1844 if (xen_have_vector_callback) {
bc2b0331 1845 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1846 rc = xen_set_callback_via(callback_via);
1847 if (rc) {
283c0972 1848 pr_err("Request for Xen HVM callback vector failed\n");
38e20b07
SY
1849 xen_have_vector_callback = 0;
1850 return;
1851 }
283c0972 1852 pr_info("Xen HVM callback vector for event delivery is enabled\n");
38e20b07 1853 /* in the restore case the vector has already been allocated */
bc2b0331
S
1854 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1855 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1856 xen_hvm_callback_vector);
38e20b07
SY
1857 }
1858}
ca65f9fc
SS
1859#else
1860void xen_callback_vector(void) {}
1861#endif
38e20b07 1862
2e3d8860 1863void __init xen_init_IRQ(void)
e46cdb66 1864{
0ec53ecf 1865 int i;
c7a3589e 1866
b21ddbf5
JF
1867 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1868 GFP_KERNEL);
9d093e29 1869 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1870 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1871 evtchn_to_irq[i] = -1;
e46cdb66
JF
1872
1873 init_evtchn_cpu_bindings();
1874
1875 /* No event channels are 'live' right now. */
1876 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1877 mask_evtchn(i);
1878
9846ff10
SS
1879 pirq_needs_eoi = pirq_needs_eoi_flag;
1880
0ec53ecf 1881#ifdef CONFIG_X86
38e20b07
SY
1882 if (xen_hvm_domain()) {
1883 xen_callback_vector();
1884 native_init_IRQ();
3942b740
SS
1885 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1886 * __acpi_register_gsi can point at the right function */
1887 pci_xen_hvm_init();
38e20b07 1888 } else {
0ec53ecf 1889 int rc;
9846ff10
SS
1890 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1891
38e20b07 1892 irq_ctx_init(smp_processor_id());
38aa66fc 1893 if (xen_initial_domain())
a0ee0567 1894 pci_xen_initial_domain();
9846ff10
SS
1895
1896 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1897 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1898 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1899 if (rc != 0) {
1900 free_page((unsigned long) pirq_eoi_map);
1901 pirq_eoi_map = NULL;
1902 } else
1903 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1904 }
0ec53ecf 1905#endif
e46cdb66 1906}