Commit | Line | Data |
---|---|---|
e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
25985edc | 8 | * chip. When an event is received, it is mapped to an irq and sent |
e46cdb66 JF |
9 | * through the normal interrupt processing path. |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
283c0972 JP |
24 | #define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt |
25 | ||
e46cdb66 JF |
26 | #include <linux/linkage.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/string.h> | |
28e08861 | 31 | #include <linux/bootmem.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b21ddbf5 | 33 | #include <linux/irqnr.h> |
f731e3ef | 34 | #include <linux/pci.h> |
e46cdb66 | 35 | |
0ec53ecf | 36 | #ifdef CONFIG_X86 |
38e20b07 | 37 | #include <asm/desc.h> |
e46cdb66 JF |
38 | #include <asm/ptrace.h> |
39 | #include <asm/irq.h> | |
792dc4f6 | 40 | #include <asm/idle.h> |
0794bfc7 | 41 | #include <asm/io_apic.h> |
9846ff10 | 42 | #include <asm/xen/page.h> |
42a1de56 | 43 | #include <asm/xen/pci.h> |
0ec53ecf SS |
44 | #endif |
45 | #include <asm/sync_bitops.h> | |
e46cdb66 | 46 | #include <asm/xen/hypercall.h> |
8d1b8753 | 47 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 48 | |
38e20b07 SY |
49 | #include <xen/xen.h> |
50 | #include <xen/hvm.h> | |
e04d0d07 | 51 | #include <xen/xen-ops.h> |
e46cdb66 JF |
52 | #include <xen/events.h> |
53 | #include <xen/interface/xen.h> | |
54 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
55 | #include <xen/interface/hvm/hvm_op.h> |
56 | #include <xen/interface/hvm/params.h> | |
0ec53ecf SS |
57 | #include <xen/interface/physdev.h> |
58 | #include <xen/interface/sched.h> | |
6efa20e4 | 59 | #include <xen/interface/vcpu.h> |
0ec53ecf | 60 | #include <asm/hw_irq.h> |
e46cdb66 | 61 | |
9a489f45 DV |
62 | #include "events_internal.h" |
63 | ||
ab9a1cca DV |
64 | const struct evtchn_ops *evtchn_ops; |
65 | ||
e46cdb66 JF |
66 | /* |
67 | * This lock protects updates to the following mapping and reference-count | |
68 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
69 | */ | |
77365948 | 70 | static DEFINE_MUTEX(irq_mapping_update_lock); |
e46cdb66 | 71 | |
6cb6537d IC |
72 | static LIST_HEAD(xen_irq_list_head); |
73 | ||
e46cdb66 | 74 | /* IRQ <-> VIRQ mapping. */ |
204fba4a | 75 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 76 | |
f87e4cac | 77 | /* IRQ <-> IPI mapping */ |
204fba4a | 78 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 79 | |
d0b075ff | 80 | int **evtchn_to_irq; |
bf86ad80 | 81 | #ifdef CONFIG_X86 |
9846ff10 | 82 | static unsigned long *pirq_eoi_map; |
bf86ad80 | 83 | #endif |
9846ff10 | 84 | static bool (*pirq_needs_eoi)(unsigned irq); |
3b32f574 | 85 | |
d0b075ff DV |
86 | #define EVTCHN_ROW(e) (e / (PAGE_SIZE/sizeof(**evtchn_to_irq))) |
87 | #define EVTCHN_COL(e) (e % (PAGE_SIZE/sizeof(**evtchn_to_irq))) | |
88 | #define EVTCHN_PER_ROW (PAGE_SIZE / sizeof(**evtchn_to_irq)) | |
89 | ||
e46cdb66 JF |
90 | /* Xen will never allocate port zero for any purpose. */ |
91 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
92 | ||
e46cdb66 | 93 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 94 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 95 | static struct irq_chip xen_pirq_chip; |
7e186bdd SS |
96 | static void enable_dynirq(struct irq_data *data); |
97 | static void disable_dynirq(struct irq_data *data); | |
e46cdb66 | 98 | |
d0b075ff DV |
99 | static void clear_evtchn_to_irq_row(unsigned row) |
100 | { | |
101 | unsigned col; | |
102 | ||
103 | for (col = 0; col < EVTCHN_PER_ROW; col++) | |
104 | evtchn_to_irq[row][col] = -1; | |
105 | } | |
106 | ||
107 | static void clear_evtchn_to_irq_all(void) | |
108 | { | |
109 | unsigned row; | |
110 | ||
111 | for (row = 0; row < EVTCHN_ROW(xen_evtchn_max_channels()); row++) { | |
112 | if (evtchn_to_irq[row] == NULL) | |
113 | continue; | |
114 | clear_evtchn_to_irq_row(row); | |
115 | } | |
116 | } | |
117 | ||
118 | static int set_evtchn_to_irq(unsigned evtchn, unsigned irq) | |
119 | { | |
120 | unsigned row; | |
121 | unsigned col; | |
122 | ||
123 | if (evtchn >= xen_evtchn_max_channels()) | |
124 | return -EINVAL; | |
125 | ||
126 | row = EVTCHN_ROW(evtchn); | |
127 | col = EVTCHN_COL(evtchn); | |
128 | ||
129 | if (evtchn_to_irq[row] == NULL) { | |
130 | /* Unallocated irq entries return -1 anyway */ | |
131 | if (irq == -1) | |
132 | return 0; | |
133 | ||
134 | evtchn_to_irq[row] = (int *)get_zeroed_page(GFP_KERNEL); | |
135 | if (evtchn_to_irq[row] == NULL) | |
136 | return -ENOMEM; | |
137 | ||
138 | clear_evtchn_to_irq_row(row); | |
139 | } | |
140 | ||
141 | evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)] = irq; | |
142 | return 0; | |
143 | } | |
144 | ||
145 | int get_evtchn_to_irq(unsigned evtchn) | |
146 | { | |
147 | if (evtchn >= xen_evtchn_max_channels()) | |
148 | return -1; | |
149 | if (evtchn_to_irq[EVTCHN_ROW(evtchn)] == NULL) | |
150 | return -1; | |
151 | return evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)]; | |
152 | } | |
153 | ||
9158c358 | 154 | /* Get info for IRQ */ |
9a489f45 | 155 | struct irq_info *info_for_irq(unsigned irq) |
ced40d0f | 156 | { |
c442b806 | 157 | return irq_get_handler_data(irq); |
ced40d0f JF |
158 | } |
159 | ||
9158c358 | 160 | /* Constructors for packed IRQ information. */ |
96d4c588 | 161 | static int xen_irq_info_common_setup(struct irq_info *info, |
3d4cfa37 | 162 | unsigned irq, |
9158c358 | 163 | enum xen_irq_type type, |
d0b075ff | 164 | unsigned evtchn, |
9158c358 | 165 | unsigned short cpu) |
ced40d0f | 166 | { |
d0b075ff | 167 | int ret; |
9158c358 IC |
168 | |
169 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
170 | ||
171 | info->type = type; | |
6cb6537d | 172 | info->irq = irq; |
9158c358 IC |
173 | info->evtchn = evtchn; |
174 | info->cpu = cpu; | |
3d4cfa37 | 175 | |
d0b075ff DV |
176 | ret = set_evtchn_to_irq(evtchn, irq); |
177 | if (ret < 0) | |
178 | return ret; | |
934f585e JG |
179 | |
180 | irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN); | |
96d4c588 | 181 | |
08385875 | 182 | return xen_evtchn_port_setup(info); |
ced40d0f JF |
183 | } |
184 | ||
96d4c588 | 185 | static int xen_irq_info_evtchn_setup(unsigned irq, |
d0b075ff | 186 | unsigned evtchn) |
ced40d0f | 187 | { |
9158c358 IC |
188 | struct irq_info *info = info_for_irq(irq); |
189 | ||
96d4c588 | 190 | return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0); |
ced40d0f JF |
191 | } |
192 | ||
96d4c588 | 193 | static int xen_irq_info_ipi_setup(unsigned cpu, |
3d4cfa37 | 194 | unsigned irq, |
d0b075ff | 195 | unsigned evtchn, |
9158c358 | 196 | enum ipi_vector ipi) |
e46cdb66 | 197 | { |
9158c358 IC |
198 | struct irq_info *info = info_for_irq(irq); |
199 | ||
9158c358 | 200 | info->u.ipi = ipi; |
3d4cfa37 IC |
201 | |
202 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
96d4c588 DV |
203 | |
204 | return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0); | |
ced40d0f JF |
205 | } |
206 | ||
96d4c588 | 207 | static int xen_irq_info_virq_setup(unsigned cpu, |
3d4cfa37 | 208 | unsigned irq, |
d0b075ff DV |
209 | unsigned evtchn, |
210 | unsigned virq) | |
ced40d0f | 211 | { |
9158c358 IC |
212 | struct irq_info *info = info_for_irq(irq); |
213 | ||
9158c358 | 214 | info->u.virq = virq; |
3d4cfa37 IC |
215 | |
216 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
96d4c588 DV |
217 | |
218 | return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0); | |
ced40d0f JF |
219 | } |
220 | ||
96d4c588 | 221 | static int xen_irq_info_pirq_setup(unsigned irq, |
d0b075ff DV |
222 | unsigned evtchn, |
223 | unsigned pirq, | |
224 | unsigned gsi, | |
beafbdc1 | 225 | uint16_t domid, |
9158c358 | 226 | unsigned char flags) |
ced40d0f | 227 | { |
9158c358 IC |
228 | struct irq_info *info = info_for_irq(irq); |
229 | ||
9158c358 IC |
230 | info->u.pirq.pirq = pirq; |
231 | info->u.pirq.gsi = gsi; | |
beafbdc1 | 232 | info->u.pirq.domid = domid; |
9158c358 | 233 | info->u.pirq.flags = flags; |
96d4c588 DV |
234 | |
235 | return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0); | |
e46cdb66 JF |
236 | } |
237 | ||
d0b075ff DV |
238 | static void xen_irq_info_cleanup(struct irq_info *info) |
239 | { | |
240 | set_evtchn_to_irq(info->evtchn, -1); | |
241 | info->evtchn = 0; | |
242 | } | |
243 | ||
e46cdb66 JF |
244 | /* |
245 | * Accessors for packed IRQ information. | |
246 | */ | |
9a489f45 | 247 | unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 248 | { |
110e7c7e JJ |
249 | if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
250 | return 0; | |
251 | ||
ced40d0f | 252 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
253 | } |
254 | ||
d4c04536 IC |
255 | unsigned irq_from_evtchn(unsigned int evtchn) |
256 | { | |
d0b075ff | 257 | return get_evtchn_to_irq(evtchn); |
d4c04536 IC |
258 | } |
259 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
260 | ||
9a489f45 DV |
261 | int irq_from_virq(unsigned int cpu, unsigned int virq) |
262 | { | |
263 | return per_cpu(virq_to_irq, cpu)[virq]; | |
264 | } | |
265 | ||
ced40d0f | 266 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 267 | { |
ced40d0f JF |
268 | struct irq_info *info = info_for_irq(irq); |
269 | ||
270 | BUG_ON(info == NULL); | |
271 | BUG_ON(info->type != IRQT_IPI); | |
272 | ||
273 | return info->u.ipi; | |
274 | } | |
275 | ||
276 | static unsigned virq_from_irq(unsigned irq) | |
277 | { | |
278 | struct irq_info *info = info_for_irq(irq); | |
279 | ||
280 | BUG_ON(info == NULL); | |
281 | BUG_ON(info->type != IRQT_VIRQ); | |
282 | ||
283 | return info->u.virq; | |
284 | } | |
285 | ||
7a043f11 SS |
286 | static unsigned pirq_from_irq(unsigned irq) |
287 | { | |
288 | struct irq_info *info = info_for_irq(irq); | |
289 | ||
290 | BUG_ON(info == NULL); | |
291 | BUG_ON(info->type != IRQT_PIRQ); | |
292 | ||
293 | return info->u.pirq.pirq; | |
294 | } | |
295 | ||
ced40d0f JF |
296 | static enum xen_irq_type type_from_irq(unsigned irq) |
297 | { | |
298 | return info_for_irq(irq)->type; | |
299 | } | |
300 | ||
9a489f45 | 301 | unsigned cpu_from_irq(unsigned irq) |
ced40d0f JF |
302 | { |
303 | return info_for_irq(irq)->cpu; | |
304 | } | |
305 | ||
9a489f45 | 306 | unsigned int cpu_from_evtchn(unsigned int evtchn) |
ced40d0f | 307 | { |
d0b075ff | 308 | int irq = get_evtchn_to_irq(evtchn); |
ced40d0f JF |
309 | unsigned ret = 0; |
310 | ||
311 | if (irq != -1) | |
312 | ret = cpu_from_irq(irq); | |
313 | ||
314 | return ret; | |
e46cdb66 JF |
315 | } |
316 | ||
bf86ad80 | 317 | #ifdef CONFIG_X86 |
9846ff10 | 318 | static bool pirq_check_eoi_map(unsigned irq) |
d46a78b0 | 319 | { |
521394e4 | 320 | return test_bit(pirq_from_irq(irq), pirq_eoi_map); |
9846ff10 | 321 | } |
bf86ad80 | 322 | #endif |
d46a78b0 | 323 | |
9846ff10 SS |
324 | static bool pirq_needs_eoi_flag(unsigned irq) |
325 | { | |
326 | struct irq_info *info = info_for_irq(irq); | |
d46a78b0 JF |
327 | BUG_ON(info->type != IRQT_PIRQ); |
328 | ||
329 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
330 | } | |
331 | ||
e46cdb66 JF |
332 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) |
333 | { | |
d0b075ff | 334 | int irq = get_evtchn_to_irq(chn); |
9a489f45 | 335 | struct irq_info *info = info_for_irq(irq); |
e46cdb66 JF |
336 | |
337 | BUG_ON(irq == -1); | |
338 | #ifdef CONFIG_SMP | |
c9e265e0 | 339 | cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu)); |
e46cdb66 JF |
340 | #endif |
341 | ||
9a489f45 | 342 | xen_evtchn_port_bind_to_cpu(info, cpu); |
168d2f46 | 343 | |
9a489f45 | 344 | info->cpu = cpu; |
3f70fa82 WL |
345 | } |
346 | ||
e46cdb66 JF |
347 | /** |
348 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
349 | * @irq: irq of event channel to send event to | |
350 | * | |
351 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
352 | * save/restore. Notifications on a broken connection are silently | |
353 | * dropped. | |
354 | */ | |
355 | void notify_remote_via_irq(int irq) | |
356 | { | |
357 | int evtchn = evtchn_from_irq(irq); | |
358 | ||
359 | if (VALID_EVTCHN(evtchn)) | |
360 | notify_remote_via_evtchn(evtchn); | |
361 | } | |
362 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
363 | ||
6cb6537d IC |
364 | static void xen_irq_init(unsigned irq) |
365 | { | |
366 | struct irq_info *info; | |
b5328cd1 | 367 | #ifdef CONFIG_SMP |
6cb6537d IC |
368 | struct irq_desc *desc = irq_to_desc(irq); |
369 | ||
370 | /* By default all event channels notify CPU#0. */ | |
371 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); | |
44626e4a | 372 | #endif |
6cb6537d | 373 | |
ca62ce8c IC |
374 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
375 | if (info == NULL) | |
376 | panic("Unable to allocate metadata for IRQ%d\n", irq); | |
6cb6537d IC |
377 | |
378 | info->type = IRQT_UNBOUND; | |
420eb554 | 379 | info->refcnt = -1; |
6cb6537d | 380 | |
c442b806 | 381 | irq_set_handler_data(irq, info); |
ca62ce8c | 382 | |
6cb6537d IC |
383 | list_add_tail(&info->list, &xen_irq_list_head); |
384 | } | |
385 | ||
7bee9768 | 386 | static int __must_check xen_allocate_irq_dynamic(void) |
0794bfc7 | 387 | { |
89911501 IC |
388 | int first = 0; |
389 | int irq; | |
0794bfc7 KRW |
390 | |
391 | #ifdef CONFIG_X86_IO_APIC | |
89911501 IC |
392 | /* |
393 | * For an HVM guest or domain 0 which see "real" (emulated or | |
25985edc | 394 | * actual respectively) GSIs we allocate dynamic IRQs |
89911501 IC |
395 | * e.g. those corresponding to event channels or MSIs |
396 | * etc. from the range above those "real" GSIs to avoid | |
397 | * collisions. | |
398 | */ | |
399 | if (xen_initial_domain() || xen_hvm_domain()) | |
400 | first = get_nr_irqs_gsi(); | |
0794bfc7 KRW |
401 | #endif |
402 | ||
89911501 | 403 | irq = irq_alloc_desc_from(first, -1); |
3a69e916 | 404 | |
e6599225 KRW |
405 | if (irq >= 0) |
406 | xen_irq_init(irq); | |
ced40d0f | 407 | |
e46cdb66 | 408 | return irq; |
d46a78b0 JF |
409 | } |
410 | ||
7bee9768 | 411 | static int __must_check xen_allocate_irq_gsi(unsigned gsi) |
c9df1ce5 IC |
412 | { |
413 | int irq; | |
414 | ||
89911501 IC |
415 | /* |
416 | * A PV guest has no concept of a GSI (since it has no ACPI | |
417 | * nor access to/knowledge of the physical APICs). Therefore | |
418 | * all IRQs are dynamically allocated from the entire IRQ | |
419 | * space. | |
420 | */ | |
421 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
422 | return xen_allocate_irq_dynamic(); |
423 | ||
424 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
425 | if (gsi < NR_IRQS_LEGACY) | |
6cb6537d IC |
426 | irq = gsi; |
427 | else | |
428 | irq = irq_alloc_desc_at(gsi, -1); | |
c9df1ce5 | 429 | |
6cb6537d | 430 | xen_irq_init(irq); |
c9df1ce5 IC |
431 | |
432 | return irq; | |
433 | } | |
434 | ||
435 | static void xen_free_irq(unsigned irq) | |
436 | { | |
c442b806 | 437 | struct irq_info *info = irq_get_handler_data(irq); |
6cb6537d | 438 | |
94032c50 KRW |
439 | if (WARN_ON(!info)) |
440 | return; | |
441 | ||
6cb6537d | 442 | list_del(&info->list); |
9158c358 | 443 | |
c442b806 | 444 | irq_set_handler_data(irq, NULL); |
ca62ce8c | 445 | |
420eb554 DDG |
446 | WARN_ON(info->refcnt > 0); |
447 | ||
ca62ce8c IC |
448 | kfree(info); |
449 | ||
72146104 IC |
450 | /* Legacy IRQ descriptors are managed by the arch. */ |
451 | if (irq < NR_IRQS_LEGACY) | |
452 | return; | |
453 | ||
c9df1ce5 IC |
454 | irq_free_desc(irq); |
455 | } | |
456 | ||
d0b075ff DV |
457 | static void xen_evtchn_close(unsigned int port) |
458 | { | |
459 | struct evtchn_close close; | |
460 | ||
461 | close.port = port; | |
462 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
463 | BUG(); | |
464 | ||
465 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
466 | bind_evtchn_to_cpu(port, 0); | |
467 | } | |
468 | ||
d46a78b0 JF |
469 | static void pirq_query_unmask(int irq) |
470 | { | |
471 | struct physdev_irq_status_query irq_status; | |
472 | struct irq_info *info = info_for_irq(irq); | |
473 | ||
474 | BUG_ON(info->type != IRQT_PIRQ); | |
475 | ||
7a043f11 | 476 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
477 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
478 | irq_status.flags = 0; | |
479 | ||
480 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
481 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
482 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
483 | } | |
484 | ||
485 | static bool probing_irq(int irq) | |
486 | { | |
487 | struct irq_desc *desc = irq_to_desc(irq); | |
488 | ||
489 | return desc && desc->action == NULL; | |
490 | } | |
491 | ||
7e186bdd SS |
492 | static void eoi_pirq(struct irq_data *data) |
493 | { | |
494 | int evtchn = evtchn_from_irq(data->irq); | |
495 | struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) }; | |
496 | int rc = 0; | |
497 | ||
498 | irq_move_irq(data); | |
499 | ||
500 | if (VALID_EVTCHN(evtchn)) | |
501 | clear_evtchn(evtchn); | |
502 | ||
503 | if (pirq_needs_eoi(data->irq)) { | |
504 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
505 | WARN_ON(rc); | |
506 | } | |
507 | } | |
508 | ||
509 | static void mask_ack_pirq(struct irq_data *data) | |
510 | { | |
511 | disable_dynirq(data); | |
512 | eoi_pirq(data); | |
513 | } | |
514 | ||
c9e265e0 | 515 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
516 | { |
517 | struct evtchn_bind_pirq bind_pirq; | |
518 | struct irq_info *info = info_for_irq(irq); | |
519 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 520 | int rc; |
d46a78b0 JF |
521 | |
522 | BUG_ON(info->type != IRQT_PIRQ); | |
523 | ||
524 | if (VALID_EVTCHN(evtchn)) | |
525 | goto out; | |
526 | ||
7a043f11 | 527 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 528 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
529 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
530 | BIND_PIRQ__WILL_SHARE : 0; | |
531 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
532 | if (rc != 0) { | |
d46a78b0 | 533 | if (!probing_irq(irq)) |
283c0972 | 534 | pr_info("Failed to obtain physical IRQ %d\n", irq); |
d46a78b0 JF |
535 | return 0; |
536 | } | |
537 | evtchn = bind_pirq.port; | |
538 | ||
539 | pirq_query_unmask(irq); | |
540 | ||
d0b075ff DV |
541 | rc = set_evtchn_to_irq(evtchn, irq); |
542 | if (rc != 0) { | |
543 | pr_err("irq%d: Failed to set port to irq mapping (%d)\n", | |
544 | irq, rc); | |
545 | xen_evtchn_close(evtchn); | |
546 | return 0; | |
547 | } | |
d46a78b0 JF |
548 | bind_evtchn_to_cpu(evtchn, 0); |
549 | info->evtchn = evtchn; | |
550 | ||
551 | out: | |
552 | unmask_evtchn(evtchn); | |
7e186bdd | 553 | eoi_pirq(irq_get_irq_data(irq)); |
d46a78b0 JF |
554 | |
555 | return 0; | |
556 | } | |
557 | ||
c9e265e0 TG |
558 | static unsigned int startup_pirq(struct irq_data *data) |
559 | { | |
560 | return __startup_pirq(data->irq); | |
561 | } | |
562 | ||
563 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 | 564 | { |
c9e265e0 | 565 | unsigned int irq = data->irq; |
d46a78b0 | 566 | struct irq_info *info = info_for_irq(irq); |
d0b075ff | 567 | unsigned evtchn = evtchn_from_irq(irq); |
d46a78b0 JF |
568 | |
569 | BUG_ON(info->type != IRQT_PIRQ); | |
570 | ||
571 | if (!VALID_EVTCHN(evtchn)) | |
572 | return; | |
573 | ||
574 | mask_evtchn(evtchn); | |
d0b075ff DV |
575 | xen_evtchn_close(evtchn); |
576 | xen_irq_info_cleanup(info); | |
d46a78b0 JF |
577 | } |
578 | ||
c9e265e0 | 579 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 580 | { |
c9e265e0 | 581 | startup_pirq(data); |
d46a78b0 JF |
582 | } |
583 | ||
c9e265e0 | 584 | static void disable_pirq(struct irq_data *data) |
d46a78b0 | 585 | { |
7e186bdd | 586 | disable_dynirq(data); |
d46a78b0 JF |
587 | } |
588 | ||
68c2c39a | 589 | int xen_irq_from_gsi(unsigned gsi) |
d46a78b0 | 590 | { |
6cb6537d | 591 | struct irq_info *info; |
d46a78b0 | 592 | |
6cb6537d IC |
593 | list_for_each_entry(info, &xen_irq_list_head, list) { |
594 | if (info->type != IRQT_PIRQ) | |
d46a78b0 JF |
595 | continue; |
596 | ||
6cb6537d IC |
597 | if (info->u.pirq.gsi == gsi) |
598 | return info->irq; | |
d46a78b0 JF |
599 | } |
600 | ||
601 | return -1; | |
602 | } | |
68c2c39a | 603 | EXPORT_SYMBOL_GPL(xen_irq_from_gsi); |
d46a78b0 | 604 | |
96d4c588 DV |
605 | static void __unbind_from_irq(unsigned int irq) |
606 | { | |
96d4c588 DV |
607 | int evtchn = evtchn_from_irq(irq); |
608 | struct irq_info *info = irq_get_handler_data(irq); | |
609 | ||
610 | if (info->refcnt > 0) { | |
611 | info->refcnt--; | |
612 | if (info->refcnt != 0) | |
613 | return; | |
614 | } | |
615 | ||
616 | if (VALID_EVTCHN(evtchn)) { | |
d0b075ff DV |
617 | unsigned int cpu = cpu_from_irq(irq); |
618 | ||
619 | xen_evtchn_close(evtchn); | |
96d4c588 DV |
620 | |
621 | switch (type_from_irq(irq)) { | |
622 | case IRQT_VIRQ: | |
d0b075ff | 623 | per_cpu(virq_to_irq, cpu)[virq_from_irq(irq)] = -1; |
96d4c588 DV |
624 | break; |
625 | case IRQT_IPI: | |
d0b075ff | 626 | per_cpu(ipi_to_irq, cpu)[ipi_from_irq(irq)] = -1; |
96d4c588 DV |
627 | break; |
628 | default: | |
629 | break; | |
630 | } | |
631 | ||
d0b075ff | 632 | xen_irq_info_cleanup(info); |
96d4c588 DV |
633 | } |
634 | ||
635 | BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND); | |
636 | ||
637 | xen_free_irq(irq); | |
638 | } | |
639 | ||
653378ac IC |
640 | /* |
641 | * Do not make any assumptions regarding the relationship between the | |
642 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
643 | * |
644 | * Note: We don't assign an event channel until the irq actually started | |
645 | * up. Return an existing irq if we've already got one for the gsi. | |
e5ac0bda SS |
646 | * |
647 | * Shareable implies level triggered, not shareable implies edge | |
648 | * triggered here. | |
d46a78b0 | 649 | */ |
f4d0635b IC |
650 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
651 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 652 | { |
a0e18116 | 653 | int irq = -1; |
d46a78b0 | 654 | struct physdev_irq irq_op; |
96d4c588 | 655 | int ret; |
d46a78b0 | 656 | |
77365948 | 657 | mutex_lock(&irq_mapping_update_lock); |
d46a78b0 | 658 | |
68c2c39a | 659 | irq = xen_irq_from_gsi(gsi); |
d46a78b0 | 660 | if (irq != -1) { |
283c0972 JP |
661 | pr_info("%s: returning irq %d for gsi %u\n", |
662 | __func__, irq, gsi); | |
420eb554 | 663 | goto out; |
d46a78b0 JF |
664 | } |
665 | ||
c9df1ce5 | 666 | irq = xen_allocate_irq_gsi(gsi); |
7bee9768 IC |
667 | if (irq < 0) |
668 | goto out; | |
d46a78b0 | 669 | |
d46a78b0 | 670 | irq_op.irq = irq; |
b5401a96 AN |
671 | irq_op.vector = 0; |
672 | ||
673 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
674 | * driver provides a PCI bus that does the call to do exactly | |
675 | * this in the priv domain. */ | |
676 | if (xen_initial_domain() && | |
677 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 678 | xen_free_irq(irq); |
d46a78b0 JF |
679 | irq = -ENOSPC; |
680 | goto out; | |
681 | } | |
682 | ||
96d4c588 | 683 | ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF, |
9158c358 | 684 | shareable ? PIRQ_SHAREABLE : 0); |
96d4c588 DV |
685 | if (ret < 0) { |
686 | __unbind_from_irq(irq); | |
687 | irq = ret; | |
688 | goto out; | |
689 | } | |
d46a78b0 | 690 | |
7e186bdd SS |
691 | pirq_query_unmask(irq); |
692 | /* We try to use the handler with the appropriate semantic for the | |
e5ac0bda SS |
693 | * type of interrupt: if the interrupt is an edge triggered |
694 | * interrupt we use handle_edge_irq. | |
7e186bdd | 695 | * |
e5ac0bda SS |
696 | * On the other hand if the interrupt is level triggered we use |
697 | * handle_fasteoi_irq like the native code does for this kind of | |
7e186bdd | 698 | * interrupts. |
e5ac0bda | 699 | * |
7e186bdd SS |
700 | * Depending on the Xen version, pirq_needs_eoi might return true |
701 | * not only for level triggered interrupts but for edge triggered | |
702 | * interrupts too. In any case Xen always honors the eoi mechanism, | |
703 | * not injecting any more pirqs of the same kind if the first one | |
704 | * hasn't received an eoi yet. Therefore using the fasteoi handler | |
705 | * is the right choice either way. | |
706 | */ | |
e5ac0bda | 707 | if (shareable) |
7e186bdd SS |
708 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, |
709 | handle_fasteoi_irq, name); | |
710 | else | |
711 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, | |
712 | handle_edge_irq, name); | |
713 | ||
d46a78b0 | 714 | out: |
77365948 | 715 | mutex_unlock(&irq_mapping_update_lock); |
d46a78b0 JF |
716 | |
717 | return irq; | |
718 | } | |
719 | ||
f731e3ef | 720 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 721 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 722 | { |
5cad61a6 | 723 | int rc; |
cbf6aa89 | 724 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 725 | |
bf480d95 | 726 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 727 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 728 | |
5cad61a6 IC |
729 | WARN_ONCE(rc == -ENOSYS, |
730 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
731 | ||
732 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
733 | } |
734 | ||
bf480d95 | 735 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
dec02dea | 736 | int pirq, const char *name, domid_t domid) |
809f9267 | 737 | { |
bf480d95 | 738 | int irq, ret; |
4b41df7f | 739 | |
77365948 | 740 | mutex_lock(&irq_mapping_update_lock); |
809f9267 | 741 | |
4b41df7f | 742 | irq = xen_allocate_irq_dynamic(); |
e6599225 | 743 | if (irq < 0) |
bb5d079a | 744 | goto out; |
809f9267 | 745 | |
7e186bdd SS |
746 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq, |
747 | name); | |
809f9267 | 748 | |
96d4c588 DV |
749 | ret = xen_irq_info_pirq_setup(irq, 0, pirq, 0, domid, 0); |
750 | if (ret < 0) | |
751 | goto error_irq; | |
5f6fb454 | 752 | ret = irq_set_msi_desc(irq, msidesc); |
bf480d95 IC |
753 | if (ret < 0) |
754 | goto error_irq; | |
809f9267 | 755 | out: |
77365948 | 756 | mutex_unlock(&irq_mapping_update_lock); |
4b41df7f | 757 | return irq; |
bf480d95 | 758 | error_irq: |
96d4c588 | 759 | __unbind_from_irq(irq); |
77365948 | 760 | mutex_unlock(&irq_mapping_update_lock); |
e6599225 | 761 | return ret; |
809f9267 | 762 | } |
f731e3ef QH |
763 | #endif |
764 | ||
b5401a96 AN |
765 | int xen_destroy_irq(int irq) |
766 | { | |
767 | struct irq_desc *desc; | |
38aa66fc JF |
768 | struct physdev_unmap_pirq unmap_irq; |
769 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
770 | int rc = -ENOENT; |
771 | ||
77365948 | 772 | mutex_lock(&irq_mapping_update_lock); |
b5401a96 AN |
773 | |
774 | desc = irq_to_desc(irq); | |
775 | if (!desc) | |
776 | goto out; | |
777 | ||
38aa66fc | 778 | if (xen_initial_domain()) { |
12334715 | 779 | unmap_irq.pirq = info->u.pirq.pirq; |
beafbdc1 | 780 | unmap_irq.domid = info->u.pirq.domid; |
38aa66fc | 781 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); |
1eff1ad0 KRW |
782 | /* If another domain quits without making the pci_disable_msix |
783 | * call, the Xen hypervisor takes care of freeing the PIRQs | |
784 | * (free_domain_pirqs). | |
785 | */ | |
786 | if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF)) | |
283c0972 | 787 | pr_info("domain %d does not have %d anymore\n", |
1eff1ad0 KRW |
788 | info->u.pirq.domid, info->u.pirq.pirq); |
789 | else if (rc) { | |
283c0972 | 790 | pr_warn("unmap irq failed %d\n", rc); |
38aa66fc JF |
791 | goto out; |
792 | } | |
793 | } | |
b5401a96 | 794 | |
c9df1ce5 | 795 | xen_free_irq(irq); |
b5401a96 AN |
796 | |
797 | out: | |
77365948 | 798 | mutex_unlock(&irq_mapping_update_lock); |
b5401a96 AN |
799 | return rc; |
800 | } | |
801 | ||
af42b8d1 | 802 | int xen_irq_from_pirq(unsigned pirq) |
d46a78b0 | 803 | { |
69c358ce | 804 | int irq; |
d46a78b0 | 805 | |
69c358ce | 806 | struct irq_info *info; |
e46cdb66 | 807 | |
77365948 | 808 | mutex_lock(&irq_mapping_update_lock); |
69c358ce IC |
809 | |
810 | list_for_each_entry(info, &xen_irq_list_head, list) { | |
9bb9efe4 | 811 | if (info->type != IRQT_PIRQ) |
69c358ce IC |
812 | continue; |
813 | irq = info->irq; | |
814 | if (info->u.pirq.pirq == pirq) | |
815 | goto out; | |
816 | } | |
817 | irq = -1; | |
818 | out: | |
77365948 | 819 | mutex_unlock(&irq_mapping_update_lock); |
69c358ce IC |
820 | |
821 | return irq; | |
af42b8d1 SS |
822 | } |
823 | ||
e6197acc KRW |
824 | |
825 | int xen_pirq_from_irq(unsigned irq) | |
826 | { | |
827 | return pirq_from_irq(irq); | |
828 | } | |
829 | EXPORT_SYMBOL_GPL(xen_pirq_from_irq); | |
96d4c588 | 830 | |
b536b4b9 | 831 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
832 | { |
833 | int irq; | |
96d4c588 | 834 | int ret; |
e46cdb66 | 835 | |
d0b075ff DV |
836 | if (evtchn >= xen_evtchn_max_channels()) |
837 | return -ENOMEM; | |
838 | ||
77365948 | 839 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 | 840 | |
d0b075ff | 841 | irq = get_evtchn_to_irq(evtchn); |
e46cdb66 JF |
842 | |
843 | if (irq == -1) { | |
c9df1ce5 | 844 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 845 | if (irq < 0) |
7bee9768 | 846 | goto out; |
e46cdb66 | 847 | |
c442b806 | 848 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, |
7e186bdd | 849 | handle_edge_irq, "event"); |
e46cdb66 | 850 | |
96d4c588 DV |
851 | ret = xen_irq_info_evtchn_setup(irq, evtchn); |
852 | if (ret < 0) { | |
853 | __unbind_from_irq(irq); | |
854 | irq = ret; | |
855 | goto out; | |
856 | } | |
5e152e6c KRW |
857 | } else { |
858 | struct irq_info *info = info_for_irq(irq); | |
859 | WARN_ON(info == NULL || info->type != IRQT_EVTCHN); | |
e46cdb66 JF |
860 | } |
861 | ||
7bee9768 | 862 | out: |
77365948 | 863 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
864 | |
865 | return irq; | |
866 | } | |
b536b4b9 | 867 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 868 | |
f87e4cac JF |
869 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
870 | { | |
871 | struct evtchn_bind_ipi bind_ipi; | |
872 | int evtchn, irq; | |
96d4c588 | 873 | int ret; |
f87e4cac | 874 | |
77365948 | 875 | mutex_lock(&irq_mapping_update_lock); |
f87e4cac JF |
876 | |
877 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 878 | |
f87e4cac | 879 | if (irq == -1) { |
c9df1ce5 | 880 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
881 | if (irq < 0) |
882 | goto out; | |
883 | ||
c442b806 | 884 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
aaca4964 | 885 | handle_percpu_irq, "ipi"); |
f87e4cac JF |
886 | |
887 | bind_ipi.vcpu = cpu; | |
888 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
889 | &bind_ipi) != 0) | |
890 | BUG(); | |
891 | evtchn = bind_ipi.port; | |
892 | ||
96d4c588 DV |
893 | ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi); |
894 | if (ret < 0) { | |
895 | __unbind_from_irq(irq); | |
896 | irq = ret; | |
897 | goto out; | |
898 | } | |
f87e4cac | 899 | bind_evtchn_to_cpu(evtchn, cpu); |
5e152e6c KRW |
900 | } else { |
901 | struct irq_info *info = info_for_irq(irq); | |
902 | WARN_ON(info == NULL || info->type != IRQT_IPI); | |
f87e4cac JF |
903 | } |
904 | ||
f87e4cac | 905 | out: |
77365948 | 906 | mutex_unlock(&irq_mapping_update_lock); |
f87e4cac JF |
907 | return irq; |
908 | } | |
909 | ||
2e820f58 IC |
910 | static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain, |
911 | unsigned int remote_port) | |
912 | { | |
913 | struct evtchn_bind_interdomain bind_interdomain; | |
914 | int err; | |
915 | ||
916 | bind_interdomain.remote_dom = remote_domain; | |
917 | bind_interdomain.remote_port = remote_port; | |
918 | ||
919 | err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain, | |
920 | &bind_interdomain); | |
921 | ||
922 | return err ? : bind_evtchn_to_irq(bind_interdomain.local_port); | |
923 | } | |
924 | ||
62cc5fc7 OH |
925 | static int find_virq(unsigned int virq, unsigned int cpu) |
926 | { | |
927 | struct evtchn_status status; | |
928 | int port, rc = -ENOENT; | |
929 | ||
930 | memset(&status, 0, sizeof(status)); | |
d0b075ff | 931 | for (port = 0; port < xen_evtchn_max_channels(); port++) { |
62cc5fc7 OH |
932 | status.dom = DOMID_SELF; |
933 | status.port = port; | |
934 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status); | |
935 | if (rc < 0) | |
936 | continue; | |
937 | if (status.status != EVTCHNSTAT_virq) | |
938 | continue; | |
939 | if (status.u.virq == virq && status.vcpu == cpu) { | |
940 | rc = port; | |
941 | break; | |
942 | } | |
943 | } | |
944 | return rc; | |
945 | } | |
f87e4cac | 946 | |
4fe7d5a7 | 947 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
e46cdb66 JF |
948 | { |
949 | struct evtchn_bind_virq bind_virq; | |
62cc5fc7 | 950 | int evtchn, irq, ret; |
e46cdb66 | 951 | |
77365948 | 952 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 JF |
953 | |
954 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
955 | ||
956 | if (irq == -1) { | |
c9df1ce5 | 957 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 958 | if (irq < 0) |
7bee9768 | 959 | goto out; |
a52521f1 | 960 | |
c442b806 | 961 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
a52521f1 JF |
962 | handle_percpu_irq, "virq"); |
963 | ||
e46cdb66 JF |
964 | bind_virq.virq = virq; |
965 | bind_virq.vcpu = cpu; | |
62cc5fc7 OH |
966 | ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, |
967 | &bind_virq); | |
968 | if (ret == 0) | |
969 | evtchn = bind_virq.port; | |
970 | else { | |
971 | if (ret == -EEXIST) | |
972 | ret = find_virq(virq, cpu); | |
973 | BUG_ON(ret < 0); | |
974 | evtchn = ret; | |
975 | } | |
e46cdb66 | 976 | |
96d4c588 DV |
977 | ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq); |
978 | if (ret < 0) { | |
979 | __unbind_from_irq(irq); | |
980 | irq = ret; | |
981 | goto out; | |
982 | } | |
e46cdb66 JF |
983 | |
984 | bind_evtchn_to_cpu(evtchn, cpu); | |
5e152e6c KRW |
985 | } else { |
986 | struct irq_info *info = info_for_irq(irq); | |
987 | WARN_ON(info == NULL || info->type != IRQT_VIRQ); | |
e46cdb66 JF |
988 | } |
989 | ||
7bee9768 | 990 | out: |
77365948 | 991 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
992 | |
993 | return irq; | |
994 | } | |
995 | ||
996 | static void unbind_from_irq(unsigned int irq) | |
997 | { | |
77365948 | 998 | mutex_lock(&irq_mapping_update_lock); |
96d4c588 | 999 | __unbind_from_irq(irq); |
77365948 | 1000 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
1001 | } |
1002 | ||
1003 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 1004 | irq_handler_t handler, |
e46cdb66 JF |
1005 | unsigned long irqflags, |
1006 | const char *devname, void *dev_id) | |
1007 | { | |
361ae8cb | 1008 | int irq, retval; |
e46cdb66 JF |
1009 | |
1010 | irq = bind_evtchn_to_irq(evtchn); | |
7bee9768 IC |
1011 | if (irq < 0) |
1012 | return irq; | |
e46cdb66 JF |
1013 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1014 | if (retval != 0) { | |
1015 | unbind_from_irq(irq); | |
1016 | return retval; | |
1017 | } | |
1018 | ||
1019 | return irq; | |
1020 | } | |
1021 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
1022 | ||
2e820f58 IC |
1023 | int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain, |
1024 | unsigned int remote_port, | |
1025 | irq_handler_t handler, | |
1026 | unsigned long irqflags, | |
1027 | const char *devname, | |
1028 | void *dev_id) | |
1029 | { | |
1030 | int irq, retval; | |
1031 | ||
1032 | irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port); | |
1033 | if (irq < 0) | |
1034 | return irq; | |
1035 | ||
1036 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
1037 | if (retval != 0) { | |
1038 | unbind_from_irq(irq); | |
1039 | return retval; | |
1040 | } | |
1041 | ||
1042 | return irq; | |
1043 | } | |
1044 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler); | |
1045 | ||
e46cdb66 | 1046 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, |
7c239975 | 1047 | irq_handler_t handler, |
e46cdb66 JF |
1048 | unsigned long irqflags, const char *devname, void *dev_id) |
1049 | { | |
361ae8cb | 1050 | int irq, retval; |
e46cdb66 JF |
1051 | |
1052 | irq = bind_virq_to_irq(virq, cpu); | |
7bee9768 IC |
1053 | if (irq < 0) |
1054 | return irq; | |
e46cdb66 JF |
1055 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1056 | if (retval != 0) { | |
1057 | unbind_from_irq(irq); | |
1058 | return retval; | |
1059 | } | |
1060 | ||
1061 | return irq; | |
1062 | } | |
1063 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
1064 | ||
f87e4cac JF |
1065 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
1066 | unsigned int cpu, | |
1067 | irq_handler_t handler, | |
1068 | unsigned long irqflags, | |
1069 | const char *devname, | |
1070 | void *dev_id) | |
1071 | { | |
1072 | int irq, retval; | |
1073 | ||
1074 | irq = bind_ipi_to_irq(ipi, cpu); | |
1075 | if (irq < 0) | |
1076 | return irq; | |
1077 | ||
9bab0b7f | 1078 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME; |
f87e4cac JF |
1079 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1080 | if (retval != 0) { | |
1081 | unbind_from_irq(irq); | |
1082 | return retval; | |
1083 | } | |
1084 | ||
1085 | return irq; | |
1086 | } | |
1087 | ||
e46cdb66 JF |
1088 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
1089 | { | |
94032c50 KRW |
1090 | struct irq_info *info = irq_get_handler_data(irq); |
1091 | ||
1092 | if (WARN_ON(!info)) | |
1093 | return; | |
e46cdb66 JF |
1094 | free_irq(irq, dev_id); |
1095 | unbind_from_irq(irq); | |
1096 | } | |
1097 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1098 | ||
420eb554 DDG |
1099 | int evtchn_make_refcounted(unsigned int evtchn) |
1100 | { | |
d0b075ff | 1101 | int irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1102 | struct irq_info *info; |
1103 | ||
1104 | if (irq == -1) | |
1105 | return -ENOENT; | |
1106 | ||
1107 | info = irq_get_handler_data(irq); | |
1108 | ||
1109 | if (!info) | |
1110 | return -ENOENT; | |
1111 | ||
1112 | WARN_ON(info->refcnt != -1); | |
1113 | ||
1114 | info->refcnt = 1; | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | EXPORT_SYMBOL_GPL(evtchn_make_refcounted); | |
1119 | ||
1120 | int evtchn_get(unsigned int evtchn) | |
1121 | { | |
1122 | int irq; | |
1123 | struct irq_info *info; | |
1124 | int err = -ENOENT; | |
1125 | ||
d0b075ff | 1126 | if (evtchn >= xen_evtchn_max_channels()) |
c3b3f16d DDG |
1127 | return -EINVAL; |
1128 | ||
420eb554 DDG |
1129 | mutex_lock(&irq_mapping_update_lock); |
1130 | ||
d0b075ff | 1131 | irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1132 | if (irq == -1) |
1133 | goto done; | |
1134 | ||
1135 | info = irq_get_handler_data(irq); | |
1136 | ||
1137 | if (!info) | |
1138 | goto done; | |
1139 | ||
1140 | err = -EINVAL; | |
1141 | if (info->refcnt <= 0) | |
1142 | goto done; | |
1143 | ||
1144 | info->refcnt++; | |
1145 | err = 0; | |
1146 | done: | |
1147 | mutex_unlock(&irq_mapping_update_lock); | |
1148 | ||
1149 | return err; | |
1150 | } | |
1151 | EXPORT_SYMBOL_GPL(evtchn_get); | |
1152 | ||
1153 | void evtchn_put(unsigned int evtchn) | |
1154 | { | |
d0b075ff | 1155 | int irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1156 | if (WARN_ON(irq == -1)) |
1157 | return; | |
1158 | unbind_from_irq(irq); | |
1159 | } | |
1160 | EXPORT_SYMBOL_GPL(evtchn_put); | |
1161 | ||
f87e4cac JF |
1162 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1163 | { | |
6efa20e4 KRW |
1164 | int irq; |
1165 | ||
072b2064 | 1166 | #ifdef CONFIG_X86 |
6efa20e4 KRW |
1167 | if (unlikely(vector == XEN_NMI_VECTOR)) { |
1168 | int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL); | |
1169 | if (rc < 0) | |
1170 | printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc); | |
1171 | return; | |
1172 | } | |
072b2064 | 1173 | #endif |
6efa20e4 | 1174 | irq = per_cpu(ipi_to_irq, cpu)[vector]; |
f87e4cac JF |
1175 | BUG_ON(irq < 0); |
1176 | notify_remote_via_irq(irq); | |
1177 | } | |
1178 | ||
245b2e70 TH |
1179 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
1180 | ||
38e20b07 | 1181 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 | 1182 | { |
780f36d8 | 1183 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
9a489f45 | 1184 | int cpu = get_cpu(); |
088c05a8 | 1185 | unsigned count; |
e46cdb66 | 1186 | |
229664be | 1187 | do { |
229664be | 1188 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1189 | |
b2e4ae69 | 1190 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1191 | goto out; |
e46cdb66 | 1192 | |
9a489f45 | 1193 | xen_evtchn_handle_events(cpu); |
e46cdb66 | 1194 | |
229664be JF |
1195 | BUG_ON(!irqs_disabled()); |
1196 | ||
780f36d8 CL |
1197 | count = __this_cpu_read(xed_nesting_count); |
1198 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1199 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1200 | |
1201 | out: | |
38e20b07 SY |
1202 | |
1203 | put_cpu(); | |
1204 | } | |
1205 | ||
1206 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1207 | { | |
1208 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1209 | ||
772aebce | 1210 | irq_enter(); |
0ec53ecf | 1211 | #ifdef CONFIG_X86 |
38e20b07 | 1212 | exit_idle(); |
0ec53ecf | 1213 | #endif |
38e20b07 SY |
1214 | |
1215 | __xen_evtchn_do_upcall(); | |
1216 | ||
3445a8fd JF |
1217 | irq_exit(); |
1218 | set_irq_regs(old_regs); | |
38e20b07 | 1219 | } |
3445a8fd | 1220 | |
38e20b07 SY |
1221 | void xen_hvm_evtchn_do_upcall(void) |
1222 | { | |
1223 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1224 | } |
183d03cc | 1225 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1226 | |
eb1e305f JF |
1227 | /* Rebind a new event channel to an existing irq. */ |
1228 | void rebind_evtchn_irq(int evtchn, int irq) | |
1229 | { | |
d77bbd4d JF |
1230 | struct irq_info *info = info_for_irq(irq); |
1231 | ||
94032c50 KRW |
1232 | if (WARN_ON(!info)) |
1233 | return; | |
1234 | ||
eb1e305f JF |
1235 | /* Make sure the irq is masked, since the new event channel |
1236 | will also be masked. */ | |
1237 | disable_irq(irq); | |
1238 | ||
77365948 | 1239 | mutex_lock(&irq_mapping_update_lock); |
eb1e305f JF |
1240 | |
1241 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
d0b075ff | 1242 | BUG_ON(get_evtchn_to_irq(evtchn) != -1); |
eb1e305f | 1243 | /* Expect irq to have been bound before, |
d77bbd4d JF |
1244 | so there should be a proper type */ |
1245 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f | 1246 | |
96d4c588 | 1247 | (void)xen_irq_info_evtchn_setup(irq, evtchn); |
eb1e305f | 1248 | |
77365948 | 1249 | mutex_unlock(&irq_mapping_update_lock); |
eb1e305f JF |
1250 | |
1251 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1252 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1253 | |
1254 | /* Unmask the event channel. */ | |
1255 | enable_irq(irq); | |
1256 | } | |
1257 | ||
e46cdb66 | 1258 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1259 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1260 | { |
1261 | struct evtchn_bind_vcpu bind_vcpu; | |
1262 | int evtchn = evtchn_from_irq(irq); | |
4704fe4f | 1263 | int masked; |
e46cdb66 | 1264 | |
be49472f IC |
1265 | if (!VALID_EVTCHN(evtchn)) |
1266 | return -1; | |
1267 | ||
1268 | /* | |
1269 | * Events delivered via platform PCI interrupts are always | |
1270 | * routed to vcpu 0 and hence cannot be rebound. | |
1271 | */ | |
1272 | if (xen_hvm_domain() && !xen_have_vector_callback) | |
d5dedd45 | 1273 | return -1; |
e46cdb66 JF |
1274 | |
1275 | /* Send future instances of this interrupt to other vcpu. */ | |
1276 | bind_vcpu.port = evtchn; | |
1277 | bind_vcpu.vcpu = tcpu; | |
1278 | ||
4704fe4f DV |
1279 | /* |
1280 | * Mask the event while changing the VCPU binding to prevent | |
1281 | * it being delivered on an unexpected VCPU. | |
1282 | */ | |
3f70fa82 | 1283 | masked = test_and_set_mask(evtchn); |
4704fe4f | 1284 | |
e46cdb66 JF |
1285 | /* |
1286 | * If this fails, it usually just indicates that we're dealing with a | |
1287 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1288 | * it, but don't do the xenlinux-level rebind in that case. | |
1289 | */ | |
1290 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1291 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1292 | |
4704fe4f DV |
1293 | if (!masked) |
1294 | unmask_evtchn(evtchn); | |
1295 | ||
d5dedd45 YL |
1296 | return 0; |
1297 | } | |
e46cdb66 | 1298 | |
c9e265e0 TG |
1299 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1300 | bool force) | |
e46cdb66 | 1301 | { |
0de26520 | 1302 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 | 1303 | |
c9e265e0 | 1304 | return rebind_irq_to_cpu(data->irq, tcpu); |
e46cdb66 JF |
1305 | } |
1306 | ||
87295185 | 1307 | static int retrigger_evtchn(int evtchn) |
642e0c88 | 1308 | { |
87295185 | 1309 | int masked; |
642e0c88 IY |
1310 | |
1311 | if (!VALID_EVTCHN(evtchn)) | |
87295185 | 1312 | return 0; |
642e0c88 | 1313 | |
3f70fa82 | 1314 | masked = test_and_set_mask(evtchn); |
76ec8d64 | 1315 | set_evtchn(evtchn); |
642e0c88 IY |
1316 | if (!masked) |
1317 | unmask_evtchn(evtchn); | |
1318 | ||
1319 | return 1; | |
1320 | } | |
1321 | ||
87295185 DV |
1322 | int resend_irq_on_evtchn(unsigned int irq) |
1323 | { | |
1324 | return retrigger_evtchn(evtchn_from_irq(irq)); | |
1325 | } | |
1326 | ||
c9e265e0 | 1327 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1328 | { |
c9e265e0 | 1329 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1330 | |
1331 | if (VALID_EVTCHN(evtchn)) | |
1332 | unmask_evtchn(evtchn); | |
1333 | } | |
1334 | ||
c9e265e0 | 1335 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1336 | { |
c9e265e0 | 1337 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1338 | |
1339 | if (VALID_EVTCHN(evtchn)) | |
1340 | mask_evtchn(evtchn); | |
1341 | } | |
1342 | ||
c9e265e0 | 1343 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1344 | { |
c9e265e0 | 1345 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1346 | |
7e186bdd | 1347 | irq_move_irq(data); |
e46cdb66 JF |
1348 | |
1349 | if (VALID_EVTCHN(evtchn)) | |
7e186bdd SS |
1350 | clear_evtchn(evtchn); |
1351 | } | |
1352 | ||
1353 | static void mask_ack_dynirq(struct irq_data *data) | |
1354 | { | |
1355 | disable_dynirq(data); | |
1356 | ack_dynirq(data); | |
e46cdb66 JF |
1357 | } |
1358 | ||
c9e265e0 | 1359 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1360 | { |
87295185 | 1361 | return retrigger_evtchn(evtchn_from_irq(data->irq)); |
e46cdb66 JF |
1362 | } |
1363 | ||
0a85226f | 1364 | static void restore_pirqs(void) |
9a069c33 SS |
1365 | { |
1366 | int pirq, rc, irq, gsi; | |
1367 | struct physdev_map_pirq map_irq; | |
69c358ce | 1368 | struct irq_info *info; |
9a069c33 | 1369 | |
69c358ce IC |
1370 | list_for_each_entry(info, &xen_irq_list_head, list) { |
1371 | if (info->type != IRQT_PIRQ) | |
9a069c33 SS |
1372 | continue; |
1373 | ||
69c358ce IC |
1374 | pirq = info->u.pirq.pirq; |
1375 | gsi = info->u.pirq.gsi; | |
1376 | irq = info->irq; | |
1377 | ||
9a069c33 SS |
1378 | /* save/restore of PT devices doesn't work, so at this point the |
1379 | * only devices present are GSI based emulated devices */ | |
9a069c33 SS |
1380 | if (!gsi) |
1381 | continue; | |
1382 | ||
1383 | map_irq.domid = DOMID_SELF; | |
1384 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1385 | map_irq.index = gsi; | |
1386 | map_irq.pirq = pirq; | |
1387 | ||
1388 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1389 | if (rc) { | |
283c0972 JP |
1390 | pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", |
1391 | gsi, irq, pirq, rc); | |
9158c358 | 1392 | xen_free_irq(irq); |
9a069c33 SS |
1393 | continue; |
1394 | } | |
1395 | ||
1396 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1397 | ||
c9e265e0 | 1398 | __startup_pirq(irq); |
9a069c33 SS |
1399 | } |
1400 | } | |
1401 | ||
0e91398f JF |
1402 | static void restore_cpu_virqs(unsigned int cpu) |
1403 | { | |
1404 | struct evtchn_bind_virq bind_virq; | |
1405 | int virq, irq, evtchn; | |
1406 | ||
1407 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1408 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1409 | continue; | |
1410 | ||
ced40d0f | 1411 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1412 | |
1413 | /* Get a new binding from Xen. */ | |
1414 | bind_virq.virq = virq; | |
1415 | bind_virq.vcpu = cpu; | |
1416 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1417 | &bind_virq) != 0) | |
1418 | BUG(); | |
1419 | evtchn = bind_virq.port; | |
1420 | ||
1421 | /* Record the new mapping. */ | |
96d4c588 | 1422 | (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq); |
0e91398f | 1423 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1424 | } |
1425 | } | |
1426 | ||
1427 | static void restore_cpu_ipis(unsigned int cpu) | |
1428 | { | |
1429 | struct evtchn_bind_ipi bind_ipi; | |
1430 | int ipi, irq, evtchn; | |
1431 | ||
1432 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1433 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1434 | continue; | |
1435 | ||
ced40d0f | 1436 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1437 | |
1438 | /* Get a new binding from Xen. */ | |
1439 | bind_ipi.vcpu = cpu; | |
1440 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1441 | &bind_ipi) != 0) | |
1442 | BUG(); | |
1443 | evtchn = bind_ipi.port; | |
1444 | ||
1445 | /* Record the new mapping. */ | |
96d4c588 | 1446 | (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi); |
0e91398f | 1447 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1448 | } |
1449 | } | |
1450 | ||
2d9e1e2f JF |
1451 | /* Clear an irq's pending state, in preparation for polling on it */ |
1452 | void xen_clear_irq_pending(int irq) | |
1453 | { | |
1454 | int evtchn = evtchn_from_irq(irq); | |
1455 | ||
1456 | if (VALID_EVTCHN(evtchn)) | |
1457 | clear_evtchn(evtchn); | |
1458 | } | |
d9a8814f | 1459 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1460 | void xen_set_irq_pending(int irq) |
1461 | { | |
1462 | int evtchn = evtchn_from_irq(irq); | |
1463 | ||
1464 | if (VALID_EVTCHN(evtchn)) | |
1465 | set_evtchn(evtchn); | |
1466 | } | |
1467 | ||
1468 | bool xen_test_irq_pending(int irq) | |
1469 | { | |
1470 | int evtchn = evtchn_from_irq(irq); | |
1471 | bool ret = false; | |
1472 | ||
1473 | if (VALID_EVTCHN(evtchn)) | |
1474 | ret = test_evtchn(evtchn); | |
1475 | ||
1476 | return ret; | |
1477 | } | |
1478 | ||
d9a8814f KRW |
1479 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1480 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1481 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1482 | { |
1483 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1484 | ||
1485 | if (VALID_EVTCHN(evtchn)) { | |
1486 | struct sched_poll poll; | |
1487 | ||
1488 | poll.nr_ports = 1; | |
d9a8814f | 1489 | poll.timeout = timeout; |
ff3c5362 | 1490 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1491 | |
1492 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1493 | BUG(); | |
1494 | } | |
1495 | } | |
d9a8814f KRW |
1496 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1497 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1498 | * irq will be disabled so it won't deliver an interrupt. */ | |
1499 | void xen_poll_irq(int irq) | |
1500 | { | |
1501 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1502 | } | |
2d9e1e2f | 1503 | |
c7c2c3a2 KRW |
1504 | /* Check whether the IRQ line is shared with other guests. */ |
1505 | int xen_test_irq_shared(int irq) | |
1506 | { | |
1507 | struct irq_info *info = info_for_irq(irq); | |
94032c50 KRW |
1508 | struct physdev_irq_status_query irq_status; |
1509 | ||
1510 | if (WARN_ON(!info)) | |
1511 | return -ENOENT; | |
1512 | ||
1513 | irq_status.irq = info->u.pirq.pirq; | |
c7c2c3a2 KRW |
1514 | |
1515 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) | |
1516 | return 0; | |
1517 | return !(irq_status.flags & XENIRQSTAT_shared); | |
1518 | } | |
1519 | EXPORT_SYMBOL_GPL(xen_test_irq_shared); | |
1520 | ||
0e91398f JF |
1521 | void xen_irq_resume(void) |
1522 | { | |
6cb6537d IC |
1523 | unsigned int cpu, evtchn; |
1524 | struct irq_info *info; | |
0e91398f | 1525 | |
0e91398f | 1526 | /* New event-channel space is not 'live' yet. */ |
d0b075ff | 1527 | for (evtchn = 0; evtchn < xen_evtchn_nr_channels(); evtchn++) |
0e91398f JF |
1528 | mask_evtchn(evtchn); |
1529 | ||
1530 | /* No IRQ <-> event-channel mappings. */ | |
6cb6537d IC |
1531 | list_for_each_entry(info, &xen_irq_list_head, list) |
1532 | info->evtchn = 0; /* zap event-channel binding */ | |
0e91398f | 1533 | |
d0b075ff | 1534 | clear_evtchn_to_irq_all(); |
0e91398f JF |
1535 | |
1536 | for_each_possible_cpu(cpu) { | |
1537 | restore_cpu_virqs(cpu); | |
1538 | restore_cpu_ipis(cpu); | |
1539 | } | |
6903591f | 1540 | |
0a85226f | 1541 | restore_pirqs(); |
0e91398f JF |
1542 | } |
1543 | ||
e46cdb66 | 1544 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1545 | .name = "xen-dyn", |
54a353a0 | 1546 | |
c9e265e0 TG |
1547 | .irq_disable = disable_dynirq, |
1548 | .irq_mask = disable_dynirq, | |
1549 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1550 | |
7e186bdd SS |
1551 | .irq_ack = ack_dynirq, |
1552 | .irq_mask_ack = mask_ack_dynirq, | |
1553 | ||
c9e265e0 TG |
1554 | .irq_set_affinity = set_affinity_irq, |
1555 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1556 | }; |
1557 | ||
d46a78b0 | 1558 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1559 | .name = "xen-pirq", |
d46a78b0 | 1560 | |
c9e265e0 TG |
1561 | .irq_startup = startup_pirq, |
1562 | .irq_shutdown = shutdown_pirq, | |
c9e265e0 | 1563 | .irq_enable = enable_pirq, |
c9e265e0 | 1564 | .irq_disable = disable_pirq, |
d46a78b0 | 1565 | |
7e186bdd SS |
1566 | .irq_mask = disable_dynirq, |
1567 | .irq_unmask = enable_dynirq, | |
1568 | ||
1569 | .irq_ack = eoi_pirq, | |
1570 | .irq_eoi = eoi_pirq, | |
1571 | .irq_mask_ack = mask_ack_pirq, | |
d46a78b0 | 1572 | |
c9e265e0 | 1573 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1574 | |
c9e265e0 | 1575 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1576 | }; |
1577 | ||
aaca4964 | 1578 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1579 | .name = "xen-percpu", |
aaca4964 | 1580 | |
c9e265e0 TG |
1581 | .irq_disable = disable_dynirq, |
1582 | .irq_mask = disable_dynirq, | |
1583 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1584 | |
c9e265e0 | 1585 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1586 | }; |
1587 | ||
38e20b07 SY |
1588 | int xen_set_callback_via(uint64_t via) |
1589 | { | |
1590 | struct xen_hvm_param a; | |
1591 | a.domid = DOMID_SELF; | |
1592 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1593 | a.value = via; | |
1594 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1595 | } | |
1596 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1597 | ||
ca65f9fc | 1598 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1599 | /* Vector callbacks are better than PCI interrupts to receive event |
1600 | * channel notifications because we can receive vector callbacks on any | |
1601 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1602 | void xen_callback_vector(void) | |
1603 | { | |
1604 | int rc; | |
1605 | uint64_t callback_via; | |
1606 | if (xen_have_vector_callback) { | |
bc2b0331 | 1607 | callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR); |
38e20b07 SY |
1608 | rc = xen_set_callback_via(callback_via); |
1609 | if (rc) { | |
283c0972 | 1610 | pr_err("Request for Xen HVM callback vector failed\n"); |
38e20b07 SY |
1611 | xen_have_vector_callback = 0; |
1612 | return; | |
1613 | } | |
283c0972 | 1614 | pr_info("Xen HVM callback vector for event delivery is enabled\n"); |
38e20b07 | 1615 | /* in the restore case the vector has already been allocated */ |
bc2b0331 S |
1616 | if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) |
1617 | alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, | |
1618 | xen_hvm_callback_vector); | |
38e20b07 SY |
1619 | } |
1620 | } | |
ca65f9fc SS |
1621 | #else |
1622 | void xen_callback_vector(void) {} | |
1623 | #endif | |
38e20b07 | 1624 | |
2e3d8860 | 1625 | void __init xen_init_IRQ(void) |
e46cdb66 | 1626 | { |
0ec53ecf | 1627 | int i; |
c7a3589e | 1628 | |
ab9a1cca DV |
1629 | xen_evtchn_2l_init(); |
1630 | ||
d0b075ff DV |
1631 | evtchn_to_irq = kcalloc(EVTCHN_ROW(xen_evtchn_max_channels()), |
1632 | sizeof(*evtchn_to_irq), GFP_KERNEL); | |
9d093e29 | 1633 | BUG_ON(!evtchn_to_irq); |
e46cdb66 | 1634 | |
e46cdb66 | 1635 | /* No event channels are 'live' right now. */ |
d0b075ff | 1636 | for (i = 0; i < xen_evtchn_nr_channels(); i++) |
e46cdb66 JF |
1637 | mask_evtchn(i); |
1638 | ||
9846ff10 SS |
1639 | pirq_needs_eoi = pirq_needs_eoi_flag; |
1640 | ||
0ec53ecf | 1641 | #ifdef CONFIG_X86 |
38e20b07 SY |
1642 | if (xen_hvm_domain()) { |
1643 | xen_callback_vector(); | |
1644 | native_init_IRQ(); | |
3942b740 SS |
1645 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1646 | * __acpi_register_gsi can point at the right function */ | |
1647 | pci_xen_hvm_init(); | |
38e20b07 | 1648 | } else { |
0ec53ecf | 1649 | int rc; |
9846ff10 SS |
1650 | struct physdev_pirq_eoi_gmfn eoi_gmfn; |
1651 | ||
38e20b07 | 1652 | irq_ctx_init(smp_processor_id()); |
38aa66fc | 1653 | if (xen_initial_domain()) |
a0ee0567 | 1654 | pci_xen_initial_domain(); |
9846ff10 SS |
1655 | |
1656 | pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO); | |
1657 | eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map); | |
1658 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn); | |
1659 | if (rc != 0) { | |
1660 | free_page((unsigned long) pirq_eoi_map); | |
1661 | pirq_eoi_map = NULL; | |
1662 | } else | |
1663 | pirq_needs_eoi = pirq_check_eoi_map; | |
38e20b07 | 1664 | } |
0ec53ecf | 1665 | #endif |
e46cdb66 | 1666 | } |