Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0e94f2ee VD |
2 | * w83627hf/thf WDT driver |
3 | * | |
30a83695 GR |
4 | * (c) Copyright 2013 Guenter Roeck |
5 | * converted to watchdog infrastructure | |
6 | * | |
0e94f2ee VD |
7 | * (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com> |
8 | * added support for W83627THF. | |
1da177e4 | 9 | * |
d36b6910 | 10 | * (c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com> |
1da177e4 LT |
11 | * |
12 | * Based on advantechwdt.c which is based on wdt.c. | |
13 | * Original copyright messages: | |
14 | * | |
15 | * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl> | |
16 | * | |
29fa0586 AC |
17 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>, |
18 | * All Rights Reserved. | |
1da177e4 LT |
19 | * |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License | |
22 | * as published by the Free Software Foundation; either version | |
23 | * 2 of the License, or (at your option) any later version. | |
24 | * | |
25 | * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide | |
26 | * warranty for any of this software. This material is provided | |
27 | * "AS-IS" and at no charge. | |
28 | * | |
29fa0586 | 29 | * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
30 | */ |
31 | ||
27c766aa JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/types.h> | |
1da177e4 | 37 | #include <linux/watchdog.h> |
1da177e4 | 38 | #include <linux/ioport.h> |
1da177e4 | 39 | #include <linux/init.h> |
46a3949d | 40 | #include <linux/io.h> |
1da177e4 | 41 | |
9c67bea4 | 42 | #define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT" |
1da177e4 LT |
43 | #define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */ |
44 | ||
962c04f5 | 45 | static int wdt_io; |
7b6d0b6a GR |
46 | static int cr_wdt_timeout; /* WDT timeout register */ |
47 | static int cr_wdt_control; /* WDT control register */ | |
33f74b89 | 48 | static int cr_wdt_csr; /* WDT control & status register */ |
962c04f5 | 49 | |
7b6d0b6a GR |
50 | enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf, |
51 | w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p, | |
3a9aedb2 GR |
52 | w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793, |
53 | nct6795, nct6102 }; | |
1da177e4 | 54 | |
30a83695 | 55 | static int timeout; /* in seconds */ |
1da177e4 | 56 | module_param(timeout, int, 0); |
46a3949d AC |
57 | MODULE_PARM_DESC(timeout, |
58 | "Watchdog timeout in seconds. 1 <= timeout <= 255, default=" | |
59 | __MODULE_STRING(WATCHDOG_TIMEOUT) "."); | |
1da177e4 | 60 | |
86a1e189 WVS |
61 | static bool nowayout = WATCHDOG_NOWAYOUT; |
62 | module_param(nowayout, bool, 0); | |
46a3949d AC |
63 | MODULE_PARM_DESC(nowayout, |
64 | "Watchdog cannot be stopped once started (default=" | |
65 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
1da177e4 | 66 | |
be281588 GR |
67 | static int early_disable; |
68 | module_param(early_disable, int, 0); | |
69 | MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)"); | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * Kernel methods. | |
73 | */ | |
74 | ||
75 | #define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */ | |
46a3949d AC |
76 | #define WDT_EFIR (wdt_io+0) /* Extended Function Index Register |
77 | (same as EFER) */ | |
1da177e4 LT |
78 | #define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */ |
79 | ||
ef0c1a6b GR |
80 | #define W83627HF_LD_WDT 0x08 |
81 | ||
962c04f5 GR |
82 | #define W83627HF_ID 0x52 |
83 | #define W83627S_ID 0x59 | |
7b6d0b6a GR |
84 | #define W83697HF_ID 0x60 |
85 | #define W83697UG_ID 0x68 | |
962c04f5 GR |
86 | #define W83637HF_ID 0x70 |
87 | #define W83627THF_ID 0x82 | |
88 | #define W83687THF_ID 0x85 | |
89 | #define W83627EHF_ID 0x88 | |
90 | #define W83627DHG_ID 0xa0 | |
91 | #define W83627UHG_ID 0xa2 | |
92 | #define W83667HG_ID 0xa5 | |
93 | #define W83627DHG_P_ID 0xb0 | |
94 | #define W83667HG_B_ID 0xb3 | |
95 | #define NCT6775_ID 0xb4 | |
96 | #define NCT6776_ID 0xc3 | |
33f74b89 | 97 | #define NCT6102_ID 0xc4 |
962c04f5 | 98 | #define NCT6779_ID 0xc5 |
a77841d5 GR |
99 | #define NCT6791_ID 0xc8 |
100 | #define NCT6792_ID 0xc9 | |
3a9aedb2 GR |
101 | #define NCT6793_ID 0xd1 |
102 | #define NCT6795_ID 0xd3 | |
962c04f5 | 103 | |
7b6d0b6a GR |
104 | #define W83627HF_WDT_TIMEOUT 0xf6 |
105 | #define W83697HF_WDT_TIMEOUT 0xf4 | |
33f74b89 | 106 | #define NCT6102D_WDT_TIMEOUT 0xf1 |
7b6d0b6a GR |
107 | |
108 | #define W83627HF_WDT_CONTROL 0xf5 | |
109 | #define W83697HF_WDT_CONTROL 0xf3 | |
33f74b89 RK |
110 | #define NCT6102D_WDT_CONTROL 0xf0 |
111 | ||
112 | #define W836X7HF_WDT_CSR 0xf7 | |
113 | #define NCT6102D_WDT_CSR 0xf2 | |
7b6d0b6a | 114 | |
ef0c1a6b GR |
115 | static void superio_outb(int reg, int val) |
116 | { | |
117 | outb(reg, WDT_EFER); | |
118 | outb(val, WDT_EFDR); | |
119 | } | |
120 | ||
121 | static inline int superio_inb(int reg) | |
122 | { | |
123 | outb(reg, WDT_EFER); | |
124 | return inb(WDT_EFDR); | |
125 | } | |
126 | ||
127 | static int superio_enter(void) | |
1da177e4 | 128 | { |
ef0c1a6b GR |
129 | if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME)) |
130 | return -EBUSY; | |
131 | ||
1da177e4 LT |
132 | outb_p(0x87, WDT_EFER); /* Enter extended function mode */ |
133 | outb_p(0x87, WDT_EFER); /* Again according to manual */ | |
ef0c1a6b GR |
134 | |
135 | return 0; | |
1da177e4 LT |
136 | } |
137 | ||
ef0c1a6b GR |
138 | static void superio_select(int ld) |
139 | { | |
140 | superio_outb(0x07, ld); | |
141 | } | |
142 | ||
143 | static void superio_exit(void) | |
1da177e4 LT |
144 | { |
145 | outb_p(0xAA, WDT_EFER); /* Leave extended function mode */ | |
ef0c1a6b | 146 | release_region(wdt_io, 2); |
1da177e4 LT |
147 | } |
148 | ||
962c04f5 | 149 | static int w83627hf_init(struct watchdog_device *wdog, enum chips chip) |
1da177e4 | 150 | { |
ef0c1a6b | 151 | int ret; |
1da177e4 LT |
152 | unsigned char t; |
153 | ||
ef0c1a6b GR |
154 | ret = superio_enter(); |
155 | if (ret) | |
156 | return ret; | |
1da177e4 | 157 | |
ef0c1a6b | 158 | superio_select(W83627HF_LD_WDT); |
8f526389 | 159 | |
ef0c1a6b GR |
160 | /* set CR30 bit 0 to activate GPIO2 */ |
161 | t = superio_inb(0x30); | |
ac461103 | 162 | if (!(t & 0x01)) |
ef0c1a6b | 163 | superio_outb(0x30, t | 0x01); |
8f526389 | 164 | |
962c04f5 GR |
165 | switch (chip) { |
166 | case w83627hf: | |
167 | case w83627s: | |
168 | t = superio_inb(0x2B) & ~0x10; | |
169 | superio_outb(0x2B, t); /* set GPIO24 to WDT0 */ | |
170 | break; | |
7b6d0b6a GR |
171 | case w83697hf: |
172 | /* Set pin 119 to WDTO# mode (= CR29, WDT0) */ | |
173 | t = superio_inb(0x29) & ~0x60; | |
174 | t |= 0x20; | |
175 | superio_outb(0x29, t); | |
176 | break; | |
177 | case w83697ug: | |
178 | /* Set pin 118 to WDTO# mode */ | |
179 | t = superio_inb(0x2b) & ~0x04; | |
180 | superio_outb(0x2b, t); | |
181 | break; | |
962c04f5 GR |
182 | case w83627thf: |
183 | t = (superio_inb(0x2B) & ~0x08) | 0x04; | |
184 | superio_outb(0x2B, t); /* set GPIO3 to WDT0 */ | |
185 | break; | |
186 | case w83627dhg: | |
187 | case w83627dhg_p: | |
188 | t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */ | |
189 | superio_outb(0x2D, t); /* set GPIO5 to WDT0 */ | |
7b6d0b6a | 190 | t = superio_inb(cr_wdt_control); |
962c04f5 GR |
191 | t |= 0x02; /* enable the WDTO# output low pulse |
192 | * to the KBRST# pin */ | |
7b6d0b6a | 193 | superio_outb(cr_wdt_control, t); |
962c04f5 GR |
194 | break; |
195 | case w83637hf: | |
196 | break; | |
197 | case w83687thf: | |
198 | t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */ | |
199 | superio_outb(0x2C, t); | |
200 | break; | |
201 | case w83627ehf: | |
202 | case w83627uhg: | |
203 | case w83667hg: | |
204 | case w83667hg_b: | |
205 | case nct6775: | |
206 | case nct6776: | |
207 | case nct6779: | |
a77841d5 GR |
208 | case nct6791: |
209 | case nct6792: | |
3a9aedb2 GR |
210 | case nct6793: |
211 | case nct6795: | |
33f74b89 | 212 | case nct6102: |
962c04f5 GR |
213 | /* |
214 | * These chips have a fixed WDTO# output pin (W83627UHG), | |
215 | * or support more than one WDTO# output pin. | |
216 | * Don't touch its configuration, and hope the BIOS | |
217 | * does the right thing. | |
218 | */ | |
7b6d0b6a | 219 | t = superio_inb(cr_wdt_control); |
962c04f5 GR |
220 | t |= 0x02; /* enable the WDTO# output low pulse |
221 | * to the KBRST# pin */ | |
7b6d0b6a | 222 | superio_outb(cr_wdt_control, t); |
962c04f5 GR |
223 | break; |
224 | default: | |
225 | break; | |
226 | } | |
227 | ||
7b6d0b6a | 228 | t = superio_inb(cr_wdt_timeout); |
93642ecd | 229 | if (t != 0) { |
be281588 GR |
230 | if (early_disable) { |
231 | pr_warn("Stopping previously enabled watchdog until userland kicks in\n"); | |
232 | superio_outb(cr_wdt_timeout, 0); | |
233 | } else { | |
234 | pr_info("Watchdog already running. Resetting timeout to %d sec\n", | |
235 | wdog->timeout); | |
236 | superio_outb(cr_wdt_timeout, wdog->timeout); | |
237 | } | |
93642ecd | 238 | } |