[linux-block.git] / drivers / watchdog / w83627hf_wdt.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *	w83627hf/thf WDT driver
 *
 *	(c) Copyright 2013 Guenter Roeck
 *		converted to watchdog infrastructure
 *
 *	(c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
 *		added support for W83627THF.
 *
 *	(c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com>
 *
 *	Based on advantechwdt.c which is based on wdt.c.
 *	Original copyright messages:
 *
 *	(c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
 *
 *	(c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
 *						All Rights Reserved.
 *
 *	Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
 *	warranty for any of this software. This material is provided
 *	"AS-IS" and at no charge.
 *
 *	(c) Copyright 1995    Alan Cox <alan@lxorguk.ukuu.org.uk>
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/dmi.h>

#define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT"
#define WATCHDOG_TIMEOUT 60		/* 60 sec default timeout */

static int wdt_io;
static int cr_wdt_timeout;	/* WDT timeout register */
static int cr_wdt_control;	/* WDT control register */
static int cr_wdt_csr;		/* WDT control & status register */
static int wdt_cfg_enter = 0x87;/* key to unlock configuration space */
static int wdt_cfg_leave = 0xAA;/* key to lock configuration space */

enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
	     w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
	     w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
	     nct6795, nct6796, nct6102, nct6116 };

static int timeout;			/* in seconds */
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout,
		"Watchdog timeout in seconds. 1 <= timeout <= 255, default="
				__MODULE_STRING(WATCHDOG_TIMEOUT) ".");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
		"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static int early_disable;
module_param(early_disable, int, 0);
MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)");

/*
 *	Kernel methods.
 */

#define WDT_EFER (wdt_io+0)   /* Extended Function Enable Registers */
#define WDT_EFIR (wdt_io+0)   /* Extended Function Index Register
							(same as EFER) */
#define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */

#define W83627HF_LD_WDT		0x08

#define W83627HF_ID		0x52
#define W83627S_ID		0x59
#define W83697HF_ID		0x60
#define W83697UG_ID		0x68
#define W83637HF_ID		0x70
#define W83627THF_ID		0x82
#define W83687THF_ID		0x85
#define W83627EHF_ID		0x88
#define W83627DHG_ID		0xa0
#define W83627UHG_ID		0xa2
#define W83667HG_ID		0xa5
#define W83627DHG_P_ID		0xb0
#define W83667HG_B_ID		0xb3
#define NCT6775_ID		0xb4
#define NCT6776_ID		0xc3
#define NCT6102_ID		0xc4
#define NCT6116_ID		0xd2
#define NCT6779_ID		0xc5
#define NCT6791_ID		0xc8
#define NCT6792_ID		0xc9
#define NCT6793_ID		0xd1
#define NCT6795_ID		0xd3
#define NCT6796_ID		0xd4	/* also NCT9697D, NCT9698D */

#define W83627HF_WDT_TIMEOUT	0xf6
#define W83697HF_WDT_TIMEOUT	0xf4
#define NCT6102D_WDT_TIMEOUT	0xf1

#define W83627HF_WDT_CONTROL	0xf5
#define W83697HF_WDT_CONTROL	0xf3
#define NCT6102D_WDT_CONTROL	0xf0

#define W836X7HF_WDT_CSR	0xf7
#define NCT6102D_WDT_CSR	0xf2

#define WDT_CSR_STATUS		0x10
#define WDT_CSR_KBD		0x40
#define WDT_CSR_MOUSE		0x80

static void superio_outb(int reg, int val)
{
	outb(reg, WDT_EFER);
	outb(val, WDT_EFDR);
}

static inline int superio_inb(int reg)
{
	outb(reg, WDT_EFER);
	return inb(WDT_EFDR);
}

static int superio_enter(void)
{
	if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME))
		return -EBUSY;

	outb_p(wdt_cfg_enter, WDT_EFER); /* Enter extended function mode */
	outb_p(wdt_cfg_enter, WDT_EFER); /* Again according to manual */

	return 0;
}

static void superio_select(int ld)
{
	superio_outb(0x07, ld);
}

static void superio_exit(void)
{
	outb_p(wdt_cfg_leave, WDT_EFER); /* Leave extended function mode */
	release_region(wdt_io, 2);
}

static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
{
	int ret;
	unsigned char t;

	ret = superio_enter();
	if (ret)
		return ret;

	superio_select(W83627HF_LD_WDT);

	/* set CR30 bit 0 to activate GPIO2 */
	t = superio_inb(0x30);
	if (!(t & 0x01))
		superio_outb(0x30, t | 0x01);

	switch (chip) {
	case w83627hf:
	case w83627s:
		t = superio_inb(0x2B) & ~0x10;
		superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
		break;
	case w83697hf:
		/* Set pin 119 to WDTO# mode (= CR29, WDT0) */
		t = superio_inb(0x29) & ~0x60;
		t |= 0x20;
		superio_outb(0x29, t);
		break;
	case w83697ug:
		/* Set pin 118 to WDTO# mode */
		t = superio_inb(0x2b) & ~0x04;
		superio_outb(0x2b, t);
		break;
	case w83627thf:
		t = (superio_inb(0x2B) & ~0x08) | 0x04;
		superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
		break;
	case w83627dhg:
	case w83627dhg_p:
		t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
		superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
		t = superio_inb(cr_wdt_control);
		t |= 0x02;	/* enable the WDTO# output low pulse
				 * to the KBRST# pin */
		superio_outb(cr_wdt_control, t);
		break;
	case w83637hf:
		break;
	case w83687thf:
		t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */
		superio_outb(0x2C, t);
		break;
	case w83627ehf:
	case w83627uhg:
	case w83667hg:
	case w83667hg_b:
	case nct6775:
	case nct6776:
	case nct6779:
	case nct6791:
	case nct6792:
	case nct6793:
	case nct6795:
	case nct6796:
	case nct6102:
	case nct6116:
		/*
		 * These chips have a fixed WDTO# output pin (W83627UHG),
		 * or support more than one WDTO# output pin.
		 * Don't touch its configuration, and hope the BIOS
		 * does the right thing.
		 */
		t = superio_inb(cr_wdt_control);
		t |= 0x02;	/* enable the WDTO# output low pulse
				 * to the KBRST# pin */
		superio_outb(cr_wdt_control, t);
		break;
	default:
		break;
	}

	t = superio_inb(cr_wdt_timeout);
	if (t != 0) {
		if (early_disable) {
			pr_warn("Stopping previously enabled watchdog until userland kicks in\n");
			superio_outb(cr_wdt_timeout, 0);
		} else {
			pr_info("Watchdog already running. Resetting timeout to %d sec\n",
				wdog->timeout);
			superio_outb(cr_wdt_timeout, wdog->timeout);
		}
	}
Commit	Line	Data
d0173278	1	// SPDX-License-Identifier: GPL-2.0+
1da177e4	2	/*
0e94f2ee VD	3	* w83627hf/thf WDT driver
0e94f2ee VD	4	*
30a83695 GR	5	* (c) Copyright 2013 Guenter Roeck
	6	* converted to watchdog infrastructure
	7	*
0e94f2ee VD	8	* (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
0e94f2ee VD	9	* added support for W83627THF.
1da177e4	10	*
d36b6910	11	* (c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com>
1da177e4 LT	12	*
	13	* Based on advantechwdt.c which is based on wdt.c.
	14	* Original copyright messages:
	15	*
	16	* (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
	17	*
29fa0586 AC	18	* (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
29fa0586 AC	19	* All Rights Reserved.
1da177e4	20	*
1da177e4 LT	21	* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
	22	* warranty for any of this software. This material is provided
	23	* "AS-IS" and at no charge.
	24	*
29fa0586	25	* (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4 LT	26	*/
1da177e4 LT	27
27c766aa JP	28	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	29
1da177e4 LT	30	#include <linux/module.h>
	31	#include <linux/moduleparam.h>
	32	#include <linux/types.h>
1da177e4	33	#include <linux/watchdog.h>
1da177e4	34	#include <linux/ioport.h>
1da177e4	35	#include <linux/init.h>
46a3949d	36	#include <linux/io.h>
31eb42bd	37	#include <linux/dmi.h>
1da177e4	38
9c67bea4	39	#define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT"
1da177e4 LT	40	#define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
1da177e4 LT	41
962c04f5	42	static int wdt_io;
7b6d0b6a GR	43	static int cr_wdt_timeout; /* WDT timeout register */
7b6d0b6a GR	44	static int cr_wdt_control; /* WDT control register */
33f74b89	45	static int cr_wdt_csr; /* WDT control & status register */
31eb42bd JD	46	static int wdt_cfg_enter = 0x87;/* key to unlock configuration space */
31eb42bd JD	47	static int wdt_cfg_leave = 0xAA;/* key to lock configuration space */
962c04f5	48
7b6d0b6a GR	49	enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
7b6d0b6a GR	50	w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
3a9aedb2	51	w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
e11cfc69	52	nct6795, nct6796, nct6102, nct6116 };
1da177e4	53
30a83695	54	static int timeout; /* in seconds */
1da177e4	55	module_param(timeout, int, 0);
46a3949d AC	56	MODULE_PARM_DESC(timeout,
	57	"Watchdog timeout in seconds. 1 <= timeout <= 255, default="
	58	__MODULE_STRING(WATCHDOG_TIMEOUT) ".");
1da177e4	59
86a1e189 WVS	60	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	61	module_param(nowayout, bool, 0);
46a3949d AC	62	MODULE_PARM_DESC(nowayout,
	63	"Watchdog cannot be stopped once started (default="
	64	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
1da177e4	65
be281588 GR	66	static int early_disable;
	67	module_param(early_disable, int, 0);
	68	MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)");
	69
1da177e4 LT	70	/*
	71	* Kernel methods.
	72	*/
	73
	74	#define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */
46a3949d AC	75	#define WDT_EFIR (wdt_io+0) /* Extended Function Index Register
46a3949d AC	76	(same as EFER) */
1da177e4 LT	77	#define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */
1da177e4 LT	78
ef0c1a6b GR	79	#define W83627HF_LD_WDT 0x08
ef0c1a6b GR	80
962c04f5 GR	81	#define W83627HF_ID 0x52
962c04f5 GR	82	#define W83627S_ID 0x59
7b6d0b6a GR	83	#define W83697HF_ID 0x60
7b6d0b6a GR	84	#define W83697UG_ID 0x68
962c04f5 GR	85	#define W83637HF_ID 0x70
	86	#define W83627THF_ID 0x82
	87	#define W83687THF_ID 0x85
	88	#define W83627EHF_ID 0x88
	89	#define W83627DHG_ID 0xa0
	90	#define W83627UHG_ID 0xa2
	91	#define W83667HG_ID 0xa5
	92	#define W83627DHG_P_ID 0xb0
	93	#define W83667HG_B_ID 0xb3
	94	#define NCT6775_ID 0xb4
	95	#define NCT6776_ID 0xc3
33f74b89	96	#define NCT6102_ID 0xc4
e11cfc69	97	#define NCT6116_ID 0xd2
962c04f5	98	#define NCT6779_ID 0xc5
a77841d5 GR	99	#define NCT6791_ID 0xc8
a77841d5 GR	100	#define NCT6792_ID 0xc9
3a9aedb2 GR	101	#define NCT6793_ID 0xd1
3a9aedb2 GR	102	#define NCT6795_ID 0xd3
57cbf0e3	103	#define NCT6796_ID 0xd4 /* also NCT9697D, NCT9698D */
962c04f5	104
7b6d0b6a GR	105	#define W83627HF_WDT_TIMEOUT 0xf6
7b6d0b6a GR	106	#define W83697HF_WDT_TIMEOUT 0xf4
33f74b89	107	#define NCT6102D_WDT_TIMEOUT 0xf1
7b6d0b6a GR	108
	109	#define W83627HF_WDT_CONTROL 0xf5
	110	#define W83697HF_WDT_CONTROL 0xf3
33f74b89 RK	111	#define NCT6102D_WDT_CONTROL 0xf0
	112
	113	#define W836X7HF_WDT_CSR 0xf7
	114	#define NCT6102D_WDT_CSR 0xf2
7b6d0b6a	115
5a9fbf8b HS	116	#define WDT_CSR_STATUS 0x10
	117	#define WDT_CSR_KBD 0x40
	118	#define WDT_CSR_MOUSE 0x80
	119
ef0c1a6b GR	120	static void superio_outb(int reg, int val)
	121	{
	122	outb(reg, WDT_EFER);
	123	outb(val, WDT_EFDR);
	124	}
	125
	126	static inline int superio_inb(int reg)
	127	{
	128	outb(reg, WDT_EFER);
	129	return inb(WDT_EFDR);
	130	}
	131
	132	static int superio_enter(void)
1da177e4	133	{
ef0c1a6b GR	134	if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME))
	135	return -EBUSY;
	136
31eb42bd JD	137	outb_p(wdt_cfg_enter, WDT_EFER); /* Enter extended function mode */
31eb42bd JD	138	outb_p(wdt_cfg_enter, WDT_EFER); /* Again according to manual */
ef0c1a6b GR	139
ef0c1a6b GR	140	return 0;
1da177e4 LT	141	}
1da177e4 LT	142
ef0c1a6b GR	143	static void superio_select(int ld)
	144	{
	145	superio_outb(0x07, ld);
	146	}
	147
	148	static void superio_exit(void)
1da177e4	149	{
31eb42bd	150	outb_p(wdt_cfg_leave, WDT_EFER); /* Leave extended function mode */
ef0c1a6b	151	release_region(wdt_io, 2);
1da177e4 LT	152	}
1da177e4 LT	153
962c04f5	154	static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
1da177e4	155	{
ef0c1a6b	156	int ret;
1da177e4 LT	157	unsigned char t;
1da177e4 LT	158
ef0c1a6b GR	159	ret = superio_enter();
	160	if (ret)
	161	return ret;
1da177e4	162
ef0c1a6b	163	superio_select(W83627HF_LD_WDT);
8f526389	164
ef0c1a6b GR	165	/* set CR30 bit 0 to activate GPIO2 */
ef0c1a6b GR	166	t = superio_inb(0x30);
ac461103	167	if (!(t & 0x01))
ef0c1a6b	168	superio_outb(0x30, t \| 0x01);
8f526389	169
962c04f5 GR	170	switch (chip) {
	171	case w83627hf:
	172	case w83627s:
	173	t = superio_inb(0x2B) & ~0x10;
	174	superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
	175	break;
7b6d0b6a GR	176	case w83697hf:
	177	/* Set pin 119 to WDTO# mode (= CR29, WDT0) */
	178	t = superio_inb(0x29) & ~0x60;
	179	t \|= 0x20;
	180	superio_outb(0x29, t);
	181	break;
	182	case w83697ug:
	183	/* Set pin 118 to WDTO# mode */
	184	t = superio_inb(0x2b) & ~0x04;
	185	superio_outb(0x2b, t);
	186	break;
962c04f5 GR	187	case w83627thf:
	188	t = (superio_inb(0x2B) & ~0x08) \| 0x04;
	189	superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
	190	break;
	191	case w83627dhg:
	192	case w83627dhg_p:
	193	t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
	194	superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
7b6d0b6a	195	t = superio_inb(cr_wdt_control);
962c04f5 GR	196	t \|= 0x02; /* enable the WDTO# output low pulse
962c04f5 GR	197	* to the KBRST# pin */
7b6d0b6a	198	superio_outb(cr_wdt_control, t);
962c04f5 GR	199	break;
	200	case w83637hf:
	201	break;
	202	case w83687thf:
	203	t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */
	204	superio_outb(0x2C, t);
	205	break;
	206	case w83627ehf:
	207	case w83627uhg:
	208	case w83667hg:
	209	case w83667hg_b:
	210	case nct6775:
	211	case nct6776:
	212	case nct6779:
a77841d5 GR	213	case nct6791:
a77841d5 GR	214	case nct6792:
3a9aedb2 GR	215	case nct6793:
3a9aedb2 GR	216	case nct6795:
57cbf0e3	217	case nct6796:
33f74b89	218	case nct6102:
e11cfc69	219	case nct6116:
962c04f5 GR	220	/*
	221	* These chips have a fixed WDTO# output pin (W83627UHG),
	222	* or support more than one WDTO# output pin.
	223	* Don't touch its configuration, and hope the BIOS
	224	* does the right thing.
	225	*/
7b6d0b6a	226	t = superio_inb(cr_wdt_control);
962c04f5 GR	227	t \|= 0x02; /* enable the WDTO# output low pulse
962c04f5 GR	228	* to the KBRST# pin */
7b6d0b6a	229	superio_outb(cr_wdt_control, t);
962c04f5 GR	230	break;
	231	default:
	232	break;
	233	}
	234
7b6d0b6a	235	t = superio_inb(cr_wdt_timeout);
93642ecd	236	if (t != 0) {
be281588 GR	237	if (early_disable) {
	238	pr_warn("Stopping previously enabled watchdog until userland kicks in\n");
	239	superio_outb(cr_wdt_timeout, 0);
	240	} else {
	241	pr_info("Watchdog already running. Resetting timeout to %d sec\n",
	242	wdog->timeout);
	243	superio_outb(cr_wdt_timeout, wdog->timeout);
	244	}
93642ecd	245	}