Merge existing fixes from regulator/for-5.9
[linux-2.6-block.git] / drivers / watchdog / w83627hf_wdt.c
CommitLineData
d0173278 1// SPDX-License-Identifier: GPL-2.0+
1da177e4 2/*
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3 * w83627hf/thf WDT driver
4 *
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5 * (c) Copyright 2013 Guenter Roeck
6 * converted to watchdog infrastructure
7 *
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8 * (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
9 * added support for W83627THF.
1da177e4 10 *
d36b6910 11 * (c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com>
1da177e4
LT
12 *
13 * Based on advantechwdt.c which is based on wdt.c.
14 * Original copyright messages:
15 *
16 * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
17 *
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18 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
19 * All Rights Reserved.
1da177e4 20 *
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21 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
22 * warranty for any of this software. This material is provided
23 * "AS-IS" and at no charge.
24 *
29fa0586 25 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
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26 */
27
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28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
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30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/types.h>
1da177e4 33#include <linux/watchdog.h>
1da177e4 34#include <linux/ioport.h>
1da177e4 35#include <linux/init.h>
46a3949d 36#include <linux/io.h>
31eb42bd 37#include <linux/dmi.h>
1da177e4 38
9c67bea4 39#define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT"
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40#define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
41
962c04f5 42static int wdt_io;
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43static int cr_wdt_timeout; /* WDT timeout register */
44static int cr_wdt_control; /* WDT control register */
33f74b89 45static int cr_wdt_csr; /* WDT control & status register */
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46static int wdt_cfg_enter = 0x87;/* key to unlock configuration space */
47static int wdt_cfg_leave = 0xAA;/* key to lock configuration space */
962c04f5 48
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49enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
50 w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
3a9aedb2 51 w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
e11cfc69 52 nct6795, nct6796, nct6102, nct6116 };
1da177e4 53
30a83695 54static int timeout; /* in seconds */
1da177e4 55module_param(timeout, int, 0);
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56MODULE_PARM_DESC(timeout,
57 "Watchdog timeout in seconds. 1 <= timeout <= 255, default="
58 __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
1da177e4 59
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WVS
60static bool nowayout = WATCHDOG_NOWAYOUT;
61module_param(nowayout, bool, 0);
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62MODULE_PARM_DESC(nowayout,
63 "Watchdog cannot be stopped once started (default="
64 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
1da177e4 65
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66static int early_disable;
67module_param(early_disable, int, 0);
68MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)");
69
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70/*
71 * Kernel methods.
72 */
73
74#define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */
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75#define WDT_EFIR (wdt_io+0) /* Extended Function Index Register
76 (same as EFER) */
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77#define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */
78
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79#define W83627HF_LD_WDT 0x08
80
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81#define W83627HF_ID 0x52
82#define W83627S_ID 0x59
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83#define W83697HF_ID 0x60
84#define W83697UG_ID 0x68
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85#define W83637HF_ID 0x70
86#define W83627THF_ID 0x82
87#define W83687THF_ID 0x85
88#define W83627EHF_ID 0x88
89#define W83627DHG_ID 0xa0
90#define W83627UHG_ID 0xa2
91#define W83667HG_ID 0xa5
92#define W83627DHG_P_ID 0xb0
93#define W83667HG_B_ID 0xb3
94#define NCT6775_ID 0xb4
95#define NCT6776_ID 0xc3
33f74b89 96#define NCT6102_ID 0xc4
e11cfc69 97#define NCT6116_ID 0xd2
962c04f5 98#define NCT6779_ID 0xc5
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99#define NCT6791_ID 0xc8
100#define NCT6792_ID 0xc9
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101#define NCT6793_ID 0xd1
102#define NCT6795_ID 0xd3
57cbf0e3 103#define NCT6796_ID 0xd4 /* also NCT9697D, NCT9698D */
962c04f5 104
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105#define W83627HF_WDT_TIMEOUT 0xf6
106#define W83697HF_WDT_TIMEOUT 0xf4
33f74b89 107#define NCT6102D_WDT_TIMEOUT 0xf1
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108
109#define W83627HF_WDT_CONTROL 0xf5
110#define W83697HF_WDT_CONTROL 0xf3
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111#define NCT6102D_WDT_CONTROL 0xf0
112
113#define W836X7HF_WDT_CSR 0xf7
114#define NCT6102D_WDT_CSR 0xf2
7b6d0b6a 115
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116static void superio_outb(int reg, int val)
117{
118 outb(reg, WDT_EFER);
119 outb(val, WDT_EFDR);
120}
121
122static inline int superio_inb(int reg)
123{
124 outb(reg, WDT_EFER);
125 return inb(WDT_EFDR);
126}
127
128static int superio_enter(void)
1da177e4 129{
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130 if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME))
131 return -EBUSY;
132
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133 outb_p(wdt_cfg_enter, WDT_EFER); /* Enter extended function mode */
134 outb_p(wdt_cfg_enter, WDT_EFER); /* Again according to manual */
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135
136 return 0;
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137}
138
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139static void superio_select(int ld)
140{
141 superio_outb(0x07, ld);
142}
143
144static void superio_exit(void)
1da177e4 145{
31eb42bd 146 outb_p(wdt_cfg_leave, WDT_EFER); /* Leave extended function mode */
ef0c1a6b 147 release_region(wdt_io, 2);
1da177e4
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148}
149
962c04f5 150static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
1da177e4 151{
ef0c1a6b 152 int ret;
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153 unsigned char t;
154
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155 ret = superio_enter();
156 if (ret)
157 return ret;
1da177e4 158
ef0c1a6b 159 superio_select(W83627HF_LD_WDT);
8f526389 160
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161 /* set CR30 bit 0 to activate GPIO2 */
162 t = superio_inb(0x30);
ac461103 163 if (!(t & 0x01))
ef0c1a6b 164 superio_outb(0x30, t | 0x01);
8f526389 165
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166 switch (chip) {
167 case w83627hf:
168 case w83627s:
169 t = superio_inb(0x2B) & ~0x10;
170 superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
171 break;
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172 case w83697hf:
173 /* Set pin 119 to WDTO# mode (= CR29, WDT0) */
174 t = superio_inb(0x29) & ~0x60;
175 t |= 0x20;
176 superio_outb(0x29, t);
177 break;
178 case w83697ug:
179 /* Set pin 118 to WDTO# mode */
180 t = superio_inb(0x2b) & ~0x04;
181 superio_outb(0x2b, t);
182 break;
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183 case w83627thf:
184 t = (superio_inb(0x2B) & ~0x08) | 0x04;
185 superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
186 break;
187 case w83627dhg:
188 case w83627dhg_p:
189 t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
190 superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
7b6d0b6a 191 t = superio_inb(cr_wdt_control);
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192 t |= 0x02; /* enable the WDTO# output low pulse
193 * to the KBRST# pin */
7b6d0b6a 194 superio_outb(cr_wdt_control, t);
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195 break;
196 case w83637hf:
197 break;
198 case w83687thf:
199 t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */
200 superio_outb(0x2C, t);
201 break;
202 case w83627ehf:
203 case w83627uhg:
204 case w83667hg:
205 case w83667hg_b:
206 case nct6775:
207 case nct6776:
208 case nct6779:
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209 case nct6791:
210 case nct6792:
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211 case nct6793:
212 case nct6795:
57cbf0e3 213 case nct6796:
33f74b89 214 case nct6102:
e11cfc69 215 case nct6116:
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216 /*
217 * These chips have a fixed WDTO# output pin (W83627UHG),
218 * or support more than one WDTO# output pin.
219 * Don't touch its configuration, and hope the BIOS
220 * does the right thing.
221 */
7b6d0b6a 222 t = superio_inb(cr_wdt_control);
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223 t |= 0x02; /* enable the WDTO# output low pulse
224 * to the KBRST# pin */
7b6d0b6a 225 superio_outb(cr_wdt_control, t);
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226 break;
227 default:
228 break;
229 }
230
7b6d0b6a 231 t = superio_inb(cr_wdt_timeout);
93642ecd 232 if (t != 0) {
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233 if (early_disable) {
234 pr_warn("Stopping previously enabled watchdog until userland kicks in\n");
235 superio_outb(cr_wdt_timeout, 0);
236 } else {
237 pr_info("Watchdog already running. Resetting timeout to %d sec\n",
238 wdog->timeout);
239 superio_outb(cr_wdt_timeout, wdog->timeout);
240 }
93642ecd 241 }