[linux-block.git] / drivers / watchdog / sunxi_wdt.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *      sunxi Watchdog Driver
 *
 *      Copyright (c) 2013 Carlo Caione
 *                    2012 Henrik Nordstrom
 *
 *      Based on xen_wdt.c
 *      (c) Copyright 2010 Novell, Inc.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>

#define WDT_MAX_TIMEOUT         16
#define WDT_MIN_TIMEOUT         1
#define WDT_TIMEOUT_MASK        0x0F

#define WDT_CTRL_RELOAD         ((1 << 0) | (0x0a57 << 1))

#define WDT_MODE_EN             (1 << 0)

#define DRV_NAME		"sunxi-wdt"
#define DRV_VERSION		"1.0"

static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int timeout;

/*
 * This structure stores the register offsets for different variants
 * of Allwinner's watchdog hardware.
 */
struct sunxi_wdt_reg {
	u8 wdt_ctrl;
	u8 wdt_cfg;
	u8 wdt_mode;
	u8 wdt_timeout_shift;
	u8 wdt_reset_mask;
	u8 wdt_reset_val;
	u32 wdt_key_val;
};

struct sunxi_wdt_dev {
	struct watchdog_device wdt_dev;
	void __iomem *wdt_base;
	const struct sunxi_wdt_reg *wdt_regs;
};

/*
 * wdt_timeout_map maps the watchdog timer interval value in seconds to
 * the value of the register WDT_MODE at bits .wdt_timeout_shift ~ +3
 *
 * [timeout seconds] = register value
 *
 */

static const int wdt_timeout_map[] = {
	[1] = 0x1,  /* 1s  */
	[2] = 0x2,  /* 2s  */
	[3] = 0x3,  /* 3s  */
	[4] = 0x4,  /* 4s  */
	[5] = 0x5,  /* 5s  */
	[6] = 0x6,  /* 6s  */
	[8] = 0x7,  /* 8s  */
	[10] = 0x8, /* 10s */
	[12] = 0x9, /* 12s */
	[14] = 0xA, /* 14s */
	[16] = 0xB, /* 16s */
};


static int sunxi_wdt_restart(struct watchdog_device *wdt_dev,
			     unsigned long action, void *data)
{
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
	u32 val;

	/* Set system reset function */
	val = readl(wdt_base + regs->wdt_cfg);
	val &= ~(regs->wdt_reset_mask);
	val |= regs->wdt_reset_val;
	val |= regs->wdt_key_val;
	writel(val, wdt_base + regs->wdt_cfg);

	/* Set lowest timeout and enable watchdog */
	val = readl(wdt_base + regs->wdt_mode);
	val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
	val |= WDT_MODE_EN;
	val |= regs->wdt_key_val;
	writel(val, wdt_base + regs->wdt_mode);

	/*
	 * Restart the watchdog. The default (and lowest) interval
	 * value for the watchdog is 0.5s.
	 */
	writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);

	while (1) {
		mdelay(5);
		val = readl(wdt_base + regs->wdt_mode);
		val |= WDT_MODE_EN;
		val |= regs->wdt_key_val;
		writel(val, wdt_base + regs->wdt_mode);
	}
	return 0;
}

static int sunxi_wdt_ping(struct watchdog_device *wdt_dev)
{
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;

	writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);

	return 0;
}

static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev,
		unsigned int timeout)
{
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
	u32 reg;

	if (wdt_timeout_map[timeout] == 0)
		timeout++;

	sunxi_wdt->wdt_dev.timeout = timeout;

	reg = readl(wdt_base + regs->wdt_mode);
	reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
	reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
	reg |= regs->wdt_key_val;
	writel(reg, wdt_base + regs->wdt_mode);

	sunxi_wdt_ping(wdt_dev);

	return 0;
}

static int sunxi_wdt_stop(struct watchdog_device *wdt_dev)
{
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;

	writel(regs->wdt_key_val, wdt_base + regs->wdt_mode);

	return 0;
}

static int sunxi_wdt_start(struct watchdog_device *wdt_dev)
{
	u32 reg;
	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = sunxi_wdt->wdt_base;
	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
	int ret;

	ret = sunxi_wdt_set_timeout(&sunxi_wdt->wdt_dev,
			sunxi_wdt->wdt_dev.timeout);
	if (ret < 0)
		return ret;

	/* Set system reset function */
	reg = readl(wdt_base + regs->wdt_cfg);
	reg &= ~(regs->wdt_reset_mask);
	reg |= regs->wdt_reset_val;
	reg |= regs->wdt_key_val;
	writel(reg, wdt_base + regs->wdt_cfg);

	/* Enable watchdog */
	reg = readl(wdt_base + regs->wdt_mode);
	reg |= WDT_MODE_EN;
	reg |= regs->wdt_key_val;
	writel(reg, wdt_base + regs->wdt_mode);

	return 0;
}

static const struct watchdog_info sunxi_wdt_info = {
	.identity	= DRV_NAME,
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_KEEPALIVEPING |
			  WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops sunxi_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= sunxi_wdt_start,
	.stop		= sunxi_wdt_stop,
	.ping		= sunxi_wdt_ping,
	.set_timeout	= sunxi_wdt_set_timeout,
	.restart	= sunxi_wdt_restart,
};

static const struct sunxi_wdt_reg sun4i_wdt_reg = {
	.wdt_ctrl = 0x00,
	.wdt_cfg = 0x04,
	.wdt_mode = 0x04,
	.wdt_timeout_shift = 3,
	.wdt_reset_mask = 0x02,
	.wdt_reset_val = 0x02,
};

static const struct sunxi_wdt_reg sun6i_wdt_reg = {
	.wdt_ctrl = 0x10,
	.wdt_cfg = 0x14,
	.wdt_mode = 0x18,
	.wdt_timeout_shift = 4,
	.wdt_reset_mask = 0x03,
	.wdt_reset_val = 0x01,
};

static const struct sunxi_wdt_reg sun20i_wdt_reg = {
	.wdt_ctrl = 0x10,
	.wdt_cfg = 0x14,
	.wdt_mode = 0x18,
	.wdt_timeout_shift = 4,
	.wdt_reset_mask = 0x03,
	.wdt_reset_val = 0x01,
	.wdt_key_val = 0x16aa0000,
};

static const struct of_device_id sunxi_wdt_dt_ids[] = {
	{ .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
	{ .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
	{ .compatible = "allwinner,sun20i-d1-wdt", .data = &sun20i_wdt_reg },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);

static int sunxi_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct sunxi_wdt_dev *sunxi_wdt;
	int err;

	sunxi_wdt = devm_kzalloc(dev, sizeof(*sunxi_wdt), GFP_KERNEL);
	if (!sunxi_wdt)
		return -ENOMEM;

	sunxi_wdt->wdt_regs = of_device_get_match_data(dev);
	if (!sunxi_wdt->wdt_regs)
		return -ENODEV;

	sunxi_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(sunxi_wdt->wdt_base))
		return PTR_ERR(sunxi_wdt->wdt_base);

	sunxi_wdt->wdt_dev.info = &sunxi_wdt_info;
	sunxi_wdt->wdt_dev.ops = &sunxi_wdt_ops;
	sunxi_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
	sunxi_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
	sunxi_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
	sunxi_wdt->wdt_dev.parent = dev;

	watchdog_init_timeout(&sunxi_wdt->wdt_dev, timeout, dev);
	watchdog_set_nowayout(&sunxi_wdt->wdt_dev, nowayout);
	watchdog_set_restart_priority(&sunxi_wdt->wdt_dev, 128);

	watchdog_set_drvdata(&sunxi_wdt->wdt_dev, sunxi_wdt);

	sunxi_wdt_stop(&sunxi_wdt->wdt_dev);

	watchdog_stop_on_reboot(&sunxi_wdt->wdt_dev);
	err = devm_watchdog_register_device(dev, &sunxi_wdt->wdt_dev);
	if (unlikely(err))
		return err;

	dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)",
		 sunxi_wdt->wdt_dev.timeout, nowayout);

	return 0;
}

static struct platform_driver sunxi_wdt_driver = {
	.probe		= sunxi_wdt_probe,
	.driver		= {
		.name		= DRV_NAME,
		.of_match_table	= sunxi_wdt_dt_ids,
	},
};

module_platform_driver(sunxi_wdt_driver);

module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
		"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
MODULE_AUTHOR("Henrik Nordstrom <henrik@henriknordstrom.net>");
MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
d00680ed CC	2	/*
	3	* sunxi Watchdog Driver
	4	*
	5	* Copyright (c) 2013 Carlo Caione
	6	* 2012 Henrik Nordstrom
	7	*
d00680ed CC	8	* Based on xen_wdt.c
	9	* (c) Copyright 2010 Novell, Inc.
	10	*/
	11
	12	#include <linux/clk.h>
440e96bc	13	#include <linux/delay.h>
d00680ed CC	14	#include <linux/err.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/moduleparam.h>
	20	#include <linux/of.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/types.h>
	23	#include <linux/watchdog.h>
	24
	25	#define WDT_MAX_TIMEOUT 16
	26	#define WDT_MIN_TIMEOUT 1
f2147de3	27	#define WDT_TIMEOUT_MASK 0x0F
d00680ed	28
d00680ed CC	29	#define WDT_CTRL_RELOAD ((1 << 0) \| (0x0a57 << 1))
d00680ed CC	30
d00680ed	31	#define WDT_MODE_EN (1 << 0)
d00680ed CC	32
	33	#define DRV_NAME "sunxi-wdt"
	34	#define DRV_VERSION "1.0"
	35
	36	static bool nowayout = WATCHDOG_NOWAYOUT;
1d1dedc2	37	static unsigned int timeout;
d00680ed	38
f2147de3 CYT	39	/*
	40	* This structure stores the register offsets for different variants
	41	* of Allwinner's watchdog hardware.
	42	*/
	43	struct sunxi_wdt_reg {
	44	u8 wdt_ctrl;
	45	u8 wdt_cfg;
	46	u8 wdt_mode;
	47	u8 wdt_timeout_shift;
	48	u8 wdt_reset_mask;
	49	u8 wdt_reset_val;
94213a39	50	u32 wdt_key_val;
f2147de3 CYT	51	};
f2147de3 CYT	52
d00680ed CC	53	struct sunxi_wdt_dev {
	54	struct watchdog_device wdt_dev;
	55	void __iomem *wdt_base;
f2147de3	56	const struct sunxi_wdt_reg *wdt_regs;
d00680ed CC	57	};
	58
	59	/*
	60	* wdt_timeout_map maps the watchdog timer interval value in seconds to
f2147de3	61	* the value of the register WDT_MODE at bits .wdt_timeout_shift ~ +3
d00680ed CC	62	*
	63	* [timeout seconds] = register value
	64	*
	65	*/
	66
	67	static const int wdt_timeout_map[] = {
51ee34ab EL	68	[1] = 0x1, /* 1s */
	69	[2] = 0x2, /* 2s */
	70	[3] = 0x3, /* 3s */
	71	[4] = 0x4, /* 4s */
	72	[5] = 0x5, /* 5s */
	73	[6] = 0x6, /* 6s */
	74	[8] = 0x7, /* 8s */
	75	[10] = 0x8, /* 10s */
	76	[12] = 0x9, /* 12s */
	77	[14] = 0xA, /* 14s */
	78	[16] = 0xB, /* 16s */
d00680ed CC	79	};
d00680ed CC	80
440e96bc	81
4d8b229d GR	82	static int sunxi_wdt_restart(struct watchdog_device *wdt_dev,
4d8b229d GR	83	unsigned long action, void *data)
440e96bc	84	{
0ebad1e5	85	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
d20a1d90	86	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3 CYT	87	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
	88	u32 val;
	89
	90	/* Set system reset function */
	91	val = readl(wdt_base + regs->wdt_cfg);
	92	val &= ~(regs->wdt_reset_mask);
	93	val \|= regs->wdt_reset_val;
94213a39	94	val \|= regs->wdt_key_val;
f2147de3	95	writel(val, wdt_base + regs->wdt_cfg);
d20a1d90	96
f2147de3 CYT	97	/* Set lowest timeout and enable watchdog */
	98	val = readl(wdt_base + regs->wdt_mode);
	99	val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
	100	val \|= WDT_MODE_EN;
94213a39	101	val \|= regs->wdt_key_val;
f2147de3	102	writel(val, wdt_base + regs->wdt_mode);
440e96bc MR	103
	104	/*
	105	* Restart the watchdog. The default (and lowest) interval
	106	* value for the watchdog is 0.5s.
	107	*/
f2147de3	108	writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
440e96bc MR	109
	110	while (1) {
	111	mdelay(5);
f2147de3 CYT	112	val = readl(wdt_base + regs->wdt_mode);
f2147de3 CYT	113	val \|= WDT_MODE_EN;
94213a39	114	val \|= regs->wdt_key_val;
f2147de3	115	writel(val, wdt_base + regs->wdt_mode);
440e96bc	116	}
0ebad1e5	117	return 0;
440e96bc MR	118	}
440e96bc MR	119
d00680ed CC	120	static int sunxi_wdt_ping(struct watchdog_device *wdt_dev)
	121	{
	122	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	123	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3	124	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
d00680ed	125
f2147de3	126	writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
d00680ed CC	127
	128	return 0;
	129	}
	130
	131	static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev,
	132	unsigned int timeout)
	133	{
	134	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	135	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3	136	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
d00680ed CC	137	u32 reg;
	138
	139	if (wdt_timeout_map[timeout] == 0)
	140	timeout++;
	141
	142	sunxi_wdt->wdt_dev.timeout = timeout;
	143
f2147de3 CYT	144	reg = readl(wdt_base + regs->wdt_mode);
	145	reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
	146	reg \|= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
94213a39	147	reg \|= regs->wdt_key_val;
f2147de3	148	writel(reg, wdt_base + regs->wdt_mode);
d00680ed CC	149
	150	sunxi_wdt_ping(wdt_dev);
	151
	152	return 0;
	153	}
	154
	155	static int sunxi_wdt_stop(struct watchdog_device *wdt_dev)
	156	{
	157	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	158	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3	159	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
d00680ed	160
94213a39	161	writel(regs->wdt_key_val, wdt_base + regs->wdt_mode);
d00680ed CC	162
	163	return 0;
	164	}
	165
	166	static int sunxi_wdt_start(struct watchdog_device *wdt_dev)
	167	{
	168	u32 reg;
	169	struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
	170	void __iomem *wdt_base = sunxi_wdt->wdt_base;
f2147de3	171	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
d00680ed CC	172	int ret;
	173
	174	ret = sunxi_wdt_set_timeout(&sunxi_wdt->wdt_dev,
	175	sunxi_wdt->wdt_dev.timeout);
	176	if (ret < 0)
	177	return ret;
	178
f2147de3 CYT	179	/* Set system reset function */
	180	reg = readl(wdt_base + regs->wdt_cfg);
	181	reg &= ~(regs->wdt_reset_mask);
0919e444	182	reg \|= regs->wdt_reset_val;
94213a39	183	reg \|= regs->wdt_key_val;
f2147de3 CYT	184	writel(reg, wdt_base + regs->wdt_cfg);
	185
	186	/* Enable watchdog */
	187	reg = readl(wdt_base + regs->wdt_mode);
	188	reg \|= WDT_MODE_EN;
94213a39	189	reg \|= regs->wdt_key_val;
f2147de3	190	writel(reg, wdt_base + regs->wdt_mode);
d00680ed CC	191
	192	return 0;
	193	}
	194
	195	static const struct watchdog_info sunxi_wdt_info = {
	196	.identity = DRV_NAME,
	197	.options = WDIOF_SETTIMEOUT \|
	198	WDIOF_KEEPALIVEPING \|
	199	WDIOF_MAGICCLOSE,
	200	};
	201
	202	static const struct watchdog_ops sunxi_wdt_ops = {
	203	.owner = THIS_MODULE,
	204	.start = sunxi_wdt_start,
	205	.stop = sunxi_wdt_stop,
	206	.ping = sunxi_wdt_ping,
	207	.set_timeout = sunxi_wdt_set_timeout,
0ebad1e5	208	.restart = sunxi_wdt_restart,
d00680ed CC	209	};
d00680ed CC	210
f2147de3 CYT	211	static const struct sunxi_wdt_reg sun4i_wdt_reg = {
	212	.wdt_ctrl = 0x00,
	213	.wdt_cfg = 0x04,
	214	.wdt_mode = 0x04,
	215	.wdt_timeout_shift = 3,
	216	.wdt_reset_mask = 0x02,
	217	.wdt_reset_val = 0x02,
	218	};
	219
c5ec618f CYT	220	static const struct sunxi_wdt_reg sun6i_wdt_reg = {
	221	.wdt_ctrl = 0x10,
	222	.wdt_cfg = 0x14,
	223	.wdt_mode = 0x18,
	224	.wdt_timeout_shift = 4,
	225	.wdt_reset_mask = 0x03,
	226	.wdt_reset_val = 0x01,
	227	};
	228
94213a39 SH	229	static const struct sunxi_wdt_reg sun20i_wdt_reg = {
	230	.wdt_ctrl = 0x10,
	231	.wdt_cfg = 0x14,
	232	.wdt_mode = 0x18,
	233	.wdt_timeout_shift = 4,
	234	.wdt_reset_mask = 0x03,
	235	.wdt_reset_val = 0x01,
	236	.wdt_key_val = 0x16aa0000,
	237	};
	238
f2147de3 CYT	239	static const struct of_device_id sunxi_wdt_dt_ids[] = {
f2147de3 CYT	240	{ .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
c5ec618f	241	{ .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
94213a39	242	{ .compatible = "allwinner,sun20i-d1-wdt", .data = &sun20i_wdt_reg },
f2147de3 CYT	243	{ /* sentinel */ }
	244	};
	245	MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
	246
1d5898b4	247	static int sunxi_wdt_probe(struct platform_device *pdev)
d00680ed	248	{
8ba41f6c	249	struct device *dev = &pdev->dev;
d00680ed	250	struct sunxi_wdt_dev *sunxi_wdt;
d00680ed CC	251	int err;
d00680ed CC	252
8ba41f6c	253	sunxi_wdt = devm_kzalloc(dev, sizeof(*sunxi_wdt), GFP_KERNEL);
d00680ed	254	if (!sunxi_wdt)
ff01cb1c	255	return -ENOMEM;
d00680ed	256
8ba41f6c	257	sunxi_wdt->wdt_regs = of_device_get_match_data(dev);
e5310371	258	if (!sunxi_wdt->wdt_regs)
f2147de3 CYT	259	return -ENODEV;
f2147de3 CYT	260
0f0a6a28	261	sunxi_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
d00680ed CC	262	if (IS_ERR(sunxi_wdt->wdt_base))
	263	return PTR_ERR(sunxi_wdt->wdt_base);
	264
	265	sunxi_wdt->wdt_dev.info = &sunxi_wdt_info;
	266	sunxi_wdt->wdt_dev.ops = &sunxi_wdt_ops;
	267	sunxi_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
	268	sunxi_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
	269	sunxi_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
8ba41f6c	270	sunxi_wdt->wdt_dev.parent = dev;
d00680ed	271
8ba41f6c	272	watchdog_init_timeout(&sunxi_wdt->wdt_dev, timeout, dev);
d00680ed	273	watchdog_set_nowayout(&sunxi_wdt->wdt_dev, nowayout);
0ebad1e5	274	watchdog_set_restart_priority(&sunxi_wdt->wdt_dev, 128);
d00680ed CC	275
	276	watchdog_set_drvdata(&sunxi_wdt->wdt_dev, sunxi_wdt);
	277
	278	sunxi_wdt_stop(&sunxi_wdt->wdt_dev);
	279
42f82693	280	watchdog_stop_on_reboot(&sunxi_wdt->wdt_dev);
8ba41f6c	281	err = devm_watchdog_register_device(dev, &sunxi_wdt->wdt_dev);
d00680ed CC	282	if (unlikely(err))
	283	return err;
	284
8ba41f6c GR	285	dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)",
8ba41f6c GR	286	sunxi_wdt->wdt_dev.timeout, nowayout);
d00680ed CC	287
	288	return 0;
	289	}
	290
d00680ed CC	291	static struct platform_driver sunxi_wdt_driver = {
d00680ed CC	292	.probe = sunxi_wdt_probe,
d00680ed	293	.driver = {
d00680ed	294	.name = DRV_NAME,
85eee819	295	.of_match_table = sunxi_wdt_dt_ids,
d00680ed CC	296	},
	297	};
	298
	299	module_platform_driver(sunxi_wdt_driver);
	300
	301	module_param(timeout, uint, 0);
	302	MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
	303
	304	module_param(nowayout, bool, 0);
	305	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	306	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	307
	308	MODULE_LICENSE("GPL");
	309	MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
	310	MODULE_AUTHOR("Henrik Nordstrom <henrik@henriknordstrom.net>");
	311	MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
	312	MODULE_VERSION(DRV_VERSION);