[linux-2.6-block.git] / drivers / watchdog / stm32_iwdg.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for STM32 Independent Watchdog
 *
 * Copyright (C) STMicroelectronics 2017
 * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
 *
 * This driver is based on tegra_wdt.c
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>

/* IWDG registers */
#define IWDG_KR		0x00 /* Key register */
#define IWDG_PR		0x04 /* Prescaler Register */
#define IWDG_RLR	0x08 /* ReLoad Register */
#define IWDG_SR		0x0C /* Status Register */
#define IWDG_WINR	0x10 /* Windows Register */

/* IWDG_KR register bit mask */
#define KR_KEY_RELOAD	0xAAAA /* reload counter enable */
#define KR_KEY_ENABLE	0xCCCC /* peripheral enable */
#define KR_KEY_EWA	0x5555 /* write access enable */
#define KR_KEY_DWA	0x0000 /* write access disable */

/* IWDG_PR register bit values */
#define PR_4		0x00 /* prescaler set to 4 */
#define PR_8		0x01 /* prescaler set to 8 */
#define PR_16		0x02 /* prescaler set to 16 */
#define PR_32		0x03 /* prescaler set to 32 */
#define PR_64		0x04 /* prescaler set to 64 */
#define PR_128		0x05 /* prescaler set to 128 */
#define PR_256		0x06 /* prescaler set to 256 */

/* IWDG_RLR register values */
#define RLR_MIN		0x07C /* min value supported by reload register */
#define RLR_MAX		0xFFF /* max value supported by reload register */

/* IWDG_SR register bit mask */
#define FLAG_PVU	BIT(0) /* Watchdog prescaler value update */
#define FLAG_RVU	BIT(1) /* Watchdog counter reload value update */

/* set timeout to 100000 us */
#define TIMEOUT_US	100000
#define SLEEP_US	1000

#define HAS_PCLK	true

struct stm32_iwdg {
	struct watchdog_device	wdd;
	void __iomem		*regs;
	struct clk		*clk_lsi;
	struct clk		*clk_pclk;
	unsigned int		rate;
	bool			has_pclk;
};

static inline u32 reg_read(void __iomem *base, u32 reg)
{
	return readl_relaxed(base + reg);
}

static inline void reg_write(void __iomem *base, u32 reg, u32 val)
{
	writel_relaxed(val, base + reg);
}

static int stm32_iwdg_start(struct watchdog_device *wdd)
{
	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
	u32 val = FLAG_PVU | FLAG_RVU;
	u32 reload;
	int ret;

	dev_dbg(wdd->parent, "%s\n", __func__);

	/* prescaler fixed to 256 */
	reload = clamp_t(unsigned int, ((wdd->timeout * wdt->rate) / 256) - 1,
			 RLR_MIN, RLR_MAX);

	/* enable write access */
	reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);

	/* set prescaler & reload registers */
	reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */
	reg_write(wdt->regs, IWDG_RLR, reload);
	reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);

	/* wait for the registers to be updated (max 100ms) */
	ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val,
					 !(val & (FLAG_PVU | FLAG_RVU)),
					 SLEEP_US, TIMEOUT_US);
	if (ret) {
		dev_err(wdd->parent,
			"Fail to set prescaler or reload registers\n");
		return ret;
	}

	/* reload watchdog */
	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);

	return 0;
}

static int stm32_iwdg_ping(struct watchdog_device *wdd)
{
	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);

	dev_dbg(wdd->parent, "%s\n", __func__);

	/* reload watchdog */
	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);

	return 0;
}

static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
				  unsigned int timeout)
{
	dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);

	wdd->timeout = timeout;

	if (watchdog_active(wdd))
		return stm32_iwdg_start(wdd);

	return 0;
}

static int stm32_iwdg_clk_init(struct platform_device *pdev,
			       struct stm32_iwdg *wdt)
{
	u32 ret;

	wdt->clk_lsi = devm_clk_get(&pdev->dev, "lsi");
	if (IS_ERR(wdt->clk_lsi)) {
		dev_err(&pdev->dev, "Unable to get lsi clock\n");
		return PTR_ERR(wdt->clk_lsi);
	}

	/* optional peripheral clock */
	if (wdt->has_pclk) {
		wdt->clk_pclk = devm_clk_get(&pdev->dev, "pclk");
		if (IS_ERR(wdt->clk_pclk)) {
			dev_err(&pdev->dev, "Unable to get pclk clock\n");
			return PTR_ERR(wdt->clk_pclk);
		}

		ret = clk_prepare_enable(wdt->clk_pclk);
		if (ret) {
			dev_err(&pdev->dev, "Unable to prepare pclk clock\n");
			return ret;
		}
	}

	ret = clk_prepare_enable(wdt->clk_lsi);
	if (ret) {
		dev_err(&pdev->dev, "Unable to prepare lsi clock\n");
		clk_disable_unprepare(wdt->clk_pclk);
		return ret;
	}

	wdt->rate = clk_get_rate(wdt->clk_lsi);

	return 0;
}

static const struct watchdog_info stm32_iwdg_info = {
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_MAGICCLOSE |
			  WDIOF_KEEPALIVEPING,
	.identity	= "STM32 Independent Watchdog",
};

static const struct watchdog_ops stm32_iwdg_ops = {
	.owner		= THIS_MODULE,
	.start		= stm32_iwdg_start,
	.ping		= stm32_iwdg_ping,
	.set_timeout	= stm32_iwdg_set_timeout,
};

static const struct of_device_id stm32_iwdg_of_match[] = {
	{ .compatible = "st,stm32-iwdg", .data = (void *)!HAS_PCLK },
	{ .compatible = "st,stm32mp1-iwdg", .data = (void *)HAS_PCLK },
	{ /* end node */ }
};
MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);

static int stm32_iwdg_probe(struct platform_device *pdev)
{
	struct watchdog_device *wdd;
	const struct of_device_id *match;
	struct stm32_iwdg *wdt;
	struct resource *res;
	int ret;

	match = of_match_device(stm32_iwdg_of_match, &pdev->dev);
	if (!match)
		return -ENODEV;

	wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdt->has_pclk = match->data;

	/* This is the timer base. */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdt->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wdt->regs)) {
		dev_err(&pdev->dev, "Could not get resource\n");
		return PTR_ERR(wdt->regs);
	}

	ret = stm32_iwdg_clk_init(pdev, wdt);
	if (ret)
		return ret;

	/* Initialize struct watchdog_device. */
	wdd = &wdt->wdd;
	wdd->info = &stm32_iwdg_info;
	wdd->ops = &stm32_iwdg_ops;
	wdd->min_timeout = ((RLR_MIN + 1) * 256) / wdt->rate;
	wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * 256 * 1000) / wdt->rate;
	wdd->parent = &pdev->dev;

	watchdog_set_drvdata(wdd, wdt);
	watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);

	ret = watchdog_init_timeout(wdd, 0, &pdev->dev);
	if (ret)
		dev_warn(&pdev->dev,
			 "unable to set timeout value, using default\n");

	ret = watchdog_register_device(wdd);
	if (ret) {
		dev_err(&pdev->dev, "failed to register watchdog device\n");
		goto err;
	}

	platform_set_drvdata(pdev, wdt);

	return 0;
err:
	clk_disable_unprepare(wdt->clk_lsi);
	clk_disable_unprepare(wdt->clk_pclk);

	return ret;
}

static int stm32_iwdg_remove(struct platform_device *pdev)
{
	struct stm32_iwdg *wdt = platform_get_drvdata(pdev);

	watchdog_unregister_device(&wdt->wdd);
	clk_disable_unprepare(wdt->clk_lsi);
	clk_disable_unprepare(wdt->clk_pclk);

	return 0;
}

static struct platform_driver stm32_iwdg_driver = {
	.probe		= stm32_iwdg_probe,
	.remove		= stm32_iwdg_remove,
	.driver = {
		.name	= "iwdg",
		.of_match_table = of_match_ptr(stm32_iwdg_of_match),
	},
};
module_platform_driver(stm32_iwdg_driver);

MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
49620a28	1	// SPDX-License-Identifier: GPL-2.0
4332d113 YF	2	/*
	3	* Driver for STM32 Independent Watchdog
	4	*
49620a28 BG	5	* Copyright (C) STMicroelectronics 2017
49620a28 BG	6	* Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
4332d113 YF	7	*
	8	* This driver is based on tegra_wdt.c
	9	*
4332d113 YF	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/delay.h>
4332d113 YF	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/iopoll.h>
c2cf466c LB	17	#include <linux/kernel.h>
c2cf466c LB	18	#include <linux/module.h>
4332d113	19	#include <linux/of.h>
c2cf466c	20	#include <linux/of_device.h>
4332d113 YF	21	#include <linux/platform_device.h>
	22	#include <linux/watchdog.h>
	23
	24	/* IWDG registers */
	25	#define IWDG_KR 0x00 /* Key register */
	26	#define IWDG_PR 0x04 /* Prescaler Register */
	27	#define IWDG_RLR 0x08 /* ReLoad Register */
	28	#define IWDG_SR 0x0C /* Status Register */
	29	#define IWDG_WINR 0x10 /* Windows Register */
	30
	31	/* IWDG_KR register bit mask */
	32	#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
	33	#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
	34	#define KR_KEY_EWA 0x5555 /* write access enable */
	35	#define KR_KEY_DWA 0x0000 /* write access disable */
	36
	37	/* IWDG_PR register bit values */
	38	#define PR_4 0x00 /* prescaler set to 4 */
	39	#define PR_8 0x01 /* prescaler set to 8 */
	40	#define PR_16 0x02 /* prescaler set to 16 */
	41	#define PR_32 0x03 /* prescaler set to 32 */
	42	#define PR_64 0x04 /* prescaler set to 64 */
	43	#define PR_128 0x05 /* prescaler set to 128 */
	44	#define PR_256 0x06 /* prescaler set to 256 */
	45
	46	/* IWDG_RLR register values */
	47	#define RLR_MIN 0x07C /* min value supported by reload register */
	48	#define RLR_MAX 0xFFF /* max value supported by reload register */
	49
	50	/* IWDG_SR register bit mask */
	51	#define FLAG_PVU BIT(0) /* Watchdog prescaler value update */
	52	#define FLAG_RVU BIT(1) /* Watchdog counter reload value update */
	53
	54	/* set timeout to 100000 us */
	55	#define TIMEOUT_US 100000
	56	#define SLEEP_US 1000
	57
c2cf466c LB	58	#define HAS_PCLK true
c2cf466c LB	59
4332d113 YF	60	struct stm32_iwdg {
	61	struct watchdog_device wdd;
	62	void __iomem *regs;
c2cf466c LB	63	struct clk *clk_lsi;
c2cf466c LB	64	struct clk *clk_pclk;
4332d113	65	unsigned int rate;
c2cf466c	66	bool has_pclk;
4332d113 YF	67	};
	68
	69	static inline u32 reg_read(void __iomem *base, u32 reg)
	70	{
	71	return readl_relaxed(base + reg);
	72	}
	73
	74	static inline void reg_write(void __iomem *base, u32 reg, u32 val)
	75	{
	76	writel_relaxed(val, base + reg);
	77	}
	78
	79	static int stm32_iwdg_start(struct watchdog_device *wdd)
	80	{
	81	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
	82	u32 val = FLAG_PVU \| FLAG_RVU;
	83	u32 reload;
	84	int ret;
	85
	86	dev_dbg(wdd->parent, "%s\n", __func__);
	87
	88	/* prescaler fixed to 256 */
	89	reload = clamp_t(unsigned int, ((wdd->timeout * wdt->rate) / 256) - 1,
	90	RLR_MIN, RLR_MAX);
	91
	92	/* enable write access */
	93	reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
	94
	95	/* set prescaler & reload registers */
	96	reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */
	97	reg_write(wdt->regs, IWDG_RLR, reload);
	98	reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
	99
	100	/* wait for the registers to be updated (max 100ms) */
	101	ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val,
	102	!(val & (FLAG_PVU \| FLAG_RVU)),
	103	SLEEP_US, TIMEOUT_US);
	104	if (ret) {
	105	dev_err(wdd->parent,
	106	"Fail to set prescaler or reload registers\n");
	107	return ret;
	108	}
	109
	110	/* reload watchdog */
	111	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
	112
	113	return 0;
	114	}
	115
	116	static int stm32_iwdg_ping(struct watchdog_device *wdd)
	117	{
	118	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
	119
	120	dev_dbg(wdd->parent, "%s\n", __func__);
	121
	122	/* reload watchdog */
	123	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
	124
	125	return 0;
	126	}
	127
	128	static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
	129	unsigned int timeout)
	130	{
131	dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
132
133	wdd->timeout = timeout;
134
135	if (watchdog_active(wdd))
136	return stm32_iwdg_start(wdd);
137
138	return 0;
139	}
140
c2cf466c LB	141	static int stm32_iwdg_clk_init(struct platform_device *pdev,
	142	struct stm32_iwdg *wdt)
	143	{
	144	u32 ret;
	145
	146	wdt->clk_lsi = devm_clk_get(&pdev->dev, "lsi");
	147	if (IS_ERR(wdt->clk_lsi)) {
	148	dev_err(&pdev->dev, "Unable to get lsi clock\n");
	149	return PTR_ERR(wdt->clk_lsi);
	150	}
	151
	152	/* optional peripheral clock */
	153	if (wdt->has_pclk) {
	154	wdt->clk_pclk = devm_clk_get(&pdev->dev, "pclk");
	155	if (IS_ERR(wdt->clk_pclk)) {
	156	dev_err(&pdev->dev, "Unable to get pclk clock\n");
	157	return PTR_ERR(wdt->clk_pclk);
	158	}
	159
	160	ret = clk_prepare_enable(wdt->clk_pclk);
	161	if (ret) {
	162	dev_err(&pdev->dev, "Unable to prepare pclk clock\n");
	163	return ret;
	164	}
	165	}
	166
	167	ret = clk_prepare_enable(wdt->clk_lsi);
	168	if (ret) {
	169	dev_err(&pdev->dev, "Unable to prepare lsi clock\n");
	170	clk_disable_unprepare(wdt->clk_pclk);
	171	return ret;
	172	}
	173
	174	wdt->rate = clk_get_rate(wdt->clk_lsi);
	175
	176	return 0;
	177	}
	178
4332d113 YF	179	static const struct watchdog_info stm32_iwdg_info = {
	180	.options = WDIOF_SETTIMEOUT \|
	181	WDIOF_MAGICCLOSE \|
	182	WDIOF_KEEPALIVEPING,
	183	.identity = "STM32 Independent Watchdog",
	184	};
	185
d7b16e75	186	static const struct watchdog_ops stm32_iwdg_ops = {
4332d113 YF	187	.owner = THIS_MODULE,
	188	.start = stm32_iwdg_start,
	189	.ping = stm32_iwdg_ping,
	190	.set_timeout = stm32_iwdg_set_timeout,
	191	};
	192
c2cf466c LB	193	static const struct of_device_id stm32_iwdg_of_match[] = {
	194	{ .compatible = "st,stm32-iwdg", .data = (void *)!HAS_PCLK },
	195	{ .compatible = "st,stm32mp1-iwdg", .data = (void *)HAS_PCLK },
	196	{ /* end node */ }
	197	};
	198	MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
	199
4332d113 YF	200	static int stm32_iwdg_probe(struct platform_device *pdev)
	201	{
	202	struct watchdog_device *wdd;
c2cf466c	203	const struct of_device_id *match;
4332d113 YF	204	struct stm32_iwdg *wdt;
4332d113 YF	205	struct resource *res;
4332d113 YF	206	int ret;
4332d113 YF	207
c2cf466c LB	208	match = of_match_device(stm32_iwdg_of_match, &pdev->dev);
	209	if (!match)
	210	return -ENODEV;
	211
	212	wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
	213	if (!wdt)
	214	return -ENOMEM;
	215
	216	wdt->has_pclk = match->data;
	217
4332d113 YF	218	/* This is the timer base. */
4332d113 YF	219	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c2cf466c LB	220	wdt->regs = devm_ioremap_resource(&pdev->dev, res);
c2cf466c LB	221	if (IS_ERR(wdt->regs)) {
4332d113	222	dev_err(&pdev->dev, "Could not get resource\n");
c2cf466c	223	return PTR_ERR(wdt->regs);
4332d113 YF	224	}
4332d113 YF	225
c2cf466c LB	226	ret = stm32_iwdg_clk_init(pdev, wdt);
c2cf466c LB	227	if (ret)
4332d113	228	return ret;
4332d113 YF	229
	230	/* Initialize struct watchdog_device. */
	231	wdd = &wdt->wdd;
	232	wdd->info = &stm32_iwdg_info;
	233	wdd->ops = &stm32_iwdg_ops;
	234	wdd->min_timeout = ((RLR_MIN + 1) * 256) / wdt->rate;
	235	wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * 256 * 1000) / wdt->rate;
	236	wdd->parent = &pdev->dev;
	237
	238	watchdog_set_drvdata(wdd, wdt);
	239	watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
	240
	241	ret = watchdog_init_timeout(wdd, 0, &pdev->dev);
	242	if (ret)
	243	dev_warn(&pdev->dev,
	244	"unable to set timeout value, using default\n");
	245
	246	ret = watchdog_register_device(wdd);
	247	if (ret) {
	248	dev_err(&pdev->dev, "failed to register watchdog device\n");
	249	goto err;
	250	}
	251
	252	platform_set_drvdata(pdev, wdt);
	253
	254	return 0;
	255	err:
c2cf466c LB	256	clk_disable_unprepare(wdt->clk_lsi);
c2cf466c LB	257	clk_disable_unprepare(wdt->clk_pclk);
4332d113 YF	258
	259	return ret;
	260	}
	261
	262	static int stm32_iwdg_remove(struct platform_device *pdev)
	263	{
	264	struct stm32_iwdg *wdt = platform_get_drvdata(pdev);
	265
	266	watchdog_unregister_device(&wdt->wdd);
c2cf466c LB	267	clk_disable_unprepare(wdt->clk_lsi);
c2cf466c LB	268	clk_disable_unprepare(wdt->clk_pclk);
4332d113 YF	269
	270	return 0;
	271	}
	272
4332d113 YF	273	static struct platform_driver stm32_iwdg_driver = {
	274	.probe = stm32_iwdg_probe,
	275	.remove = stm32_iwdg_remove,
	276	.driver = {
	277	.name = "iwdg",
c2cf466c	278	.of_match_table = of_match_ptr(stm32_iwdg_of_match),
4332d113 YF	279	},
	280	};
	281	module_platform_driver(stm32_iwdg_driver);
	282
	283	MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
	284	MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
	285	MODULE_LICENSE("GPL v2");