[linux-2.6-block.git] / drivers / watchdog / stm32_iwdg.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for STM32 Independent Watchdog
 *
 * Copyright (C) STMicroelectronics 2017
 * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
 *
 * This driver is based on tegra_wdt.c
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>

/* IWDG registers */
#define IWDG_KR		0x00 /* Key register */
#define IWDG_PR		0x04 /* Prescaler Register */
#define IWDG_RLR	0x08 /* ReLoad Register */
#define IWDG_SR		0x0C /* Status Register */
#define IWDG_WINR	0x10 /* Windows Register */

/* IWDG_KR register bit mask */
#define KR_KEY_RELOAD	0xAAAA /* reload counter enable */
#define KR_KEY_ENABLE	0xCCCC /* peripheral enable */
#define KR_KEY_EWA	0x5555 /* write access enable */
#define KR_KEY_DWA	0x0000 /* write access disable */

/* IWDG_PR register */
#define PR_SHIFT	2
#define PR_MIN		BIT(PR_SHIFT)

/* IWDG_RLR register values */
#define RLR_MIN		0x2		/* min value recommended */
#define RLR_MAX		GENMASK(11, 0)	/* max value of reload register */

/* IWDG_SR register bit mask */
#define SR_PVU	BIT(0) /* Watchdog prescaler value update */
#define SR_RVU	BIT(1) /* Watchdog counter reload value update */

/* set timeout to 100000 us */
#define TIMEOUT_US	100000
#define SLEEP_US	1000

struct stm32_iwdg_data {
	bool has_pclk;
	u32 max_prescaler;
};

static const struct stm32_iwdg_data stm32_iwdg_data = {
	.has_pclk = false,
	.max_prescaler = 256,
};

static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
	.has_pclk = true,
	.max_prescaler = 1024,
};

struct stm32_iwdg {
	struct watchdog_device	wdd;
	const struct stm32_iwdg_data *data;
	void __iomem		*regs;
	struct clk		*clk_lsi;
	struct clk		*clk_pclk;
	unsigned int		rate;
};

static inline u32 reg_read(void __iomem *base, u32 reg)
{
	return readl_relaxed(base + reg);
}

static inline void reg_write(void __iomem *base, u32 reg, u32 val)
{
	writel_relaxed(val, base + reg);
}

static int stm32_iwdg_start(struct watchdog_device *wdd)
{
	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
	u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
	int ret;

	dev_dbg(wdd->parent, "%s\n", __func__);

	tout = clamp_t(unsigned int, wdd->timeout,
		       wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);

	presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);

	/* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
	presc = roundup_pow_of_two(presc);
	iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
	iwdg_rlr = ((tout * wdt->rate) / presc) - 1;

	/* enable write access */
	reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);

	/* set prescaler & reload registers */
	reg_write(wdt->regs, IWDG_PR, iwdg_pr);
	reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
	reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);

	/* wait for the registers to be updated (max 100ms) */
	ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
					 !(iwdg_sr & (SR_PVU | SR_RVU)),
					 SLEEP_US, TIMEOUT_US);
	if (ret) {
		dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
		return ret;
	}

	/* reload watchdog */
	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);

	return 0;
}

static int stm32_iwdg_ping(struct watchdog_device *wdd)
{
	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);

	dev_dbg(wdd->parent, "%s\n", __func__);

	/* reload watchdog */
	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);

	return 0;
}

static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
				  unsigned int timeout)
{
	dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);

	wdd->timeout = timeout;

	if (watchdog_active(wdd))
		return stm32_iwdg_start(wdd);

	return 0;
}

static void stm32_clk_disable_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static int stm32_iwdg_clk_init(struct platform_device *pdev,
			       struct stm32_iwdg *wdt)
{
	struct device *dev = &pdev->dev;
	u32 ret;

	wdt->clk_lsi = devm_clk_get(dev, "lsi");
	if (IS_ERR(wdt->clk_lsi)) {
		dev_err(dev, "Unable to get lsi clock\n");
		return PTR_ERR(wdt->clk_lsi);
	}

	/* optional peripheral clock */
	if (wdt->data->has_pclk) {
		wdt->clk_pclk = devm_clk_get(dev, "pclk");
		if (IS_ERR(wdt->clk_pclk)) {
			dev_err(dev, "Unable to get pclk clock\n");
			return PTR_ERR(wdt->clk_pclk);
		}

		ret = clk_prepare_enable(wdt->clk_pclk);
		if (ret) {
			dev_err(dev, "Unable to prepare pclk clock\n");
			return ret;
		}
		ret = devm_add_action_or_reset(dev,
					       stm32_clk_disable_unprepare,
					       wdt->clk_pclk);
		if (ret)
			return ret;
	}

	ret = clk_prepare_enable(wdt->clk_lsi);
	if (ret) {
		dev_err(dev, "Unable to prepare lsi clock\n");
		return ret;
	}
	ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
				       wdt->clk_lsi);
	if (ret)
		return ret;

	wdt->rate = clk_get_rate(wdt->clk_lsi);

	return 0;
}

static const struct watchdog_info stm32_iwdg_info = {
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_MAGICCLOSE |
			  WDIOF_KEEPALIVEPING,
	.identity	= "STM32 Independent Watchdog",
};

static const struct watchdog_ops stm32_iwdg_ops = {
	.owner		= THIS_MODULE,
	.start		= stm32_iwdg_start,
	.ping		= stm32_iwdg_ping,
	.set_timeout	= stm32_iwdg_set_timeout,
};

static const struct of_device_id stm32_iwdg_of_match[] = {
	{ .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
	{ .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
	{ /* end node */ }
};
MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);

static int stm32_iwdg_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct stm32_iwdg *wdt;
	int ret;

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdt->data = of_device_get_match_data(&pdev->dev);
	if (!wdt->data)
		return -ENODEV;

	/* This is the timer base. */
	wdt->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(wdt->regs)) {
		dev_err(dev, "Could not get resource\n");
		return PTR_ERR(wdt->regs);
	}

	ret = stm32_iwdg_clk_init(pdev, wdt);
	if (ret)
		return ret;

	/* Initialize struct watchdog_device. */
	wdd = &wdt->wdd;
	wdd->parent = dev;
	wdd->info = &stm32_iwdg_info;
	wdd->ops = &stm32_iwdg_ops;
	wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
	wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
				    1000) / wdt->rate;

	watchdog_set_drvdata(wdd, wdt);
	watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
	watchdog_init_timeout(wdd, 0, dev);

	ret = devm_watchdog_register_device(dev, wdd);
	if (ret) {
		dev_err(dev, "failed to register watchdog device\n");
		return ret;
	}

	platform_set_drvdata(pdev, wdt);

	return 0;
}

static struct platform_driver stm32_iwdg_driver = {
	.probe		= stm32_iwdg_probe,
	.driver = {
		.name	= "iwdg",
		.of_match_table = of_match_ptr(stm32_iwdg_of_match),
	},
};
module_platform_driver(stm32_iwdg_driver);

MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
49620a28	1	// SPDX-License-Identifier: GPL-2.0
4332d113 YF	2	/*
	3	* Driver for STM32 Independent Watchdog
	4	*
49620a28 BG	5	* Copyright (C) STMicroelectronics 2017
49620a28 BG	6	* Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
4332d113 YF	7	*
	8	* This driver is based on tegra_wdt.c
	9	*
4332d113 YF	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/delay.h>
4332d113 YF	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/iopoll.h>
c2cf466c LB	17	#include <linux/kernel.h>
c2cf466c LB	18	#include <linux/module.h>
4332d113	19	#include <linux/of.h>
c2cf466c	20	#include <linux/of_device.h>
4332d113 YF	21	#include <linux/platform_device.h>
	22	#include <linux/watchdog.h>
	23
	24	/* IWDG registers */
	25	#define IWDG_KR 0x00 /* Key register */
	26	#define IWDG_PR 0x04 /* Prescaler Register */
	27	#define IWDG_RLR 0x08 /* ReLoad Register */
	28	#define IWDG_SR 0x0C /* Status Register */
	29	#define IWDG_WINR 0x10 /* Windows Register */
	30
	31	/* IWDG_KR register bit mask */
	32	#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
	33	#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
	34	#define KR_KEY_EWA 0x5555 /* write access enable */
	35	#define KR_KEY_DWA 0x0000 /* write access disable */
	36
e9974166 LB	37	/* IWDG_PR register */
	38	#define PR_SHIFT 2
	39	#define PR_MIN BIT(PR_SHIFT)
4332d113 YF	40
4332d113 YF	41	/* IWDG_RLR register values */
e9974166 LB	42	#define RLR_MIN 0x2 /* min value recommended */
e9974166 LB	43	#define RLR_MAX GENMASK(11, 0) /* max value of reload register */
4332d113 YF	44
4332d113 YF	45	/* IWDG_SR register bit mask */
e9974166 LB	46	#define SR_PVU BIT(0) /* Watchdog prescaler value update */
e9974166 LB	47	#define SR_RVU BIT(1) /* Watchdog counter reload value update */
4332d113 YF	48
	49	/* set timeout to 100000 us */
	50	#define TIMEOUT_US 100000
	51	#define SLEEP_US 1000
	52
e9974166 LB	53	struct stm32_iwdg_data {
	54	bool has_pclk;
	55	u32 max_prescaler;
	56	};
	57
	58	static const struct stm32_iwdg_data stm32_iwdg_data = {
	59	.has_pclk = false,
	60	.max_prescaler = 256,
	61	};
	62
	63	static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
	64	.has_pclk = true,
	65	.max_prescaler = 1024,
	66	};
c2cf466c	67
4332d113 YF	68	struct stm32_iwdg {
4332d113 YF	69	struct watchdog_device wdd;
e9974166	70	const struct stm32_iwdg_data *data;
4332d113	71	void __iomem *regs;
c2cf466c LB	72	struct clk *clk_lsi;
c2cf466c LB	73	struct clk *clk_pclk;
4332d113 YF	74	unsigned int rate;
	75	};
	76
	77	static inline u32 reg_read(void __iomem *base, u32 reg)
	78	{
	79	return readl_relaxed(base + reg);
	80	}
	81
	82	static inline void reg_write(void __iomem *base, u32 reg, u32 val)
	83	{
	84	writel_relaxed(val, base + reg);
	85	}
	86
	87	static int stm32_iwdg_start(struct watchdog_device *wdd)
	88	{
	89	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
e9974166	90	u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
4332d113 YF	91	int ret;
	92
	93	dev_dbg(wdd->parent, "%s\n", __func__);
	94
e9974166 LB	95	tout = clamp_t(unsigned int, wdd->timeout,
	96	wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
	97
	98	presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
	99
	100	/* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
	101	presc = roundup_pow_of_two(presc);
	102	iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
	103	iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
4332d113 YF	104
	105	/* enable write access */
	106	reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
	107
	108	/* set prescaler & reload registers */
e9974166 LB	109	reg_write(wdt->regs, IWDG_PR, iwdg_pr);
e9974166 LB	110	reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
4332d113 YF	111	reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
	112
	113	/* wait for the registers to be updated (max 100ms) */
e9974166 LB	114	ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
e9974166 LB	115	!(iwdg_sr & (SR_PVU \| SR_RVU)),
4332d113 YF	116	SLEEP_US, TIMEOUT_US);
4332d113 YF	117	if (ret) {
e9974166	118	dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
4332d113 YF	119	return ret;
	120	}
	121
	122	/* reload watchdog */
	123	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
	124
	125	return 0;
	126	}
	127
	128	static int stm32_iwdg_ping(struct watchdog_device *wdd)
	129	{
	130	struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
	131
	132	dev_dbg(wdd->parent, "%s\n", __func__);
	133
	134	/* reload watchdog */
	135	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
	136
	137	return 0;
	138	}
	139
	140	static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
	141	unsigned int timeout)
	142	{
	143	dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
	144
	145	wdd->timeout = timeout;
	146
	147	if (watchdog_active(wdd))
	148	return stm32_iwdg_start(wdd);
	149
	150	return 0;
	151	}
	152
1f533058 GR	153	static void stm32_clk_disable_unprepare(void *data)
	154	{
	155	clk_disable_unprepare(data);
	156	}
	157
c2cf466c LB	158	static int stm32_iwdg_clk_init(struct platform_device *pdev,
	159	struct stm32_iwdg *wdt)
	160	{
1f533058	161	struct device *dev = &pdev->dev;
c2cf466c LB	162	u32 ret;
c2cf466c LB	163
1f533058	164	wdt->clk_lsi = devm_clk_get(dev, "lsi");
c2cf466c	165	if (IS_ERR(wdt->clk_lsi)) {
1f533058	166	dev_err(dev, "Unable to get lsi clock\n");
c2cf466c LB	167	return PTR_ERR(wdt->clk_lsi);
	168	}
	169
	170	/* optional peripheral clock */
e9974166	171	if (wdt->data->has_pclk) {
1f533058	172	wdt->clk_pclk = devm_clk_get(dev, "pclk");
c2cf466c	173	if (IS_ERR(wdt->clk_pclk)) {
1f533058	174	dev_err(dev, "Unable to get pclk clock\n");
c2cf466c LB	175	return PTR_ERR(wdt->clk_pclk);
	176	}
	177
	178	ret = clk_prepare_enable(wdt->clk_pclk);
	179	if (ret) {
1f533058	180	dev_err(dev, "Unable to prepare pclk clock\n");
c2cf466c LB	181	return ret;
c2cf466c LB	182	}
1f533058 GR	183	ret = devm_add_action_or_reset(dev,
	184	stm32_clk_disable_unprepare,
	185	wdt->clk_pclk);
	186	if (ret)
	187	return ret;
c2cf466c LB	188	}
	189
	190	ret = clk_prepare_enable(wdt->clk_lsi);
	191	if (ret) {
1f533058	192	dev_err(dev, "Unable to prepare lsi clock\n");
c2cf466c LB	193	return ret;
c2cf466c LB	194	}
1f533058 GR	195	ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
	196	wdt->clk_lsi);
	197	if (ret)
	198	return ret;
c2cf466c LB	199
	200	wdt->rate = clk_get_rate(wdt->clk_lsi);
	201
	202	return 0;
	203	}
	204
4332d113 YF	205	static const struct watchdog_info stm32_iwdg_info = {
	206	.options = WDIOF_SETTIMEOUT \|
	207	WDIOF_MAGICCLOSE \|
	208	WDIOF_KEEPALIVEPING,
	209	.identity = "STM32 Independent Watchdog",
	210	};
	211
d7b16e75	212	static const struct watchdog_ops stm32_iwdg_ops = {
4332d113 YF	213	.owner = THIS_MODULE,
	214	.start = stm32_iwdg_start,
	215	.ping = stm32_iwdg_ping,
	216	.set_timeout = stm32_iwdg_set_timeout,
	217	};
	218
c2cf466c	219	static const struct of_device_id stm32_iwdg_of_match[] = {
e9974166 LB	220	{ .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
e9974166 LB	221	{ .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
c2cf466c LB	222	{ /* end node */ }
	223	};
	224	MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
	225
4332d113 YF	226	static int stm32_iwdg_probe(struct platform_device *pdev)
4332d113 YF	227	{
1f533058	228	struct device *dev = &pdev->dev;
4332d113 YF	229	struct watchdog_device *wdd;
4332d113 YF	230	struct stm32_iwdg *wdt;
4332d113 YF	231	int ret;
4332d113 YF	232
1f533058	233	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
c2cf466c LB	234	if (!wdt)
	235	return -ENOMEM;
	236
e9974166 LB	237	wdt->data = of_device_get_match_data(&pdev->dev);
	238	if (!wdt->data)
	239	return -ENODEV;
c2cf466c	240
4332d113	241	/* This is the timer base. */
0f0a6a28	242	wdt->regs = devm_platform_ioremap_resource(pdev, 0);
c2cf466c	243	if (IS_ERR(wdt->regs)) {
1f533058	244	dev_err(dev, "Could not get resource\n");
c2cf466c	245	return PTR_ERR(wdt->regs);
4332d113 YF	246	}
4332d113 YF	247
c2cf466c LB	248	ret = stm32_iwdg_clk_init(pdev, wdt);
c2cf466c LB	249	if (ret)
4332d113	250	return ret;
4332d113 YF	251
	252	/* Initialize struct watchdog_device. */
	253	wdd = &wdt->wdd;
e9974166	254	wdd->parent = dev;
4332d113 YF	255	wdd->info = &stm32_iwdg_info;
4332d113 YF	256	wdd->ops = &stm32_iwdg_ops;
e9974166 LB	257	wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
	258	wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
	259	1000) / wdt->rate;
4332d113 YF	260
	261	watchdog_set_drvdata(wdd, wdt);
	262	watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
6781ce2e	263	watchdog_init_timeout(wdd, 0, dev);
4332d113	264
1f533058	265	ret = devm_watchdog_register_device(dev, wdd);
4332d113	266	if (ret) {
1f533058 GR	267	dev_err(dev, "failed to register watchdog device\n");
1f533058 GR	268	return ret;
4332d113 YF	269	}
	270
	271	platform_set_drvdata(pdev, wdt);
	272
4332d113 YF	273	return 0;
	274	}
	275
4332d113 YF	276	static struct platform_driver stm32_iwdg_driver = {
4332d113 YF	277	.probe = stm32_iwdg_probe,
4332d113 YF	278	.driver = {
4332d113 YF	279	.name = "iwdg",
c2cf466c	280	.of_match_table = of_match_ptr(stm32_iwdg_of_match),
4332d113 YF	281	},
	282	};
	283	module_platform_driver(stm32_iwdg_driver);
	284
	285	MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
	286	MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
	287	MODULE_LICENSE("GPL v2");