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49620a28 | 1 | // SPDX-License-Identifier: GPL-2.0 |
4332d113 YF |
2 | /* |
3 | * Driver for STM32 Independent Watchdog | |
4 | * | |
49620a28 BG |
5 | * Copyright (C) STMicroelectronics 2017 |
6 | * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics. | |
4332d113 YF |
7 | * |
8 | * This driver is based on tegra_wdt.c | |
9 | * | |
4332d113 YF |
10 | */ |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
4332d113 YF |
14 | #include <linux/interrupt.h> |
15 | #include <linux/io.h> | |
16 | #include <linux/iopoll.h> | |
c2cf466c LB |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> | |
4332d113 | 19 | #include <linux/of.h> |
c2cf466c | 20 | #include <linux/of_device.h> |
4332d113 YF |
21 | #include <linux/platform_device.h> |
22 | #include <linux/watchdog.h> | |
23 | ||
24 | /* IWDG registers */ | |
25 | #define IWDG_KR 0x00 /* Key register */ | |
26 | #define IWDG_PR 0x04 /* Prescaler Register */ | |
27 | #define IWDG_RLR 0x08 /* ReLoad Register */ | |
28 | #define IWDG_SR 0x0C /* Status Register */ | |
29 | #define IWDG_WINR 0x10 /* Windows Register */ | |
30 | ||
31 | /* IWDG_KR register bit mask */ | |
32 | #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */ | |
33 | #define KR_KEY_ENABLE 0xCCCC /* peripheral enable */ | |
34 | #define KR_KEY_EWA 0x5555 /* write access enable */ | |
35 | #define KR_KEY_DWA 0x0000 /* write access disable */ | |
36 | ||
e9974166 LB |
37 | /* IWDG_PR register */ |
38 | #define PR_SHIFT 2 | |
39 | #define PR_MIN BIT(PR_SHIFT) | |
4332d113 YF |
40 | |
41 | /* IWDG_RLR register values */ | |
e9974166 LB |
42 | #define RLR_MIN 0x2 /* min value recommended */ |
43 | #define RLR_MAX GENMASK(11, 0) /* max value of reload register */ | |
4332d113 YF |
44 | |
45 | /* IWDG_SR register bit mask */ | |
e9974166 LB |
46 | #define SR_PVU BIT(0) /* Watchdog prescaler value update */ |
47 | #define SR_RVU BIT(1) /* Watchdog counter reload value update */ | |
4332d113 YF |
48 | |
49 | /* set timeout to 100000 us */ | |
50 | #define TIMEOUT_US 100000 | |
51 | #define SLEEP_US 1000 | |
52 | ||
e9974166 LB |
53 | struct stm32_iwdg_data { |
54 | bool has_pclk; | |
55 | u32 max_prescaler; | |
56 | }; | |
57 | ||
58 | static const struct stm32_iwdg_data stm32_iwdg_data = { | |
59 | .has_pclk = false, | |
60 | .max_prescaler = 256, | |
61 | }; | |
62 | ||
63 | static const struct stm32_iwdg_data stm32mp1_iwdg_data = { | |
64 | .has_pclk = true, | |
65 | .max_prescaler = 1024, | |
66 | }; | |
c2cf466c | 67 | |
4332d113 YF |
68 | struct stm32_iwdg { |
69 | struct watchdog_device wdd; | |
e9974166 | 70 | const struct stm32_iwdg_data *data; |
4332d113 | 71 | void __iomem *regs; |
c2cf466c LB |
72 | struct clk *clk_lsi; |
73 | struct clk *clk_pclk; | |
4332d113 YF |
74 | unsigned int rate; |
75 | }; | |
76 | ||
77 | static inline u32 reg_read(void __iomem *base, u32 reg) | |
78 | { | |
79 | return readl_relaxed(base + reg); | |
80 | } | |
81 | ||
82 | static inline void reg_write(void __iomem *base, u32 reg, u32 val) | |
83 | { | |
84 | writel_relaxed(val, base + reg); | |
85 | } | |
86 | ||
87 | static int stm32_iwdg_start(struct watchdog_device *wdd) | |
88 | { | |
89 | struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd); | |
e9974166 | 90 | u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr; |
4332d113 YF |
91 | int ret; |
92 | ||
93 | dev_dbg(wdd->parent, "%s\n", __func__); | |
94 | ||
e9974166 LB |
95 | tout = clamp_t(unsigned int, wdd->timeout, |
96 | wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000); | |
97 | ||
98 | presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1); | |
99 | ||
100 | /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */ | |
101 | presc = roundup_pow_of_two(presc); | |
102 | iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT; | |
103 | iwdg_rlr = ((tout * wdt->rate) / presc) - 1; | |
4332d113 YF |
104 | |
105 | /* enable write access */ | |
106 | reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA); | |
107 | ||
108 | /* set prescaler & reload registers */ | |
e9974166 LB |
109 | reg_write(wdt->regs, IWDG_PR, iwdg_pr); |
110 | reg_write(wdt->regs, IWDG_RLR, iwdg_rlr); | |
4332d113 YF |
111 | reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE); |
112 | ||
113 | /* wait for the registers to be updated (max 100ms) */ | |
e9974166 LB |
114 | ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr, |
115 | !(iwdg_sr & (SR_PVU | SR_RVU)), | |
4332d113 YF |
116 | SLEEP_US, TIMEOUT_US); |
117 | if (ret) { | |
e9974166 | 118 | dev_err(wdd->parent, "Fail to set prescaler, reload regs\n"); |
4332d113 YF |
119 | return ret; |
120 | } | |
121 | ||
122 | /* reload watchdog */ | |
123 | reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); | |
124 | ||
125 | return 0; | |
126 | } | |
127 | ||
128 | static int stm32_iwdg_ping(struct watchdog_device *wdd) | |
129 | { | |
130 | struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd); | |
131 | ||
132 | dev_dbg(wdd->parent, "%s\n", __func__); | |
133 | ||
134 | /* reload watchdog */ | |
135 | reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
140 | static int stm32_iwdg_set_timeout(struct watchdog_device *wdd, | |
141 | unsigned int timeout) | |
142 | { | |
143 | dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout); | |
144 | ||
145 | wdd->timeout = timeout; | |
146 | ||
147 | if (watchdog_active(wdd)) | |
148 | return stm32_iwdg_start(wdd); | |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
1f533058 GR |
153 | static void stm32_clk_disable_unprepare(void *data) |
154 | { | |
155 | clk_disable_unprepare(data); | |
156 | } | |
157 | ||
c2cf466c LB |
158 | static int stm32_iwdg_clk_init(struct platform_device *pdev, |
159 | struct stm32_iwdg *wdt) | |
160 | { | |
1f533058 | 161 | struct device *dev = &pdev->dev; |
c2cf466c LB |
162 | u32 ret; |
163 | ||
1f533058 | 164 | wdt->clk_lsi = devm_clk_get(dev, "lsi"); |
7c7164f9 EC |
165 | if (IS_ERR(wdt->clk_lsi)) |
166 | return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n"); | |
c2cf466c LB |
167 | |
168 | /* optional peripheral clock */ | |
e9974166 | 169 | if (wdt->data->has_pclk) { |
1f533058 | 170 | wdt->clk_pclk = devm_clk_get(dev, "pclk"); |
7c7164f9 EC |
171 | if (IS_ERR(wdt->clk_pclk)) |
172 | return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk), | |
173 | "Unable to get pclk clock\n"); | |
c2cf466c LB |
174 | |
175 | ret = clk_prepare_enable(wdt->clk_pclk); | |
176 | if (ret) { | |
1f533058 | 177 | dev_err(dev, "Unable to prepare pclk clock\n"); |
c2cf466c LB |
178 | return ret; |
179 | } | |
1f533058 GR |
180 | ret = devm_add_action_or_reset(dev, |
181 | stm32_clk_disable_unprepare, | |
182 | wdt->clk_pclk); | |
183 | if (ret) | |
184 | return ret; | |
c2cf466c LB |
185 | } |
186 | ||
187 | ret = clk_prepare_enable(wdt->clk_lsi); | |
188 | if (ret) { | |
1f533058 | 189 | dev_err(dev, "Unable to prepare lsi clock\n"); |
c2cf466c LB |
190 | return ret; |
191 | } | |
1f533058 GR |
192 | ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare, |
193 | wdt->clk_lsi); | |
194 | if (ret) | |
195 | return ret; | |
c2cf466c LB |
196 | |
197 | wdt->rate = clk_get_rate(wdt->clk_lsi); | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
4332d113 YF |
202 | static const struct watchdog_info stm32_iwdg_info = { |
203 | .options = WDIOF_SETTIMEOUT | | |
204 | WDIOF_MAGICCLOSE | | |
205 | WDIOF_KEEPALIVEPING, | |
206 | .identity = "STM32 Independent Watchdog", | |
207 | }; | |
208 | ||
d7b16e75 | 209 | static const struct watchdog_ops stm32_iwdg_ops = { |
4332d113 YF |
210 | .owner = THIS_MODULE, |
211 | .start = stm32_iwdg_start, | |
212 | .ping = stm32_iwdg_ping, | |
213 | .set_timeout = stm32_iwdg_set_timeout, | |
214 | }; | |
215 | ||
c2cf466c | 216 | static const struct of_device_id stm32_iwdg_of_match[] = { |
e9974166 LB |
217 | { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data }, |
218 | { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data }, | |
c2cf466c LB |
219 | { /* end node */ } |
220 | }; | |
221 | MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match); | |
222 | ||
4332d113 YF |
223 | static int stm32_iwdg_probe(struct platform_device *pdev) |
224 | { | |
1f533058 | 225 | struct device *dev = &pdev->dev; |
4332d113 YF |
226 | struct watchdog_device *wdd; |
227 | struct stm32_iwdg *wdt; | |
4332d113 YF |
228 | int ret; |
229 | ||
1f533058 | 230 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
c2cf466c LB |
231 | if (!wdt) |
232 | return -ENOMEM; | |
233 | ||
e9974166 LB |
234 | wdt->data = of_device_get_match_data(&pdev->dev); |
235 | if (!wdt->data) | |
236 | return -ENODEV; | |
c2cf466c | 237 | |
4332d113 | 238 | /* This is the timer base. */ |
0f0a6a28 | 239 | wdt->regs = devm_platform_ioremap_resource(pdev, 0); |
004920df | 240 | if (IS_ERR(wdt->regs)) |
c2cf466c | 241 | return PTR_ERR(wdt->regs); |
4332d113 | 242 | |
c2cf466c LB |
243 | ret = stm32_iwdg_clk_init(pdev, wdt); |
244 | if (ret) | |
4332d113 | 245 | return ret; |
4332d113 YF |
246 | |
247 | /* Initialize struct watchdog_device. */ | |
248 | wdd = &wdt->wdd; | |
e9974166 | 249 | wdd->parent = dev; |
4332d113 YF |
250 | wdd->info = &stm32_iwdg_info; |
251 | wdd->ops = &stm32_iwdg_ops; | |
e9974166 LB |
252 | wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate); |
253 | wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler * | |
254 | 1000) / wdt->rate; | |
4332d113 YF |
255 | |
256 | watchdog_set_drvdata(wdd, wdt); | |
257 | watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT); | |
6781ce2e | 258 | watchdog_init_timeout(wdd, 0, dev); |
4332d113 | 259 | |
85fdc63f CR |
260 | /* |
261 | * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set | |
262 | * (Means U-Boot/bootloaders leaves the watchdog running) | |
263 | * When we get here we should make a decision to prevent | |
264 | * any side effects before user space daemon will take care of it. | |
265 | * The best option, taking into consideration that there is no | |
266 | * way to read values back from hardware, is to enforce watchdog | |
267 | * being run with deterministic values. | |
268 | */ | |
269 | if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) { | |
270 | ret = stm32_iwdg_start(wdd); | |
271 | if (ret) | |
272 | return ret; | |
273 | ||
274 | /* Make sure the watchdog is serviced */ | |
275 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
276 | } | |
277 | ||
1f533058 | 278 | ret = devm_watchdog_register_device(dev, wdd); |
71777442 | 279 | if (ret) |
1f533058 | 280 | return ret; |
4332d113 YF |
281 | |
282 | platform_set_drvdata(pdev, wdt); | |
283 | ||
4332d113 YF |
284 | return 0; |
285 | } | |
286 | ||
4332d113 YF |
287 | static struct platform_driver stm32_iwdg_driver = { |
288 | .probe = stm32_iwdg_probe, | |
4332d113 YF |
289 | .driver = { |
290 | .name = "iwdg", | |
c2cf466c | 291 | .of_match_table = of_match_ptr(stm32_iwdg_of_match), |
4332d113 YF |
292 | }, |
293 | }; | |
294 | module_platform_driver(stm32_iwdg_driver); | |
295 | ||
296 | MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); | |
297 | MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver"); | |
298 | MODULE_LICENSE("GPL v2"); |