[linux-2.6-block.git] / drivers / watchdog / sp805_wdt.c

/*
 * drivers/char/watchdog/sp805-wdt.c
 *
 * Watchdog driver for ARM SP805 watchdog module
 *
 * Copyright (C) 2010 ST Microelectronics
 * Viresh Kumar <vireshk@kernel.org>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2 or later. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/device.h>
#include <linux/resource.h>
#include <linux/amba/bus.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/watchdog.h>

/* default timeout in seconds */
#define DEFAULT_TIMEOUT		60

#define MODULE_NAME		"sp805-wdt"

/* watchdog register offsets and masks */
#define WDTLOAD			0x000
	#define LOAD_MIN	0x00000001
	#define LOAD_MAX	0xFFFFFFFF
#define WDTVALUE		0x004
#define WDTCONTROL		0x008
	/* control register masks */
	#define	INT_ENABLE	(1 << 0)
	#define	RESET_ENABLE	(1 << 1)
	#define	ENABLE_MASK	(INT_ENABLE | RESET_ENABLE)
#define WDTINTCLR		0x00C
#define WDTRIS			0x010
#define WDTMIS			0x014
	#define INT_MASK	(1 << 0)
#define WDTLOCK			0xC00
	#define	UNLOCK		0x1ACCE551
	#define	LOCK		0x00000001

/**
 * struct sp805_wdt: sp805 wdt device structure
 * @wdd: instance of struct watchdog_device
 * @lock: spin lock protecting dev structure and io access
 * @base: base address of wdt
 * @clk: (optional) clock structure of wdt
 * @rate: (optional) clock rate when provided via properties
 * @adev: amba device structure of wdt
 * @status: current status of wdt
 * @load_val: load value to be set for current timeout
 */
struct sp805_wdt {
	struct watchdog_device		wdd;
	spinlock_t			lock;
	void __iomem			*base;
	struct clk			*clk;
	u64				rate;
	struct amba_device		*adev;
	unsigned int			load_val;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
		"Set to 1 to keep watchdog running after device release");

/* returns true if wdt is running; otherwise returns false */
static bool wdt_is_running(struct watchdog_device *wdd)
{
	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
	u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);

	return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
}

/* This routine finds load value that will reset system in required timout */
static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
{
	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
	u64 load, rate;

	rate = wdt->rate;

	/*
	 * sp805 runs counter with given value twice, after the end of first
	 * counter it gives an interrupt and then starts counter again. If
	 * interrupt already occurred then it resets the system. This is why
	 * load is half of what should be required.
	 */
	load = div_u64(rate, 2) * timeout - 1;

	load = (load > LOAD_MAX) ? LOAD_MAX : load;
	load = (load < LOAD_MIN) ? LOAD_MIN : load;

	spin_lock(&wdt->lock);
	wdt->load_val = load;
	/* roundup timeout to closest positive integer value */
	wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
	spin_unlock(&wdt->lock);

	return 0;
}

/* returns number of seconds left for reset to occur */
static unsigned int wdt_timeleft(struct watchdog_device *wdd)
{
	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
	u64 load;

	spin_lock(&wdt->lock);
	load = readl_relaxed(wdt->base + WDTVALUE);

	/*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
	if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
		load += wdt->load_val + 1;
	spin_unlock(&wdt->lock);

	return div_u64(load, wdt->rate);
}

static int
wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd)
{
	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);

	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
	writel_relaxed(0, wdt->base + WDTCONTROL);
	writel_relaxed(0, wdt->base + WDTLOAD);
	writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);

	/* Flush posted writes. */
	readl_relaxed(wdt->base + WDTLOCK);

	return 0;
}

static int wdt_config(struct watchdog_device *wdd, bool ping)
{
	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
	int ret;

	if (!ping) {

		ret = clk_prepare_enable(wdt->clk);
		if (ret) {
			dev_err(&wdt->adev->dev, "clock enable fail");
			return ret;
		}
	}

	spin_lock(&wdt->lock);

	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
	writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
	writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);

	if (!ping)
		writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
				WDTCONTROL);

	writel_relaxed(LOCK, wdt->base + WDTLOCK);

	/* Flush posted writes. */
	readl_relaxed(wdt->base + WDTLOCK);
	spin_unlock(&wdt->lock);

	return 0;
}

static int wdt_ping(struct watchdog_device *wdd)
{
	return wdt_config(wdd, true);
}

/* enables watchdog timers reset */
static int wdt_enable(struct watchdog_device *wdd)
{
	return wdt_config(wdd, false);
}

/* disables watchdog timers reset */
static int wdt_disable(struct watchdog_device *wdd)
{
	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);

	spin_lock(&wdt->lock);

	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
	writel_relaxed(0, wdt->base + WDTCONTROL);
	writel_relaxed(LOCK, wdt->base + WDTLOCK);

	/* Flush posted writes. */
	readl_relaxed(wdt->base + WDTLOCK);
	spin_unlock(&wdt->lock);

	clk_disable_unprepare(wdt->clk);

	return 0;
}

static const struct watchdog_info wdt_info = {
	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
	.identity = MODULE_NAME,
};

static const struct watchdog_ops wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= wdt_enable,
	.stop		= wdt_disable,
	.ping		= wdt_ping,
	.set_timeout	= wdt_setload,
	.get_timeleft	= wdt_timeleft,
	.restart	= wdt_restart,
};

static int
sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct sp805_wdt *wdt;
	u64 rate = 0;
	int ret = 0;

	wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt) {
		ret = -ENOMEM;
		goto err;
	}

	wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	/*
	 * When driver probe with ACPI device, clock devices
	 * are not available, so watchdog rate get from
	 * clock-frequency property given in _DSD object.
	 */
	device_property_read_u64(&adev->dev, "clock-frequency", &rate);

	wdt->clk = devm_clk_get_optional(&adev->dev, NULL);
	if (IS_ERR(wdt->clk))
		return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n");

	wdt->rate = clk_get_rate(wdt->clk);
	if (!wdt->rate)
		wdt->rate = rate;
	if (!wdt->rate) {
		dev_err(&adev->dev, "no clock-frequency property\n");
		return -ENODEV;
	}

	wdt->adev = adev;
	wdt->wdd.info = &wdt_info;
	wdt->wdd.ops = &wdt_ops;
	wdt->wdd.parent = &adev->dev;

	spin_lock_init(&wdt->lock);
	watchdog_set_nowayout(&wdt->wdd, nowayout);
	watchdog_set_drvdata(&wdt->wdd, wdt);
	watchdog_set_restart_priority(&wdt->wdd, 128);
	watchdog_stop_on_unregister(&wdt->wdd);

	/*
	 * If 'timeout-sec' devicetree property is specified, use that.
	 * Otherwise, use DEFAULT_TIMEOUT
	 */
	wdt->wdd.timeout = DEFAULT_TIMEOUT;
	watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
	wdt_setload(&wdt->wdd, wdt->wdd.timeout);

	/*
	 * If HW is already running, enable/reset the wdt and set the running
	 * bit to tell the wdt subsystem
	 */
	if (wdt_is_running(&wdt->wdd)) {
		wdt_enable(&wdt->wdd);
		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	}

	watchdog_stop_on_reboot(&wdt->wdd);
	ret = watchdog_register_device(&wdt->wdd);
	if (ret)
		goto err;
	amba_set_drvdata(adev, wdt);

	dev_info(&adev->dev, "registration successful\n");
	return 0;

err:
	dev_err(&adev->dev, "Probe Failed!!!\n");
	return ret;
}

static void sp805_wdt_remove(struct amba_device *adev)
{
	struct sp805_wdt *wdt = amba_get_drvdata(adev);

	watchdog_unregister_device(&wdt->wdd);
	watchdog_set_drvdata(&wdt->wdd, NULL);
}

static int __maybe_unused sp805_wdt_suspend(struct device *dev)
{
	struct sp805_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		return wdt_disable(&wdt->wdd);

	return 0;
}

static int __maybe_unused sp805_wdt_resume(struct device *dev)
{
	struct sp805_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		return wdt_enable(&wdt->wdd);

	return 0;
}

static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
		sp805_wdt_resume);

static const struct amba_id sp805_wdt_ids[] = {
	{
		.id	= 0x00141805,
		.mask	= 0x00ffffff,
	},
	{ 0, 0 },
};

MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);

static struct amba_driver sp805_wdt_driver = {
	.drv = {
		.name	= MODULE_NAME,
		.pm	= &sp805_wdt_dev_pm_ops,
	},
	.id_table	= sp805_wdt_ids,
	.probe		= sp805_wdt_probe,
	.remove = sp805_wdt_remove,
};

module_amba_driver(sp805_wdt_driver);

MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
4a370278 VK	1	/*
	2	* drivers/char/watchdog/sp805-wdt.c
	3	*
	4	* Watchdog driver for ARM SP805 watchdog module
	5	*
	6	* Copyright (C) 2010 ST Microelectronics
da89947b	7	* Viresh Kumar <vireshk@kernel.org>
4a370278 VK	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2 or later. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include <linux/device.h>
	15	#include <linux/resource.h>
	16	#include <linux/amba/bus.h>
	17	#include <linux/bitops.h>
	18	#include <linux/clk.h>
4a370278 VK	19	#include <linux/io.h>
	20	#include <linux/ioport.h>
	21	#include <linux/kernel.h>
	22	#include <linux/math64.h>
4a370278 VK	23	#include <linux/module.h>
4a370278 VK	24	#include <linux/moduleparam.h>
16ac4abe	25	#include <linux/pm.h>
05f0a994	26	#include <linux/property.h>
4a370278 VK	27	#include <linux/slab.h>
	28	#include <linux/spinlock.h>
	29	#include <linux/types.h>
4a370278 VK	30	#include <linux/watchdog.h>
	31
	32	/* default timeout in seconds */
	33	#define DEFAULT_TIMEOUT 60
	34
	35	#define MODULE_NAME "sp805-wdt"
	36
	37	/* watchdog register offsets and masks */
	38	#define WDTLOAD 0x000
	39	#define LOAD_MIN 0x00000001
	40	#define LOAD_MAX 0xFFFFFFFF
	41	#define WDTVALUE 0x004
	42	#define WDTCONTROL 0x008
	43	/* control register masks */
	44	#define INT_ENABLE (1 << 0)
	45	#define RESET_ENABLE (1 << 1)
fa5072ed	46	#define ENABLE_MASK (INT_ENABLE \| RESET_ENABLE)
4a370278 VK	47	#define WDTINTCLR 0x00C
	48	#define WDTRIS 0x010
	49	#define WDTMIS 0x014
	50	#define INT_MASK (1 << 0)
	51	#define WDTLOCK 0xC00
	52	#define UNLOCK 0x1ACCE551
	53	#define LOCK 0x00000001
	54
	55	/**
	56	* struct sp805_wdt: sp805 wdt device structure
4a516539	57	* @wdd: instance of struct watchdog_device
bfae14b6 VK	58	* @lock: spin lock protecting dev structure and io access
bfae14b6 VK	59	* @base: base address of wdt
3452239e AS	60	* @clk: (optional) clock structure of wdt
3452239e AS	61	* @rate: (optional) clock rate when provided via properties
bfae14b6 VK	62	* @adev: amba device structure of wdt
	63	* @status: current status of wdt
	64	* @load_val: load value to be set for current timeout
4a370278 VK	65	*/
4a370278 VK	66	struct sp805_wdt {
4a516539	67	struct watchdog_device wdd;
4a370278 VK	68	spinlock_t lock;
	69	void __iomem *base;
	70	struct clk *clk;
dc0e4a3b	71	u64 rate;
4a370278	72	struct amba_device *adev;
4a370278	73	unsigned int load_val;
4a370278 VK	74	};
4a370278 VK	75
86a1e189	76	static bool nowayout = WATCHDOG_NOWAYOUT;
4a516539 VK	77	module_param(nowayout, bool, 0);
	78	MODULE_PARM_DESC(nowayout,
	79	"Set to 1 to keep watchdog running after device release");
4a370278	80
fa5072ed RJ	81	/* returns true if wdt is running; otherwise returns false */
	82	static bool wdt_is_running(struct watchdog_device *wdd)
	83	{
	84	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
	85	u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
	86
	87	return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
	88	}
	89
4a370278	90	/* This routine finds load value that will reset system in required timout */
4a516539	91	static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
4a370278	92	{
4a516539	93	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
4a370278 VK	94	u64 load, rate;
4a370278 VK	95
dc0e4a3b	96	rate = wdt->rate;
4a370278 VK	97
	98	/*
	99	* sp805 runs counter with given value twice, after the end of first
	100	* counter it gives an interrupt and then starts counter again. If
25985edc	101	* interrupt already occurred then it resets the system. This is why
4a370278 VK	102	* load is half of what should be required.
	103	*/
	104	load = div_u64(rate, 2) * timeout - 1;
	105
	106	load = (load > LOAD_MAX) ? LOAD_MAX : load;
	107	load = (load < LOAD_MIN) ? LOAD_MIN : load;
	108
	109	spin_lock(&wdt->lock);
	110	wdt->load_val = load;
	111	/* roundup timeout to closest positive integer value */
938626d9	112	wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
4a370278	113	spin_unlock(&wdt->lock);
4a516539 VK	114
4a516539 VK	115	return 0;
4a370278 VK	116	}
	117
	118	/* returns number of seconds left for reset to occur */
4a516539	119	static unsigned int wdt_timeleft(struct watchdog_device *wdd)
4a370278	120	{
4a516539	121	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
dc0e4a3b	122	u64 load;
4a370278 VK	123
4a370278 VK	124	spin_lock(&wdt->lock);
d2e8919b	125	load = readl_relaxed(wdt->base + WDTVALUE);
4a370278 VK	126
4a370278 VK	127	/If the interrupt is inactive then time left is WDTValue + WDTLoad. /
d2e8919b	128	if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
4a370278 VK	129	load += wdt->load_val + 1;
	130	spin_unlock(&wdt->lock);
	131
dc0e4a3b	132	return div_u64(load, wdt->rate);
4a370278 VK	133	}
4a370278 VK	134
6c5c0d48 JK	135	static int
	136	wdt_restart(struct watchdog_device wdd, unsigned long mode, void cmd)
	137	{
	138	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
	139
ea104a9e	140	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
6c5c0d48 JK	141	writel_relaxed(0, wdt->base + WDTCONTROL);
	142	writel_relaxed(0, wdt->base + WDTLOAD);
	143	writel_relaxed(INT_ENABLE \| RESET_ENABLE, wdt->base + WDTCONTROL);
	144
ea104a9e MW	145	/* Flush posted writes. */
	146	readl_relaxed(wdt->base + WDTLOCK);
	147
6c5c0d48 JK	148	return 0;
	149	}
	150
4a516539	151	static int wdt_config(struct watchdog_device *wdd, bool ping)
4a370278	152	{
4a516539 VK	153	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
	154	int ret;
	155
	156	if (!ping) {
d9df0ef1	157
63fbbc16	158	ret = clk_prepare_enable(wdt->clk);
4a516539 VK	159	if (ret) {
	160	dev_err(&wdt->adev->dev, "clock enable fail");
	161	return ret;
	162	}
	163	}
	164
4a370278 VK	165	spin_lock(&wdt->lock);
4a370278 VK	166
d2e8919b VK	167	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
d2e8919b VK	168	writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
55e07177	169	writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
4a370278	170
55e07177	171	if (!ping)
4a516539 VK	172	writel_relaxed(INT_ENABLE \| RESET_ENABLE, wdt->base +
4a516539 VK	173	WDTCONTROL);
4a370278	174
d2e8919b	175	writel_relaxed(LOCK, wdt->base + WDTLOCK);
4a370278	176
081d83a3	177	/* Flush posted writes. */
d2e8919b	178	readl_relaxed(wdt->base + WDTLOCK);
4a370278	179	spin_unlock(&wdt->lock);
4a516539 VK	180
4a516539 VK	181	return 0;
4a370278 VK	182	}
4a370278 VK	183
4a516539	184	static int wdt_ping(struct watchdog_device *wdd)
4a370278	185	{
4a516539	186	return wdt_config(wdd, true);
4a370278 VK	187	}
4a370278 VK	188
4a516539 VK	189	/* enables watchdog timers reset */
4a516539 VK	190	static int wdt_enable(struct watchdog_device *wdd)
4a370278	191	{
4a516539	192	return wdt_config(wdd, false);
4a370278 VK	193	}
4a370278 VK	194
4a516539 VK	195	/* disables watchdog timers reset */
4a516539 VK	196	static int wdt_disable(struct watchdog_device *wdd)
4a370278	197	{
4a516539	198	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
4a370278	199
4a516539	200	spin_lock(&wdt->lock);
4a370278	201
4a516539 VK	202	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
	203	writel_relaxed(0, wdt->base + WDTCONTROL);
	204	writel_relaxed(LOCK, wdt->base + WDTLOCK);
4a370278	205
4a516539 VK	206	/* Flush posted writes. */
	207	readl_relaxed(wdt->base + WDTLOCK);
	208	spin_unlock(&wdt->lock);
4a370278	209
63fbbc16	210	clk_disable_unprepare(wdt->clk);
4a370278 VK	211
	212	return 0;
	213	}
	214
4a516539 VK	215	static const struct watchdog_info wdt_info = {
	216	.options = WDIOF_MAGICCLOSE \| WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING,
	217	.identity = MODULE_NAME,
4a370278 VK	218	};
4a370278 VK	219
4a516539 VK	220	static const struct watchdog_ops wdt_ops = {
	221	.owner = THIS_MODULE,
	222	.start = wdt_enable,
	223	.stop = wdt_disable,
	224	.ping = wdt_ping,
	225	.set_timeout = wdt_setload,
	226	.get_timeleft = wdt_timeleft,
6c5c0d48	227	.restart = wdt_restart,
4a370278 VK	228	};
4a370278 VK	229
2d991a16	230	static int
aa25afad	231	sp805_wdt_probe(struct amba_device adev, const struct amba_id id)
4a370278	232	{
4a516539	233	struct sp805_wdt *wdt;
05f0a994	234	u64 rate = 0;
4a370278 VK	235	int ret = 0;
4a370278 VK	236
fb35a5ad	237	wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
4a370278	238	if (!wdt) {
4a370278	239	ret = -ENOMEM;
fb35a5ad VK	240	goto err;
	241	}
	242
9d11e4f8 JH	243	wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
	244	if (IS_ERR(wdt->base))
	245	return PTR_ERR(wdt->base);
4a370278	246
05f0a994 AS	247	/*
	248	* When driver probe with ACPI device, clock devices
	249	* are not available, so watchdog rate get from
	250	* clock-frequency property given in _DSD object.
	251	*/
	252	device_property_read_u64(&adev->dev, "clock-frequency", &rate);
	253
	254	wdt->clk = devm_clk_get_optional(&adev->dev, NULL);
	255	if (IS_ERR(wdt->clk))
	256	return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n");
	257
	258	wdt->rate = clk_get_rate(wdt->clk);
	259	if (!wdt->rate)
	260	wdt->rate = rate;
	261	if (!wdt->rate) {
	262	dev_err(&adev->dev, "no clock-frequency property\n");
	263	return -ENODEV;
4a370278 VK	264	}
	265
	266	wdt->adev = adev;
4a516539 VK	267	wdt->wdd.info = &wdt_info;
4a516539 VK	268	wdt->wdd.ops = &wdt_ops;
6551881c	269	wdt->wdd.parent = &adev->dev;
4a516539	270
4a370278	271	spin_lock_init(&wdt->lock);
4a516539 VK	272	watchdog_set_nowayout(&wdt->wdd, nowayout);
4a516539 VK	273	watchdog_set_drvdata(&wdt->wdd, wdt);
6c5c0d48	274	watchdog_set_restart_priority(&wdt->wdd, 128);
ac97c937	275	watchdog_stop_on_unregister(&wdt->wdd);
b8008858 RJ	276
	277	/*
	278	* If 'timeout-sec' devicetree property is specified, use that.
	279	* Otherwise, use DEFAULT_TIMEOUT
	280	*/
	281	wdt->wdd.timeout = DEFAULT_TIMEOUT;
	282	watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
	283	wdt_setload(&wdt->wdd, wdt->wdd.timeout);
4a370278	284
fa5072ed RJ	285	/*
	286	* If HW is already running, enable/reset the wdt and set the running
	287	* bit to tell the wdt subsystem
	288	*/
	289	if (wdt_is_running(&wdt->wdd)) {
	290	wdt_enable(&wdt->wdd);
	291	set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	292	}
	293
42e967f3	294	watchdog_stop_on_reboot(&wdt->wdd);
4a516539	295	ret = watchdog_register_device(&wdt->wdd);
199801cd	296	if (ret)
07bf971a	297	goto err;
4a516539	298	amba_set_drvdata(adev, wdt);
4a370278 VK	299
	300	dev_info(&adev->dev, "registration successful\n");
	301	return 0;
	302
4a370278 VK	303	err:
	304	dev_err(&adev->dev, "Probe Failed!!!\n");
	305	return ret;
	306	}
	307
3fd269e7	308	static void sp805_wdt_remove(struct amba_device *adev)
4a370278	309	{
4a516539 VK	310	struct sp805_wdt *wdt = amba_get_drvdata(adev);
	311
	312	watchdog_unregister_device(&wdt->wdd);
4a516539	313	watchdog_set_drvdata(&wdt->wdd, NULL);
4a370278 VK	314	}
4a370278 VK	315
60d6dd53	316	static int __maybe_unused sp805_wdt_suspend(struct device *dev)
16ac4abe	317	{
4a516539 VK	318	struct sp805_wdt *wdt = dev_get_drvdata(dev);
	319
	320	if (watchdog_active(&wdt->wdd))
	321	return wdt_disable(&wdt->wdd);
16ac4abe VK	322
	323	return 0;
	324	}
	325
60d6dd53	326	static int __maybe_unused sp805_wdt_resume(struct device *dev)
16ac4abe	327	{
4a516539	328	struct sp805_wdt *wdt = dev_get_drvdata(dev);
16ac4abe	329
4a516539 VK	330	if (watchdog_active(&wdt->wdd))
4a516539 VK	331	return wdt_enable(&wdt->wdd);
16ac4abe	332
4a516539	333	return 0;
16ac4abe	334	}
16ac4abe VK	335
	336	static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
	337	sp805_wdt_resume);
	338
05ce42ff	339	static const struct amba_id sp805_wdt_ids[] = {
4a370278 VK	340	{
	341	.id = 0x00141805,
	342	.mask = 0x00ffffff,
	343	},
	344	{ 0, 0 },
	345	};
	346
17885b05 DM	347	MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);
17885b05 DM	348
4a370278 VK	349	static struct amba_driver sp805_wdt_driver = {
	350	.drv = {
	351	.name = MODULE_NAME,
16ac4abe	352	.pm = &sp805_wdt_dev_pm_ops,
4a370278 VK	353	},
	354	.id_table = sp805_wdt_ids,
	355	.probe = sp805_wdt_probe,
82268714	356	.remove = sp805_wdt_remove,
4a370278 VK	357	};
4a370278 VK	358
9e5ed094	359	module_amba_driver(sp805_wdt_driver);
4a370278	360
da89947b	361	MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
4a370278 VK	362	MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
4a370278 VK	363	MODULE_LICENSE("GPL");