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4a370278 VK |
1 | /* |
2 | * drivers/char/watchdog/sp805-wdt.c | |
3 | * | |
4 | * Watchdog driver for ARM SP805 watchdog module | |
5 | * | |
6 | * Copyright (C) 2010 ST Microelectronics | |
da89947b | 7 | * Viresh Kumar <vireshk@kernel.org> |
4a370278 VK |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2 or later. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/resource.h> | |
16 | #include <linux/amba/bus.h> | |
17 | #include <linux/bitops.h> | |
18 | #include <linux/clk.h> | |
4a370278 VK |
19 | #include <linux/io.h> |
20 | #include <linux/ioport.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/math64.h> | |
4a370278 VK |
23 | #include <linux/module.h> |
24 | #include <linux/moduleparam.h> | |
16ac4abe | 25 | #include <linux/pm.h> |
4a370278 VK |
26 | #include <linux/slab.h> |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/types.h> | |
4a370278 VK |
29 | #include <linux/watchdog.h> |
30 | ||
31 | /* default timeout in seconds */ | |
32 | #define DEFAULT_TIMEOUT 60 | |
33 | ||
34 | #define MODULE_NAME "sp805-wdt" | |
35 | ||
36 | /* watchdog register offsets and masks */ | |
37 | #define WDTLOAD 0x000 | |
38 | #define LOAD_MIN 0x00000001 | |
39 | #define LOAD_MAX 0xFFFFFFFF | |
40 | #define WDTVALUE 0x004 | |
41 | #define WDTCONTROL 0x008 | |
42 | /* control register masks */ | |
43 | #define INT_ENABLE (1 << 0) | |
44 | #define RESET_ENABLE (1 << 1) | |
45 | #define WDTINTCLR 0x00C | |
46 | #define WDTRIS 0x010 | |
47 | #define WDTMIS 0x014 | |
48 | #define INT_MASK (1 << 0) | |
49 | #define WDTLOCK 0xC00 | |
50 | #define UNLOCK 0x1ACCE551 | |
51 | #define LOCK 0x00000001 | |
52 | ||
53 | /** | |
54 | * struct sp805_wdt: sp805 wdt device structure | |
4a516539 | 55 | * @wdd: instance of struct watchdog_device |
bfae14b6 VK |
56 | * @lock: spin lock protecting dev structure and io access |
57 | * @base: base address of wdt | |
58 | * @clk: clock structure of wdt | |
59 | * @adev: amba device structure of wdt | |
60 | * @status: current status of wdt | |
61 | * @load_val: load value to be set for current timeout | |
4a370278 VK |
62 | */ |
63 | struct sp805_wdt { | |
4a516539 | 64 | struct watchdog_device wdd; |
4a370278 VK |
65 | spinlock_t lock; |
66 | void __iomem *base; | |
67 | struct clk *clk; | |
68 | struct amba_device *adev; | |
4a370278 | 69 | unsigned int load_val; |
4a370278 VK |
70 | }; |
71 | ||
86a1e189 | 72 | static bool nowayout = WATCHDOG_NOWAYOUT; |
4a516539 VK |
73 | module_param(nowayout, bool, 0); |
74 | MODULE_PARM_DESC(nowayout, | |
75 | "Set to 1 to keep watchdog running after device release"); | |
4a370278 VK |
76 | |
77 | /* This routine finds load value that will reset system in required timout */ | |
4a516539 | 78 | static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout) |
4a370278 | 79 | { |
4a516539 | 80 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
4a370278 VK |
81 | u64 load, rate; |
82 | ||
83 | rate = clk_get_rate(wdt->clk); | |
84 | ||
85 | /* | |
86 | * sp805 runs counter with given value twice, after the end of first | |
87 | * counter it gives an interrupt and then starts counter again. If | |
25985edc | 88 | * interrupt already occurred then it resets the system. This is why |
4a370278 VK |
89 | * load is half of what should be required. |
90 | */ | |
91 | load = div_u64(rate, 2) * timeout - 1; | |
92 | ||
93 | load = (load > LOAD_MAX) ? LOAD_MAX : load; | |
94 | load = (load < LOAD_MIN) ? LOAD_MIN : load; | |
95 | ||
96 | spin_lock(&wdt->lock); | |
97 | wdt->load_val = load; | |
98 | /* roundup timeout to closest positive integer value */ | |
938626d9 | 99 | wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate); |
4a370278 | 100 | spin_unlock(&wdt->lock); |
4a516539 VK |
101 | |
102 | return 0; | |
4a370278 VK |
103 | } |
104 | ||
105 | /* returns number of seconds left for reset to occur */ | |
4a516539 | 106 | static unsigned int wdt_timeleft(struct watchdog_device *wdd) |
4a370278 | 107 | { |
4a516539 | 108 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
4a370278 VK |
109 | u64 load, rate; |
110 | ||
111 | rate = clk_get_rate(wdt->clk); | |
112 | ||
113 | spin_lock(&wdt->lock); | |
d2e8919b | 114 | load = readl_relaxed(wdt->base + WDTVALUE); |
4a370278 VK |
115 | |
116 | /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */ | |
d2e8919b | 117 | if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK)) |
4a370278 VK |
118 | load += wdt->load_val + 1; |
119 | spin_unlock(&wdt->lock); | |
120 | ||
121 | return div_u64(load, rate); | |
122 | } | |
123 | ||
6c5c0d48 JK |
124 | static int |
125 | wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd) | |
126 | { | |
127 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); | |
128 | ||
129 | writel_relaxed(0, wdt->base + WDTCONTROL); | |
130 | writel_relaxed(0, wdt->base + WDTLOAD); | |
131 | writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL); | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
4a516539 | 136 | static int wdt_config(struct watchdog_device *wdd, bool ping) |
4a370278 | 137 | { |
4a516539 VK |
138 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
139 | int ret; | |
140 | ||
141 | if (!ping) { | |
d9df0ef1 | 142 | |
63fbbc16 | 143 | ret = clk_prepare_enable(wdt->clk); |
4a516539 VK |
144 | if (ret) { |
145 | dev_err(&wdt->adev->dev, "clock enable fail"); | |
146 | return ret; | |
147 | } | |
148 | } | |
149 | ||
4a370278 VK |
150 | spin_lock(&wdt->lock); |
151 | ||
d2e8919b VK |
152 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
153 | writel_relaxed(wdt->load_val, wdt->base + WDTLOAD); | |
55e07177 | 154 | writel_relaxed(INT_MASK, wdt->base + WDTINTCLR); |
4a370278 | 155 | |
55e07177 | 156 | if (!ping) |
4a516539 VK |
157 | writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + |
158 | WDTCONTROL); | |
4a370278 | 159 | |
d2e8919b | 160 | writel_relaxed(LOCK, wdt->base + WDTLOCK); |
4a370278 | 161 | |
081d83a3 | 162 | /* Flush posted writes. */ |
d2e8919b | 163 | readl_relaxed(wdt->base + WDTLOCK); |
4a370278 | 164 | spin_unlock(&wdt->lock); |
4a516539 VK |
165 | |
166 | return 0; | |
4a370278 VK |
167 | } |
168 | ||
4a516539 | 169 | static int wdt_ping(struct watchdog_device *wdd) |
4a370278 | 170 | { |
4a516539 | 171 | return wdt_config(wdd, true); |
4a370278 VK |
172 | } |
173 | ||
4a516539 VK |
174 | /* enables watchdog timers reset */ |
175 | static int wdt_enable(struct watchdog_device *wdd) | |
4a370278 | 176 | { |
4a516539 | 177 | return wdt_config(wdd, false); |
4a370278 VK |
178 | } |
179 | ||
4a516539 VK |
180 | /* disables watchdog timers reset */ |
181 | static int wdt_disable(struct watchdog_device *wdd) | |
4a370278 | 182 | { |
4a516539 | 183 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
4a370278 | 184 | |
4a516539 | 185 | spin_lock(&wdt->lock); |
4a370278 | 186 | |
4a516539 VK |
187 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
188 | writel_relaxed(0, wdt->base + WDTCONTROL); | |
189 | writel_relaxed(LOCK, wdt->base + WDTLOCK); | |
4a370278 | 190 | |
4a516539 VK |
191 | /* Flush posted writes. */ |
192 | readl_relaxed(wdt->base + WDTLOCK); | |
193 | spin_unlock(&wdt->lock); | |
4a370278 | 194 | |
63fbbc16 | 195 | clk_disable_unprepare(wdt->clk); |
4a370278 VK |
196 | |
197 | return 0; | |
198 | } | |
199 | ||
4a516539 VK |
200 | static const struct watchdog_info wdt_info = { |
201 | .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
202 | .identity = MODULE_NAME, | |
4a370278 VK |
203 | }; |
204 | ||
4a516539 VK |
205 | static const struct watchdog_ops wdt_ops = { |
206 | .owner = THIS_MODULE, | |
207 | .start = wdt_enable, | |
208 | .stop = wdt_disable, | |
209 | .ping = wdt_ping, | |
210 | .set_timeout = wdt_setload, | |
211 | .get_timeleft = wdt_timeleft, | |
6c5c0d48 | 212 | .restart = wdt_restart, |
4a370278 VK |
213 | }; |
214 | ||
2d991a16 | 215 | static int |
aa25afad | 216 | sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id) |
4a370278 | 217 | { |
4a516539 | 218 | struct sp805_wdt *wdt; |
4a370278 VK |
219 | int ret = 0; |
220 | ||
fb35a5ad | 221 | wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL); |
4a370278 | 222 | if (!wdt) { |
4a370278 | 223 | ret = -ENOMEM; |
fb35a5ad VK |
224 | goto err; |
225 | } | |
226 | ||
9d11e4f8 JH |
227 | wdt->base = devm_ioremap_resource(&adev->dev, &adev->res); |
228 | if (IS_ERR(wdt->base)) | |
229 | return PTR_ERR(wdt->base); | |
4a370278 | 230 | |
07bf971a | 231 | wdt->clk = devm_clk_get(&adev->dev, NULL); |
4a370278 VK |
232 | if (IS_ERR(wdt->clk)) { |
233 | dev_warn(&adev->dev, "Clock not found\n"); | |
234 | ret = PTR_ERR(wdt->clk); | |
fb35a5ad | 235 | goto err; |
4a370278 VK |
236 | } |
237 | ||
238 | wdt->adev = adev; | |
4a516539 VK |
239 | wdt->wdd.info = &wdt_info; |
240 | wdt->wdd.ops = &wdt_ops; | |
6551881c | 241 | wdt->wdd.parent = &adev->dev; |
4a516539 | 242 | |
4a370278 | 243 | spin_lock_init(&wdt->lock); |
4a516539 VK |
244 | watchdog_set_nowayout(&wdt->wdd, nowayout); |
245 | watchdog_set_drvdata(&wdt->wdd, wdt); | |
6c5c0d48 | 246 | watchdog_set_restart_priority(&wdt->wdd, 128); |
4a516539 | 247 | wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT); |
4a370278 | 248 | |
4a516539 VK |
249 | ret = watchdog_register_device(&wdt->wdd); |
250 | if (ret) { | |
251 | dev_err(&adev->dev, "watchdog_register_device() failed: %d\n", | |
252 | ret); | |
07bf971a | 253 | goto err; |
4a370278 | 254 | } |
4a516539 | 255 | amba_set_drvdata(adev, wdt); |
4a370278 VK |
256 | |
257 | dev_info(&adev->dev, "registration successful\n"); | |
258 | return 0; | |
259 | ||
4a370278 VK |
260 | err: |
261 | dev_err(&adev->dev, "Probe Failed!!!\n"); | |
262 | return ret; | |
263 | } | |
264 | ||
4b12b896 | 265 | static int sp805_wdt_remove(struct amba_device *adev) |
4a370278 | 266 | { |
4a516539 VK |
267 | struct sp805_wdt *wdt = amba_get_drvdata(adev); |
268 | ||
269 | watchdog_unregister_device(&wdt->wdd); | |
4a516539 | 270 | watchdog_set_drvdata(&wdt->wdd, NULL); |
4a370278 VK |
271 | |
272 | return 0; | |
273 | } | |
274 | ||
60d6dd53 | 275 | static int __maybe_unused sp805_wdt_suspend(struct device *dev) |
16ac4abe | 276 | { |
4a516539 VK |
277 | struct sp805_wdt *wdt = dev_get_drvdata(dev); |
278 | ||
279 | if (watchdog_active(&wdt->wdd)) | |
280 | return wdt_disable(&wdt->wdd); | |
16ac4abe VK |
281 | |
282 | return 0; | |
283 | } | |
284 | ||
60d6dd53 | 285 | static int __maybe_unused sp805_wdt_resume(struct device *dev) |
16ac4abe | 286 | { |
4a516539 | 287 | struct sp805_wdt *wdt = dev_get_drvdata(dev); |
16ac4abe | 288 | |
4a516539 VK |
289 | if (watchdog_active(&wdt->wdd)) |
290 | return wdt_enable(&wdt->wdd); | |
16ac4abe | 291 | |
4a516539 | 292 | return 0; |
16ac4abe | 293 | } |
16ac4abe VK |
294 | |
295 | static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend, | |
296 | sp805_wdt_resume); | |
297 | ||
05ce42ff | 298 | static const struct amba_id sp805_wdt_ids[] = { |
4a370278 VK |
299 | { |
300 | .id = 0x00141805, | |
301 | .mask = 0x00ffffff, | |
302 | }, | |
303 | { 0, 0 }, | |
304 | }; | |
305 | ||
17885b05 DM |
306 | MODULE_DEVICE_TABLE(amba, sp805_wdt_ids); |
307 | ||
4a370278 VK |
308 | static struct amba_driver sp805_wdt_driver = { |
309 | .drv = { | |
310 | .name = MODULE_NAME, | |
16ac4abe | 311 | .pm = &sp805_wdt_dev_pm_ops, |
4a370278 VK |
312 | }, |
313 | .id_table = sp805_wdt_ids, | |
314 | .probe = sp805_wdt_probe, | |
82268714 | 315 | .remove = sp805_wdt_remove, |
4a370278 VK |
316 | }; |
317 | ||
9e5ed094 | 318 | module_amba_driver(sp805_wdt_driver); |
4a370278 | 319 | |
da89947b | 320 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |
4a370278 VK |
321 | MODULE_DESCRIPTION("ARM SP805 Watchdog Driver"); |
322 | MODULE_LICENSE("GPL"); |