dm thin: fix set_pool_mode exposed pool operation races
[linux-2.6-block.git] / drivers / watchdog / sp805_wdt.c
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1/*
2 * drivers/char/watchdog/sp805-wdt.c
3 *
4 * Watchdog driver for ARM SP805 watchdog module
5 *
6 * Copyright (C) 2010 ST Microelectronics
10d8935f 7 * Viresh Kumar <viresh.linux@gmail.com>
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8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2 or later. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/device.h>
15#include <linux/resource.h>
16#include <linux/amba/bus.h>
17#include <linux/bitops.h>
18#include <linux/clk.h>
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19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/kernel.h>
23#include <linux/math64.h>
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24#include <linux/module.h>
25#include <linux/moduleparam.h>
16ac4abe 26#include <linux/pm.h>
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27#include <linux/slab.h>
28#include <linux/spinlock.h>
29#include <linux/types.h>
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30#include <linux/watchdog.h>
31
32/* default timeout in seconds */
33#define DEFAULT_TIMEOUT 60
34
35#define MODULE_NAME "sp805-wdt"
36
37/* watchdog register offsets and masks */
38#define WDTLOAD 0x000
39 #define LOAD_MIN 0x00000001
40 #define LOAD_MAX 0xFFFFFFFF
41#define WDTVALUE 0x004
42#define WDTCONTROL 0x008
43 /* control register masks */
44 #define INT_ENABLE (1 << 0)
45 #define RESET_ENABLE (1 << 1)
46#define WDTINTCLR 0x00C
47#define WDTRIS 0x010
48#define WDTMIS 0x014
49 #define INT_MASK (1 << 0)
50#define WDTLOCK 0xC00
51 #define UNLOCK 0x1ACCE551
52 #define LOCK 0x00000001
53
54/**
55 * struct sp805_wdt: sp805 wdt device structure
4a516539 56 * @wdd: instance of struct watchdog_device
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57 * @lock: spin lock protecting dev structure and io access
58 * @base: base address of wdt
59 * @clk: clock structure of wdt
60 * @adev: amba device structure of wdt
61 * @status: current status of wdt
62 * @load_val: load value to be set for current timeout
63 * @timeout: current programmed timeout
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64 */
65struct sp805_wdt {
4a516539 66 struct watchdog_device wdd;
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67 spinlock_t lock;
68 void __iomem *base;
69 struct clk *clk;
70 struct amba_device *adev;
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71 unsigned int load_val;
72 unsigned int timeout;
73};
74
86a1e189 75static bool nowayout = WATCHDOG_NOWAYOUT;
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76module_param(nowayout, bool, 0);
77MODULE_PARM_DESC(nowayout,
78 "Set to 1 to keep watchdog running after device release");
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79
80/* This routine finds load value that will reset system in required timout */
4a516539 81static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
4a370278 82{
4a516539 83 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
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84 u64 load, rate;
85
86 rate = clk_get_rate(wdt->clk);
87
88 /*
89 * sp805 runs counter with given value twice, after the end of first
90 * counter it gives an interrupt and then starts counter again. If
25985edc 91 * interrupt already occurred then it resets the system. This is why
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92 * load is half of what should be required.
93 */
94 load = div_u64(rate, 2) * timeout - 1;
95
96 load = (load > LOAD_MAX) ? LOAD_MAX : load;
97 load = (load < LOAD_MIN) ? LOAD_MIN : load;
98
99 spin_lock(&wdt->lock);
100 wdt->load_val = load;
101 /* roundup timeout to closest positive integer value */
102 wdt->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
103 spin_unlock(&wdt->lock);
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104
105 return 0;
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106}
107
108/* returns number of seconds left for reset to occur */
4a516539 109static unsigned int wdt_timeleft(struct watchdog_device *wdd)
4a370278 110{
4a516539 111 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
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112 u64 load, rate;
113
114 rate = clk_get_rate(wdt->clk);
115
116 spin_lock(&wdt->lock);
d2e8919b 117 load = readl_relaxed(wdt->base + WDTVALUE);
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118
119 /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
d2e8919b 120 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
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121 load += wdt->load_val + 1;
122 spin_unlock(&wdt->lock);
123
124 return div_u64(load, rate);
125}
126
4a516539 127static int wdt_config(struct watchdog_device *wdd, bool ping)
4a370278 128{
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129 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
130 int ret;
131
132 if (!ping) {
d9df0ef1 133
63fbbc16 134 ret = clk_prepare_enable(wdt->clk);
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135 if (ret) {
136 dev_err(&wdt->adev->dev, "clock enable fail");
137 return ret;
138 }
139 }
140
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141 spin_lock(&wdt->lock);
142
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143 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
144 writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
4a370278 145
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146 if (!ping) {
147 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
148 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
149 WDTCONTROL);
150 }
4a370278 151
d2e8919b 152 writel_relaxed(LOCK, wdt->base + WDTLOCK);
4a370278 153
081d83a3 154 /* Flush posted writes. */
d2e8919b 155 readl_relaxed(wdt->base + WDTLOCK);
4a370278 156 spin_unlock(&wdt->lock);
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157
158 return 0;
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159}
160
4a516539 161static int wdt_ping(struct watchdog_device *wdd)
4a370278 162{
4a516539 163 return wdt_config(wdd, true);
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164}
165
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166/* enables watchdog timers reset */
167static int wdt_enable(struct watchdog_device *wdd)
4a370278 168{
4a516539 169 return wdt_config(wdd, false);
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170}
171
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172/* disables watchdog timers reset */
173static int wdt_disable(struct watchdog_device *wdd)
4a370278 174{
4a516539 175 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
4a370278 176
4a516539 177 spin_lock(&wdt->lock);
4a370278 178
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179 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
180 writel_relaxed(0, wdt->base + WDTCONTROL);
181 writel_relaxed(LOCK, wdt->base + WDTLOCK);
4a370278 182
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183 /* Flush posted writes. */
184 readl_relaxed(wdt->base + WDTLOCK);
185 spin_unlock(&wdt->lock);
4a370278 186
63fbbc16 187 clk_disable_unprepare(wdt->clk);
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188
189 return 0;
190}
191
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192static const struct watchdog_info wdt_info = {
193 .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
194 .identity = MODULE_NAME,
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195};
196
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197static const struct watchdog_ops wdt_ops = {
198 .owner = THIS_MODULE,
199 .start = wdt_enable,
200 .stop = wdt_disable,
201 .ping = wdt_ping,
202 .set_timeout = wdt_setload,
203 .get_timeleft = wdt_timeleft,
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204};
205
2d991a16 206static int
aa25afad 207sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
4a370278 208{
4a516539 209 struct sp805_wdt *wdt;
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210 int ret = 0;
211
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212 if (!devm_request_mem_region(&adev->dev, adev->res.start,
213 resource_size(&adev->res), "sp805_wdt")) {
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214 dev_warn(&adev->dev, "Failed to get memory region resource\n");
215 ret = -ENOENT;
216 goto err;
217 }
218
fb35a5ad 219 wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
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220 if (!wdt) {
221 dev_warn(&adev->dev, "Kzalloc failed\n");
222 ret = -ENOMEM;
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223 goto err;
224 }
225
226 wdt->base = devm_ioremap(&adev->dev, adev->res.start,
227 resource_size(&adev->res));
228 if (!wdt->base) {
229 ret = -ENOMEM;
230 dev_warn(&adev->dev, "ioremap fail\n");
231 goto err;
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232 }
233
07bf971a 234 wdt->clk = devm_clk_get(&adev->dev, NULL);
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235 if (IS_ERR(wdt->clk)) {
236 dev_warn(&adev->dev, "Clock not found\n");
237 ret = PTR_ERR(wdt->clk);
fb35a5ad 238 goto err;
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239 }
240
241 wdt->adev = adev;
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242 wdt->wdd.info = &wdt_info;
243 wdt->wdd.ops = &wdt_ops;
244
4a370278 245 spin_lock_init(&wdt->lock);
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246 watchdog_set_nowayout(&wdt->wdd, nowayout);
247 watchdog_set_drvdata(&wdt->wdd, wdt);
248 wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT);
4a370278 249
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250 ret = watchdog_register_device(&wdt->wdd);
251 if (ret) {
252 dev_err(&adev->dev, "watchdog_register_device() failed: %d\n",
253 ret);
07bf971a 254 goto err;
4a370278 255 }
4a516539 256 amba_set_drvdata(adev, wdt);
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257
258 dev_info(&adev->dev, "registration successful\n");
259 return 0;
260
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261err:
262 dev_err(&adev->dev, "Probe Failed!!!\n");
263 return ret;
264}
265
4b12b896 266static int sp805_wdt_remove(struct amba_device *adev)
4a370278 267{
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268 struct sp805_wdt *wdt = amba_get_drvdata(adev);
269
270 watchdog_unregister_device(&wdt->wdd);
4a516539 271 watchdog_set_drvdata(&wdt->wdd, NULL);
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272
273 return 0;
274}
275
60d6dd53 276static int __maybe_unused sp805_wdt_suspend(struct device *dev)
16ac4abe 277{
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278 struct sp805_wdt *wdt = dev_get_drvdata(dev);
279
280 if (watchdog_active(&wdt->wdd))
281 return wdt_disable(&wdt->wdd);
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282
283 return 0;
284}
285
60d6dd53 286static int __maybe_unused sp805_wdt_resume(struct device *dev)
16ac4abe 287{
4a516539 288 struct sp805_wdt *wdt = dev_get_drvdata(dev);
16ac4abe 289
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290 if (watchdog_active(&wdt->wdd))
291 return wdt_enable(&wdt->wdd);
16ac4abe 292
4a516539 293 return 0;
16ac4abe 294}
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295
296static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
297 sp805_wdt_resume);
298
bb558dac 299static struct amba_id sp805_wdt_ids[] = {
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300 {
301 .id = 0x00141805,
302 .mask = 0x00ffffff,
303 },
304 { 0, 0 },
305};
306
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307MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);
308
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309static struct amba_driver sp805_wdt_driver = {
310 .drv = {
311 .name = MODULE_NAME,
16ac4abe 312 .pm = &sp805_wdt_dev_pm_ops,
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313 },
314 .id_table = sp805_wdt_ids,
315 .probe = sp805_wdt_probe,
82268714 316 .remove = sp805_wdt_remove,
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317};
318
9e5ed094 319module_amba_driver(sp805_wdt_driver);
4a370278 320
10d8935f 321MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
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322MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
323MODULE_LICENSE("GPL");