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3b190545 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
4a370278 VK |
2 | /* |
3 | * drivers/char/watchdog/sp805-wdt.c | |
4 | * | |
5 | * Watchdog driver for ARM SP805 watchdog module | |
6 | * | |
7 | * Copyright (C) 2010 ST Microelectronics | |
da89947b | 8 | * Viresh Kumar <vireshk@kernel.org> |
4a370278 VK |
9 | * |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2 or later. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
14 | ||
15 | #include <linux/device.h> | |
16 | #include <linux/resource.h> | |
17 | #include <linux/amba/bus.h> | |
18 | #include <linux/bitops.h> | |
19 | #include <linux/clk.h> | |
4a370278 VK |
20 | #include <linux/io.h> |
21 | #include <linux/ioport.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/math64.h> | |
4a370278 VK |
24 | #include <linux/module.h> |
25 | #include <linux/moduleparam.h> | |
16ac4abe | 26 | #include <linux/pm.h> |
05f0a994 | 27 | #include <linux/property.h> |
4a370278 VK |
28 | #include <linux/slab.h> |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/types.h> | |
4a370278 VK |
31 | #include <linux/watchdog.h> |
32 | ||
33 | /* default timeout in seconds */ | |
34 | #define DEFAULT_TIMEOUT 60 | |
35 | ||
36 | #define MODULE_NAME "sp805-wdt" | |
37 | ||
38 | /* watchdog register offsets and masks */ | |
39 | #define WDTLOAD 0x000 | |
40 | #define LOAD_MIN 0x00000001 | |
41 | #define LOAD_MAX 0xFFFFFFFF | |
42 | #define WDTVALUE 0x004 | |
43 | #define WDTCONTROL 0x008 | |
44 | /* control register masks */ | |
45 | #define INT_ENABLE (1 << 0) | |
46 | #define RESET_ENABLE (1 << 1) | |
fa5072ed | 47 | #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE) |
4a370278 VK |
48 | #define WDTINTCLR 0x00C |
49 | #define WDTRIS 0x010 | |
50 | #define WDTMIS 0x014 | |
51 | #define INT_MASK (1 << 0) | |
52 | #define WDTLOCK 0xC00 | |
53 | #define UNLOCK 0x1ACCE551 | |
54 | #define LOCK 0x00000001 | |
55 | ||
56 | /** | |
57 | * struct sp805_wdt: sp805 wdt device structure | |
4a516539 | 58 | * @wdd: instance of struct watchdog_device |
bfae14b6 VK |
59 | * @lock: spin lock protecting dev structure and io access |
60 | * @base: base address of wdt | |
3452239e AS |
61 | * @clk: (optional) clock structure of wdt |
62 | * @rate: (optional) clock rate when provided via properties | |
bfae14b6 VK |
63 | * @adev: amba device structure of wdt |
64 | * @status: current status of wdt | |
65 | * @load_val: load value to be set for current timeout | |
4a370278 VK |
66 | */ |
67 | struct sp805_wdt { | |
4a516539 | 68 | struct watchdog_device wdd; |
4a370278 VK |
69 | spinlock_t lock; |
70 | void __iomem *base; | |
71 | struct clk *clk; | |
dc0e4a3b | 72 | u64 rate; |
4a370278 | 73 | struct amba_device *adev; |
4a370278 | 74 | unsigned int load_val; |
4a370278 VK |
75 | }; |
76 | ||
86a1e189 | 77 | static bool nowayout = WATCHDOG_NOWAYOUT; |
4a516539 VK |
78 | module_param(nowayout, bool, 0); |
79 | MODULE_PARM_DESC(nowayout, | |
80 | "Set to 1 to keep watchdog running after device release"); | |
4a370278 | 81 | |
fa5072ed RJ |
82 | /* returns true if wdt is running; otherwise returns false */ |
83 | static bool wdt_is_running(struct watchdog_device *wdd) | |
84 | { | |
85 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); | |
86 | u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL); | |
87 | ||
88 | return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK; | |
89 | } | |
90 | ||
097a4a16 | 91 | /* This routine finds load value that will reset system in required timeout */ |
4a516539 | 92 | static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout) |
4a370278 | 93 | { |
4a516539 | 94 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
4a370278 VK |
95 | u64 load, rate; |
96 | ||
dc0e4a3b | 97 | rate = wdt->rate; |
4a370278 VK |
98 | |
99 | /* | |
100 | * sp805 runs counter with given value twice, after the end of first | |
101 | * counter it gives an interrupt and then starts counter again. If | |
25985edc | 102 | * interrupt already occurred then it resets the system. This is why |
4a370278 VK |
103 | * load is half of what should be required. |
104 | */ | |
105 | load = div_u64(rate, 2) * timeout - 1; | |
106 | ||
107 | load = (load > LOAD_MAX) ? LOAD_MAX : load; | |
108 | load = (load < LOAD_MIN) ? LOAD_MIN : load; | |
109 | ||
110 | spin_lock(&wdt->lock); | |
111 | wdt->load_val = load; | |
112 | /* roundup timeout to closest positive integer value */ | |
938626d9 | 113 | wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate); |
4a370278 | 114 | spin_unlock(&wdt->lock); |
4a516539 VK |
115 | |
116 | return 0; | |
4a370278 VK |
117 | } |
118 | ||
119 | /* returns number of seconds left for reset to occur */ | |
4a516539 | 120 | static unsigned int wdt_timeleft(struct watchdog_device *wdd) |
4a370278 | 121 | { |
4a516539 | 122 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
dc0e4a3b | 123 | u64 load; |
4a370278 VK |
124 | |
125 | spin_lock(&wdt->lock); | |
d2e8919b | 126 | load = readl_relaxed(wdt->base + WDTVALUE); |
4a370278 VK |
127 | |
128 | /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */ | |
d2e8919b | 129 | if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK)) |
4a370278 VK |
130 | load += wdt->load_val + 1; |
131 | spin_unlock(&wdt->lock); | |
132 | ||
dc0e4a3b | 133 | return div_u64(load, wdt->rate); |
4a370278 VK |
134 | } |
135 | ||
6c5c0d48 JK |
136 | static int |
137 | wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd) | |
138 | { | |
139 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); | |
140 | ||
ea104a9e | 141 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
6c5c0d48 JK |
142 | writel_relaxed(0, wdt->base + WDTCONTROL); |
143 | writel_relaxed(0, wdt->base + WDTLOAD); | |
144 | writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL); | |
145 | ||
ea104a9e MW |
146 | /* Flush posted writes. */ |
147 | readl_relaxed(wdt->base + WDTLOCK); | |
148 | ||
6c5c0d48 JK |
149 | return 0; |
150 | } | |
151 | ||
4a516539 | 152 | static int wdt_config(struct watchdog_device *wdd, bool ping) |
4a370278 | 153 | { |
4a516539 VK |
154 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
155 | int ret; | |
156 | ||
157 | if (!ping) { | |
d9df0ef1 | 158 | |
63fbbc16 | 159 | ret = clk_prepare_enable(wdt->clk); |
4a516539 VK |
160 | if (ret) { |
161 | dev_err(&wdt->adev->dev, "clock enable fail"); | |
162 | return ret; | |
163 | } | |
164 | } | |
165 | ||
4a370278 VK |
166 | spin_lock(&wdt->lock); |
167 | ||
d2e8919b VK |
168 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
169 | writel_relaxed(wdt->load_val, wdt->base + WDTLOAD); | |
55e07177 | 170 | writel_relaxed(INT_MASK, wdt->base + WDTINTCLR); |
4a370278 | 171 | |
55e07177 | 172 | if (!ping) |
4a516539 VK |
173 | writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + |
174 | WDTCONTROL); | |
4a370278 | 175 | |
d2e8919b | 176 | writel_relaxed(LOCK, wdt->base + WDTLOCK); |
4a370278 | 177 | |
081d83a3 | 178 | /* Flush posted writes. */ |
d2e8919b | 179 | readl_relaxed(wdt->base + WDTLOCK); |
4a370278 | 180 | spin_unlock(&wdt->lock); |
4a516539 VK |
181 | |
182 | return 0; | |
4a370278 VK |
183 | } |
184 | ||
4a516539 | 185 | static int wdt_ping(struct watchdog_device *wdd) |
4a370278 | 186 | { |
4a516539 | 187 | return wdt_config(wdd, true); |
4a370278 VK |
188 | } |
189 | ||
4a516539 VK |
190 | /* enables watchdog timers reset */ |
191 | static int wdt_enable(struct watchdog_device *wdd) | |
4a370278 | 192 | { |
4a516539 | 193 | return wdt_config(wdd, false); |
4a370278 VK |
194 | } |
195 | ||
4a516539 VK |
196 | /* disables watchdog timers reset */ |
197 | static int wdt_disable(struct watchdog_device *wdd) | |
4a370278 | 198 | { |
4a516539 | 199 | struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); |
4a370278 | 200 | |
4a516539 | 201 | spin_lock(&wdt->lock); |
4a370278 | 202 | |
4a516539 VK |
203 | writel_relaxed(UNLOCK, wdt->base + WDTLOCK); |
204 | writel_relaxed(0, wdt->base + WDTCONTROL); | |
205 | writel_relaxed(LOCK, wdt->base + WDTLOCK); | |
4a370278 | 206 | |
4a516539 VK |
207 | /* Flush posted writes. */ |
208 | readl_relaxed(wdt->base + WDTLOCK); | |
209 | spin_unlock(&wdt->lock); | |
4a370278 | 210 | |
63fbbc16 | 211 | clk_disable_unprepare(wdt->clk); |
4a370278 VK |
212 | |
213 | return 0; | |
214 | } | |
215 | ||
4a516539 VK |
216 | static const struct watchdog_info wdt_info = { |
217 | .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
218 | .identity = MODULE_NAME, | |
4a370278 VK |
219 | }; |
220 | ||
4a516539 VK |
221 | static const struct watchdog_ops wdt_ops = { |
222 | .owner = THIS_MODULE, | |
223 | .start = wdt_enable, | |
224 | .stop = wdt_disable, | |
225 | .ping = wdt_ping, | |
226 | .set_timeout = wdt_setload, | |
227 | .get_timeleft = wdt_timeleft, | |
6c5c0d48 | 228 | .restart = wdt_restart, |
4a370278 VK |
229 | }; |
230 | ||
2d991a16 | 231 | static int |
aa25afad | 232 | sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id) |
4a370278 | 233 | { |
4a516539 | 234 | struct sp805_wdt *wdt; |
05f0a994 | 235 | u64 rate = 0; |
4a370278 VK |
236 | int ret = 0; |
237 | ||
fb35a5ad | 238 | wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL); |
4a370278 | 239 | if (!wdt) { |
4a370278 | 240 | ret = -ENOMEM; |
fb35a5ad VK |
241 | goto err; |
242 | } | |
243 | ||
9d11e4f8 JH |
244 | wdt->base = devm_ioremap_resource(&adev->dev, &adev->res); |
245 | if (IS_ERR(wdt->base)) | |
246 | return PTR_ERR(wdt->base); | |
4a370278 | 247 | |
05f0a994 AS |
248 | /* |
249 | * When driver probe with ACPI device, clock devices | |
250 | * are not available, so watchdog rate get from | |
251 | * clock-frequency property given in _DSD object. | |
252 | */ | |
253 | device_property_read_u64(&adev->dev, "clock-frequency", &rate); | |
254 | ||
255 | wdt->clk = devm_clk_get_optional(&adev->dev, NULL); | |
256 | if (IS_ERR(wdt->clk)) | |
257 | return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n"); | |
258 | ||
259 | wdt->rate = clk_get_rate(wdt->clk); | |
260 | if (!wdt->rate) | |
261 | wdt->rate = rate; | |
262 | if (!wdt->rate) { | |
263 | dev_err(&adev->dev, "no clock-frequency property\n"); | |
264 | return -ENODEV; | |
4a370278 VK |
265 | } |
266 | ||
267 | wdt->adev = adev; | |
4a516539 VK |
268 | wdt->wdd.info = &wdt_info; |
269 | wdt->wdd.ops = &wdt_ops; | |
6551881c | 270 | wdt->wdd.parent = &adev->dev; |
4a516539 | 271 | |
4a370278 | 272 | spin_lock_init(&wdt->lock); |
4a516539 VK |
273 | watchdog_set_nowayout(&wdt->wdd, nowayout); |
274 | watchdog_set_drvdata(&wdt->wdd, wdt); | |
6c5c0d48 | 275 | watchdog_set_restart_priority(&wdt->wdd, 128); |
ac97c937 | 276 | watchdog_stop_on_unregister(&wdt->wdd); |
b8008858 RJ |
277 | |
278 | /* | |
279 | * If 'timeout-sec' devicetree property is specified, use that. | |
280 | * Otherwise, use DEFAULT_TIMEOUT | |
281 | */ | |
282 | wdt->wdd.timeout = DEFAULT_TIMEOUT; | |
283 | watchdog_init_timeout(&wdt->wdd, 0, &adev->dev); | |
284 | wdt_setload(&wdt->wdd, wdt->wdd.timeout); | |
4a370278 | 285 | |
fa5072ed RJ |
286 | /* |
287 | * If HW is already running, enable/reset the wdt and set the running | |
288 | * bit to tell the wdt subsystem | |
289 | */ | |
290 | if (wdt_is_running(&wdt->wdd)) { | |
291 | wdt_enable(&wdt->wdd); | |
292 | set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); | |
293 | } | |
294 | ||
42e967f3 | 295 | watchdog_stop_on_reboot(&wdt->wdd); |
4a516539 | 296 | ret = watchdog_register_device(&wdt->wdd); |
199801cd | 297 | if (ret) |
07bf971a | 298 | goto err; |
4a516539 | 299 | amba_set_drvdata(adev, wdt); |
4a370278 VK |
300 | |
301 | dev_info(&adev->dev, "registration successful\n"); | |
302 | return 0; | |
303 | ||
4a370278 VK |
304 | err: |
305 | dev_err(&adev->dev, "Probe Failed!!!\n"); | |
306 | return ret; | |
307 | } | |
308 | ||
3fd269e7 | 309 | static void sp805_wdt_remove(struct amba_device *adev) |
4a370278 | 310 | { |
4a516539 VK |
311 | struct sp805_wdt *wdt = amba_get_drvdata(adev); |
312 | ||
313 | watchdog_unregister_device(&wdt->wdd); | |
4a516539 | 314 | watchdog_set_drvdata(&wdt->wdd, NULL); |
4a370278 VK |
315 | } |
316 | ||
60d6dd53 | 317 | static int __maybe_unused sp805_wdt_suspend(struct device *dev) |
16ac4abe | 318 | { |
4a516539 VK |
319 | struct sp805_wdt *wdt = dev_get_drvdata(dev); |
320 | ||
321 | if (watchdog_active(&wdt->wdd)) | |
322 | return wdt_disable(&wdt->wdd); | |
16ac4abe VK |
323 | |
324 | return 0; | |
325 | } | |
326 | ||
60d6dd53 | 327 | static int __maybe_unused sp805_wdt_resume(struct device *dev) |
16ac4abe | 328 | { |
4a516539 | 329 | struct sp805_wdt *wdt = dev_get_drvdata(dev); |
16ac4abe | 330 | |
4a516539 VK |
331 | if (watchdog_active(&wdt->wdd)) |
332 | return wdt_enable(&wdt->wdd); | |
16ac4abe | 333 | |
4a516539 | 334 | return 0; |
16ac4abe | 335 | } |
16ac4abe VK |
336 | |
337 | static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend, | |
338 | sp805_wdt_resume); | |
339 | ||
05ce42ff | 340 | static const struct amba_id sp805_wdt_ids[] = { |
4a370278 VK |
341 | { |
342 | .id = 0x00141805, | |
343 | .mask = 0x00ffffff, | |
344 | }, | |
3b190545 BF |
345 | { |
346 | .id = 0x001bb824, | |
347 | .mask = 0x00ffffff, | |
348 | }, | |
4a370278 VK |
349 | { 0, 0 }, |
350 | }; | |
351 | ||
17885b05 DM |
352 | MODULE_DEVICE_TABLE(amba, sp805_wdt_ids); |
353 | ||
4a370278 VK |
354 | static struct amba_driver sp805_wdt_driver = { |
355 | .drv = { | |
356 | .name = MODULE_NAME, | |
16ac4abe | 357 | .pm = &sp805_wdt_dev_pm_ops, |
4a370278 VK |
358 | }, |
359 | .id_table = sp805_wdt_ids, | |
360 | .probe = sp805_wdt_probe, | |
82268714 | 361 | .remove = sp805_wdt_remove, |
4a370278 VK |
362 | }; |
363 | ||
9e5ed094 | 364 | module_amba_driver(sp805_wdt_driver); |
4a370278 | 365 | |
da89947b | 366 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |
4a370278 VK |
367 | MODULE_DESCRIPTION("ARM SP805 Watchdog Driver"); |
368 | MODULE_LICENSE("GPL"); |