[linux-2.6-block.git] / drivers / watchdog / sp5100_tco.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *	sp5100_tco :	TCO timer driver for sp5100 chipsets
 *
 *	(c) Copyright 2009 Google Inc., All Rights Reserved.
 *
 *	Based on i8xx_tco.c:
 *	(c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
 *	Reserved.
 *				http://www.kernelconcepts.de
 *
 *	See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
 *	    AMD Publication 45482 "AMD SB800-Series Southbridges Register
 *	                                                      Reference Guide"
 *	    AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
 *				for AMD Family 16h Models 00h-0Fh Processors"
 *	    AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
 *	    AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
 *				for AMD Family 16h Models 30h-3Fh Processors"
 */

/*
 *	Includes, defines, variables, module parameters, ...
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>

#include "sp5100_tco.h"

#define TCO_DRIVER_NAME	"sp5100-tco"

/* internal variables */

enum tco_reg_layout {
	sp5100, sb800, efch
};

struct sp5100_tco {
	struct watchdog_device wdd;
	void __iomem *tcobase;
	enum tco_reg_layout tco_reg_layout;
};

/* the watchdog platform device */
static struct platform_device *sp5100_tco_platform_device;
/* the associated PCI device */
static struct pci_dev *sp5100_tco_pci;

/* module parameters */

#define WATCHDOG_HEARTBEAT 60	/* 60 sec default heartbeat. */
static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
		 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
		" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

/*
 * Some TCO specific functions
 */

static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
{
	if (dev->vendor == PCI_VENDOR_ID_ATI &&
	    dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	    dev->revision < 0x40) {
		return sp5100;
	} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
	     dev->revision >= 0x41) ||
	    (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
	     dev->revision >= 0x49))) {
		return efch;
	}
	return sb800;
}

static int tco_timer_start(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val |= SP5100_WDT_START_STOP_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_stop(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val &= ~SP5100_WDT_START_STOP_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_ping(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val |= SP5100_WDT_TRIGGER_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_set_timeout(struct watchdog_device *wdd,
				 unsigned int t)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);

	/* Write new heartbeat to watchdog */
	writel(t, SP5100_WDT_COUNT(tco->tcobase));

	wdd->timeout = t;

	return 0;
}

static u8 sp5100_tco_read_pm_reg8(u8 index)
{
	outb(index, SP5100_IO_PM_INDEX_REG);
	return inb(SP5100_IO_PM_DATA_REG);
}

static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
{
	u8 val;

	outb(index, SP5100_IO_PM_INDEX_REG);
	val = inb(SP5100_IO_PM_DATA_REG);
	val &= reset;
	val |= set;
	outb(val, SP5100_IO_PM_DATA_REG);
}

static void tco_timer_enable(struct sp5100_tco *tco)
{
	u32 val;

	switch (tco->tco_reg_layout) {
	case sb800:
		/* For SB800 or later */
		/* Set the Watchdog timer resolution to 1 sec */
		sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
					  0xff, SB800_PM_WATCHDOG_SECOND_RES);

		/* Enable watchdog decode bit and watchdog timer */
		sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
					  ~SB800_PM_WATCHDOG_DISABLE,
					  SB800_PCI_WATCHDOG_DECODE_EN);
		break;
	case sp5100:
		/* For SP5100 or SB7x0 */
		/* Enable watchdog decode bit */
		pci_read_config_dword(sp5100_tco_pci,
				      SP5100_PCI_WATCHDOG_MISC_REG,
				      &val);

		val |= SP5100_PCI_WATCHDOG_DECODE_EN;

		pci_write_config_dword(sp5100_tco_pci,
				       SP5100_PCI_WATCHDOG_MISC_REG,
				       val);

		/* Enable Watchdog timer and set the resolution to 1 sec */
		sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
					  ~SP5100_PM_WATCHDOG_DISABLE,
					  SP5100_PM_WATCHDOG_SECOND_RES);
		break;
	case efch:
		/* Set the Watchdog timer resolution to 1 sec and enable */
		sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
					  ~EFCH_PM_WATCHDOG_DISABLE,
					  EFCH_PM_DECODEEN_SECOND_RES);
		break;
	}
}

static u32 sp5100_tco_read_pm_reg32(u8 index)
{
	u32 val = 0;
	int i;

	for (i = 3; i >= 0; i--)
		val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);

	return val;
}

static int sp5100_tco_setupdevice(struct device *dev,
				  struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	const char *dev_name;
	u32 mmio_addr = 0, val;
	int ret;

	/* Request the IO ports used by this driver */
	if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
				  SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
		dev_err(dev, "I/O address 0x%04x already in use\n",
			SP5100_IO_PM_INDEX_REG);
		return -EBUSY;
	}

	/*
	 * Determine type of southbridge chipset.
	 */
	switch (tco->tco_reg_layout) {
	case sp5100:
		dev_name = SP5100_DEVNAME;
		mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
								0xfffffff8;
		break;
	case sb800:
		dev_name = SB800_DEVNAME;
		mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
								0xfffffff8;
		break;
	case efch:
		dev_name = SB800_DEVNAME;
		val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
		if (val & EFCH_PM_DECODEEN_WDT_TMREN)
			mmio_addr = EFCH_PM_WDT_ADDR;
		break;
	default:
		return -ENODEV;
	}

	/* Check MMIO address conflict */
	if (!mmio_addr ||
	    !devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
				     dev_name)) {
		if (mmio_addr)
			dev_dbg(dev, "MMIO address 0x%08x already in use\n",
				mmio_addr);
		switch (tco->tco_reg_layout) {
		case sp5100:
			/*
			 * Secondly, Find the watchdog timer MMIO address
			 * from SBResource_MMIO register.
			 */
			/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
			pci_read_config_dword(sp5100_tco_pci,
					      SP5100_SB_RESOURCE_MMIO_BASE,
					      &mmio_addr);
			if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
					  SB800_ACPI_MMIO_SEL)) !=
						  SB800_ACPI_MMIO_DECODE_EN) {
				ret = -ENODEV;
				goto unreg_region;
			}
			mmio_addr &= ~0xFFF;
			mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
			break;
		case sb800:
			/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
			mmio_addr =
				sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
			if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
					  SB800_ACPI_MMIO_SEL)) !=
						  SB800_ACPI_MMIO_DECODE_EN) {
				ret = -ENODEV;
				goto unreg_region;
			}
			mmio_addr &= ~0xFFF;
			mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
			break;
		case efch:
			val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
			if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
				ret = -ENODEV;
				goto unreg_region;
			}
			mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
				    EFCH_PM_ACPI_MMIO_WDT_OFFSET;
			break;
		}
		dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
			mmio_addr);
		if (!devm_request_mem_region(dev, mmio_addr,
					     SP5100_WDT_MEM_MAP_SIZE,
					     dev_name)) {
			dev_dbg(dev, "MMIO address 0x%08x already in use\n",
				mmio_addr);
			ret = -EBUSY;
			goto unreg_region;
		}
	}

	tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
	if (!tco->tcobase) {
		dev_err(dev, "failed to get tcobase address\n");
		ret = -ENOMEM;
		goto unreg_region;
	}

	dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);

	/* Setup the watchdog timer */
	tco_timer_enable(tco);

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	if (val & SP5100_WDT_DISABLED) {
		dev_err(dev, "Watchdog hardware is disabled\n");
		ret = -ENODEV;
		goto unreg_region;
	}

	/*
	 * Save WatchDogFired status, because WatchDogFired flag is
	 * cleared here.
	 */
	if (val & SP5100_WDT_FIRED)
		wdd->bootstatus = WDIOF_CARDRESET;
	/* Set watchdog action to reset the system */
	val &= ~SP5100_WDT_ACTION_RESET;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	/* Set a reasonable heartbeat before we stop the timer */
	tco_timer_set_timeout(wdd, wdd->timeout);

	/*
	 * Stop the TCO before we change anything so we don't race with
	 * a zeroed timer.
	 */
	tco_timer_stop(wdd);

	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);

	return 0;

unreg_region:
	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
	return ret;
}

static struct watchdog_info sp5100_tco_wdt_info = {
	.identity = "SP5100 TCO timer",
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops sp5100_tco_wdt_ops = {
	.owner = THIS_MODULE,
	.start = tco_timer_start,
	.stop = tco_timer_stop,
	.ping = tco_timer_ping,
	.set_timeout = tco_timer_set_timeout,
};

static int sp5100_tco_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct sp5100_tco *tco;
	int ret;

	tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
	if (!tco)
		return -ENOMEM;

	tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);

	wdd = &tco->wdd;
	wdd->parent = dev;
	wdd->info = &sp5100_tco_wdt_info;
	wdd->ops = &sp5100_tco_wdt_ops;
	wdd->timeout = WATCHDOG_HEARTBEAT;
	wdd->min_timeout = 1;
	wdd->max_timeout = 0xffff;

	watchdog_init_timeout(wdd, heartbeat, NULL);
	watchdog_set_nowayout(wdd, nowayout);
	watchdog_stop_on_reboot(wdd);
	watchdog_stop_on_unregister(wdd);
	watchdog_set_drvdata(wdd, tco);

	ret = sp5100_tco_setupdevice(dev, wdd);
	if (ret)
		return ret;

	ret = devm_watchdog_register_device(dev, wdd);
	if (ret)
		return ret;

	/* Show module parameters */
	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
		 wdd->timeout, nowayout);

	return 0;
}

static struct platform_driver sp5100_tco_driver = {
	.probe		= sp5100_tco_probe,
	.driver		= {
		.name	= TCO_DRIVER_NAME,
	},
};

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because someone else might
 * want to register another driver on the same PCI id.
 */
static const struct pci_device_id sp5100_tco_pci_tbl[] = {
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ 0, },			/* End of list */
};
MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);

static int __init sp5100_tco_init(void)
{
	struct pci_dev *dev = NULL;
	int err;

	/* Match the PCI device */
	for_each_pci_dev(dev) {
		if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
			sp5100_tco_pci = dev;
			break;
		}
	}

	if (!sp5100_tco_pci)
		return -ENODEV;

	pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");

	err = platform_driver_register(&sp5100_tco_driver);
	if (err)
		return err;

	sp5100_tco_platform_device =
		platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
	if (IS_ERR(sp5100_tco_platform_device)) {
		err = PTR_ERR(sp5100_tco_platform_device);
		goto unreg_platform_driver;
	}

	return 0;

unreg_platform_driver:
	platform_driver_unregister(&sp5100_tco_driver);
	return err;
}

static void __exit sp5100_tco_exit(void)
{
	platform_device_unregister(sp5100_tco_platform_device);
	platform_driver_unregister(&sp5100_tco_driver);
}

module_init(sp5100_tco_init);
module_exit(sp5100_tco_exit);

MODULE_AUTHOR("Priyanka Gupta");
MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
15e28bf1 PG	2	/*
	3	* sp5100_tco : TCO timer driver for sp5100 chipsets
	4	*
	5	* (c) Copyright 2009 Google Inc., All Rights Reserved.
	6	*
	7	* Based on i8xx_tco.c:
	8	* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
	9	* Reserved.
	10	* http://www.kernelconcepts.de
	11	*
740fbddf TT	12	* See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
	13	* AMD Publication 45482 "AMD SB800-Series Southbridges Register
	14	* Reference Guide"
887d2ec5 GR	15	* AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
	16	* for AMD Family 16h Models 00h-0Fh Processors"
	17	* AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
	18	* AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
	19	* for AMD Family 16h Models 30h-3Fh Processors"
15e28bf1 PG	20	*/
	21
	22	/*
	23	* Includes, defines, variables, module parameters, ...
	24	*/
	25
27c766aa JP	26	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	27
7cd9d5ff GR	28	#include <linux/init.h>
	29	#include <linux/io.h>
	30	#include <linux/ioport.h>
15e28bf1 PG	31	#include <linux/module.h>
15e28bf1 PG	32	#include <linux/moduleparam.h>
15e28bf1	33	#include <linux/pci.h>
15e28bf1	34	#include <linux/platform_device.h>
7cd9d5ff GR	35	#include <linux/types.h>
7cd9d5ff GR	36	#include <linux/watchdog.h>
15e28bf1 PG	37
	38	#include "sp5100_tco.h"
	39
7cd9d5ff	40	#define TCO_DRIVER_NAME "sp5100-tco"
15e28bf1 PG	41
15e28bf1 PG	42	/* internal variables */
7cd9d5ff	43
887d2ec5 GR	44	enum tco_reg_layout {
	45	sp5100, sb800, efch
	46	};
	47
7cd9d5ff GR	48	struct sp5100_tco {
	49	struct watchdog_device wdd;
	50	void __iomem *tcobase;
887d2ec5	51	enum tco_reg_layout tco_reg_layout;
7cd9d5ff	52	};
15e28bf1 PG	53
	54	/* the watchdog platform device */
	55	static struct platform_device *sp5100_tco_platform_device;
7cd9d5ff GR	56	/* the associated PCI device */
7cd9d5ff GR	57	static struct pci_dev *sp5100_tco_pci;
15e28bf1 PG	58
	59	/* module parameters */
	60
	61	#define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
	62	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
	63	module_param(heartbeat, int, 0);
	64	MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
	65	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
	66
86a1e189 WVS	67	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	68	module_param(nowayout, bool, 0);
740fbddf	69	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
15e28bf1 PG	70	" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	71
	72	/*
	73	* Some TCO specific functions
	74	*/
46856fab	75
887d2ec5	76	static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
46856fab	77	{
887d2ec5 GR	78	if (dev->vendor == PCI_VENDOR_ID_ATI &&
	79	dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	80	dev->revision < 0x40) {
	81	return sp5100;
	82	} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	83	((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
	84	dev->revision >= 0x41) \|\|
	85	(dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
	86	dev->revision >= 0x49))) {
	87	return efch;
	88	}
	89	return sb800;
46856fab LS	90	}
46856fab LS	91
7cd9d5ff	92	static int tco_timer_start(struct watchdog_device *wdd)
15e28bf1	93	{
7cd9d5ff	94	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	95	u32 val;
15e28bf1	96
7cd9d5ff	97	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	98	val \|= SP5100_WDT_START_STOP_BIT;
7cd9d5ff GR	99	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	100
	101	return 0;
15e28bf1 PG	102	}
15e28bf1 PG	103
7cd9d5ff	104	static int tco_timer_stop(struct watchdog_device *wdd)
15e28bf1	105	{
7cd9d5ff	106	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	107	u32 val;
15e28bf1	108
7cd9d5ff	109	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	110	val &= ~SP5100_WDT_START_STOP_BIT;
7cd9d5ff GR	111	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	112
	113	return 0;
15e28bf1 PG	114	}
15e28bf1 PG	115
7cd9d5ff	116	static int tco_timer_ping(struct watchdog_device *wdd)
15e28bf1	117	{
7cd9d5ff	118	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	119	u32 val;
15e28bf1	120
7cd9d5ff	121	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	122	val \|= SP5100_WDT_TRIGGER_BIT;
7cd9d5ff GR	123	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	124
	125	return 0;
15e28bf1 PG	126	}
15e28bf1 PG	127
7cd9d5ff GR	128	static int tco_timer_set_timeout(struct watchdog_device *wdd,
7cd9d5ff GR	129	unsigned int t)
15e28bf1	130	{
7cd9d5ff	131	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1 PG	132
15e28bf1 PG	133	/* Write new heartbeat to watchdog */
7cd9d5ff GR	134	writel(t, SP5100_WDT_COUNT(tco->tcobase));
	135
	136	wdd->timeout = t;
15e28bf1	137
15e28bf1 PG	138	return 0;
	139	}
	140
2b750cff GR	141	static u8 sp5100_tco_read_pm_reg8(u8 index)
	142	{
	143	outb(index, SP5100_IO_PM_INDEX_REG);
	144	return inb(SP5100_IO_PM_DATA_REG);
	145	}
	146
	147	static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
740fbddf	148	{
2b750cff	149	u8 val;
740fbddf	150
2b750cff GR	151	outb(index, SP5100_IO_PM_INDEX_REG);
	152	val = inb(SP5100_IO_PM_DATA_REG);
	153	val &= reset;
	154	val \|= set;
	155	outb(val, SP5100_IO_PM_DATA_REG);
	156	}
	157
887d2ec5	158	static void tco_timer_enable(struct sp5100_tco *tco)
2b750cff	159	{
887d2ec5 GR	160	u32 val;
	161
	162	switch (tco->tco_reg_layout) {
	163	case sb800:
740fbddf TT	164	/* For SB800 or later */
740fbddf TT	165	/* Set the Watchdog timer resolution to 1 sec */
2b750cff GR	166	sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
2b750cff GR	167	0xff, SB800_PM_WATCHDOG_SECOND_RES);
740fbddf TT	168
740fbddf TT	169	/* Enable watchdog decode bit and watchdog timer */
2b750cff GR	170	sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
	171	~SB800_PM_WATCHDOG_DISABLE,
	172	SB800_PCI_WATCHDOG_DECODE_EN);
887d2ec5 GR	173	break;
887d2ec5 GR	174	case sp5100:
740fbddf TT	175	/* For SP5100 or SB7x0 */
	176	/* Enable watchdog decode bit */
	177	pci_read_config_dword(sp5100_tco_pci,
	178	SP5100_PCI_WATCHDOG_MISC_REG,
	179	&val);
	180
	181	val \|= SP5100_PCI_WATCHDOG_DECODE_EN;
	182
	183	pci_write_config_dword(sp5100_tco_pci,
	184	SP5100_PCI_WATCHDOG_MISC_REG,
	185	val);
	186
	187	/* Enable Watchdog timer and set the resolution to 1 sec */
2b750cff GR	188	sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
	189	~SP5100_PM_WATCHDOG_DISABLE,
	190	SP5100_PM_WATCHDOG_SECOND_RES);
887d2ec5 GR	191	break;
	192	case efch:
	193	/* Set the Watchdog timer resolution to 1 sec and enable */
	194	sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
	195	~EFCH_PM_WATCHDOG_DISABLE,
	196	EFCH_PM_DECODEEN_SECOND_RES);
	197	break;
740fbddf TT	198	}
	199	}
	200
7cd9d5ff	201	static u32 sp5100_tco_read_pm_reg32(u8 index)
2b750cff GR	202	{
	203	u32 val = 0;
	204	int i;
	205
	206	for (i = 3; i >= 0; i--)
	207	val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
	208
	209	return val;
	210	}
	211
7cd9d5ff GR	212	static int sp5100_tco_setupdevice(struct device *dev,
7cd9d5ff GR	213	struct watchdog_device *wdd)
15e28bf1	214	{
7cd9d5ff GR	215	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
7cd9d5ff GR	216	const char *dev_name;
887d2ec5	217	u32 mmio_addr = 0, val;
23dfe140	218	int ret;
15e28bf1	219
15e28bf1	220	/* Request the IO ports used by this driver */
16e7730b	221	if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
887d2ec5	222	SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
fd8f9093 GR	223	dev_err(dev, "I/O address 0x%04x already in use\n",
fd8f9093 GR	224	SP5100_IO_PM_INDEX_REG);
23dfe140	225	return -EBUSY;
15e28bf1 PG	226	}
15e28bf1 PG	227
740fbddf	228	/*
887d2ec5	229	* Determine type of southbridge chipset.
740fbddf	230	*/
887d2ec5 GR	231	switch (tco->tco_reg_layout) {
	232	case sp5100:
	233	dev_name = SP5100_DEVNAME;
	234	mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
	235	0xfffffff8;
	236	break;
	237	case sb800:
	238	dev_name = SB800_DEVNAME;
	239	mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
	240	0xfffffff8;
	241	break;
	242	case efch:
	243	dev_name = SB800_DEVNAME;
	244	val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
	245	if (val & EFCH_PM_DECODEEN_WDT_TMREN)
	246	mmio_addr = EFCH_PM_WDT_ADDR;
	247	break;
	248	default:
	249	return -ENODEV;
	250	}
740fbddf TT	251
740fbddf TT	252	/* Check MMIO address conflict */
887d2ec5 GR	253	if (!mmio_addr \|\|
887d2ec5 GR	254	!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
7cd9d5ff	255	dev_name)) {
887d2ec5 GR	256	if (mmio_addr)
	257	dev_dbg(dev, "MMIO address 0x%08x already in use\n",
	258	mmio_addr);
	259	switch (tco->tco_reg_layout) {
	260	case sp5100:
	261	/*
	262	* Secondly, Find the watchdog timer MMIO address
	263	* from SBResource_MMIO register.
	264	*/
e189410c GR	265	/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
	266	pci_read_config_dword(sp5100_tco_pci,
	267	SP5100_SB_RESOURCE_MMIO_BASE,
887d2ec5 GR	268	&mmio_addr);
	269	if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN \|
	270	SB800_ACPI_MMIO_SEL)) !=
	271	SB800_ACPI_MMIO_DECODE_EN) {
	272	ret = -ENODEV;
	273	goto unreg_region;
	274	}
	275	mmio_addr &= ~0xFFF;
	276	mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
	277	break;
	278	case sb800:
e189410c	279	/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
887d2ec5 GR	280	mmio_addr =
	281	sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
	282	if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN \|
	283	SB800_ACPI_MMIO_SEL)) !=
740fbddf	284	SB800_ACPI_MMIO_DECODE_EN) {
887d2ec5 GR	285	ret = -ENODEV;
	286	goto unreg_region;
	287	}
	288	mmio_addr &= ~0xFFF;
	289	mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
	290	break;
	291	case efch:
	292	val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
	293	if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
	294	ret = -ENODEV;
	295	goto unreg_region;
	296	}
	297	mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
	298	EFCH_PM_ACPI_MMIO_WDT_OFFSET;
	299	break;
e189410c	300	}
887d2ec5 GR	301	dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
	302	mmio_addr);
	303	if (!devm_request_mem_region(dev, mmio_addr,
	304	SP5100_WDT_MEM_MAP_SIZE,
7cd9d5ff	305	dev_name)) {
887d2ec5 GR	306	dev_dbg(dev, "MMIO address 0x%08x already in use\n",
887d2ec5 GR	307	mmio_addr);
e189410c GR	308	ret = -EBUSY;
	309	goto unreg_region;
	310	}
e189410c	311	}
740fbddf	312
887d2ec5	313	tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
7cd9d5ff	314	if (!tco->tcobase) {
fd8f9093	315	dev_err(dev, "failed to get tcobase address\n");
23dfe140	316	ret = -ENOMEM;
7cd9d5ff	317	goto unreg_region;
15e28bf1 PG	318	}
15e28bf1 PG	319
887d2ec5	320	dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
15e28bf1	321
740fbddf	322	/* Setup the watchdog timer */
887d2ec5	323	tco_timer_enable(tco);
15e28bf1	324
7cd9d5ff	325	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
f7781b06 GR	326	if (val & SP5100_WDT_DISABLED) {
	327	dev_err(dev, "Watchdog hardware is disabled\n");
	328	ret = -ENODEV;
	329	goto unreg_region;
	330	}
	331
740fbddf TT	332	/*
	333	* Save WatchDogFired status, because WatchDogFired flag is
	334	* cleared here.
	335	*/
7cd9d5ff GR	336	if (val & SP5100_WDT_FIRED)
7cd9d5ff GR	337	wdd->bootstatus = WDIOF_CARDRESET;
f7781b06	338	/* Set watchdog action to reset the system */
5bbecc5d	339	val &= ~SP5100_WDT_ACTION_RESET;
7cd9d5ff	340	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1 PG	341
15e28bf1 PG	342	/* Set a reasonable heartbeat before we stop the timer */
7cd9d5ff	343	tco_timer_set_timeout(wdd, wdd->timeout);
15e28bf1 PG	344
	345	/*
	346	* Stop the TCO before we change anything so we don't race with
	347	* a zeroed timer.
	348	*/
7cd9d5ff	349	tco_timer_stop(wdd);
15e28bf1	350
16e7730b	351	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
e189410c	352
23dfe140	353	return 0;
15e28bf1	354
15e28bf1	355	unreg_region:
2b750cff	356	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
23dfe140	357	return ret;
15e28bf1 PG	358	}
15e28bf1 PG	359
7cd9d5ff GR	360	static struct watchdog_info sp5100_tco_wdt_info = {
	361	.identity = "SP5100 TCO timer",
	362	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	363	};
	364
	365	static const struct watchdog_ops sp5100_tco_wdt_ops = {
	366	.owner = THIS_MODULE,
	367	.start = tco_timer_start,
	368	.stop = tco_timer_stop,
	369	.ping = tco_timer_ping,
	370	.set_timeout = tco_timer_set_timeout,
	371	};
	372
5bbecc5d	373	static int sp5100_tco_probe(struct platform_device *pdev)
15e28bf1	374	{
fd8f9093	375	struct device *dev = &pdev->dev;
7cd9d5ff GR	376	struct watchdog_device *wdd;
7cd9d5ff GR	377	struct sp5100_tco *tco;
15e28bf1	378	int ret;
15e28bf1	379
7cd9d5ff GR	380	tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
	381	if (!tco)
	382	return -ENOMEM;
	383
887d2ec5 GR	384	tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
887d2ec5 GR	385
7cd9d5ff GR	386	wdd = &tco->wdd;
	387	wdd->parent = dev;
	388	wdd->info = &sp5100_tco_wdt_info;
	389	wdd->ops = &sp5100_tco_wdt_ops;
	390	wdd->timeout = WATCHDOG_HEARTBEAT;
	391	wdd->min_timeout = 1;
	392	wdd->max_timeout = 0xffff;
	393
2d505e3e	394	watchdog_init_timeout(wdd, heartbeat, NULL);
7cd9d5ff GR	395	watchdog_set_nowayout(wdd, nowayout);
	396	watchdog_stop_on_reboot(wdd);
	397	watchdog_stop_on_unregister(wdd);
	398	watchdog_set_drvdata(wdd, tco);
	399
	400	ret = sp5100_tco_setupdevice(dev, wdd);
23dfe140 GR	401	if (ret)
23dfe140 GR	402	return ret;
15e28bf1	403
7cd9d5ff	404	ret = devm_watchdog_register_device(dev, wdd);
d41e3f4e	405	if (ret)
7cd9d5ff	406	return ret;
15e28bf1	407
740fbddf	408	/* Show module parameters */
7cd9d5ff GR	409	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
7cd9d5ff GR	410	wdd->timeout, nowayout);
15e28bf1 PG	411
15e28bf1 PG	412	return 0;
15e28bf1 PG	413	}
	414
	415	static struct platform_driver sp5100_tco_driver = {
5bbecc5d	416	.probe = sp5100_tco_probe,
15e28bf1	417	.driver = {
7cd9d5ff	418	.name = TCO_DRIVER_NAME,
15e28bf1 PG	419	},
	420	};
	421
a3483443 GR	422	/*
	423	* Data for PCI driver interface
	424	*
	425	* This data only exists for exporting the supported
	426	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
	427	* register a pci_driver, because someone else might
	428	* want to register another driver on the same PCI id.
	429	*/
	430	static const struct pci_device_id sp5100_tco_pci_tbl[] = {
	431	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
	432	PCI_ANY_ID, },
	433	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
	434	PCI_ANY_ID, },
	435	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
	436	PCI_ANY_ID, },
	437	{ 0, }, /* End of list */
	438	};
	439	MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
	440
5bbecc5d	441	static int __init sp5100_tco_init(void)
15e28bf1	442	{
a3483443	443	struct pci_dev *dev = NULL;
15e28bf1 PG	444	int err;
15e28bf1 PG	445
a3483443 GR	446	/* Match the PCI device */
	447	for_each_pci_dev(dev) {
	448	if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
	449	sp5100_tco_pci = dev;
	450	break;
	451	}
	452	}
	453
	454	if (!sp5100_tco_pci)
	455	return -ENODEV;
	456
7cd9d5ff	457	pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
15e28bf1 PG	458
	459	err = platform_driver_register(&sp5100_tco_driver);
	460	if (err)
	461	return err;
	462
7cd9d5ff GR	463	sp5100_tco_platform_device =
7cd9d5ff GR	464	platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
15e28bf1 PG	465	if (IS_ERR(sp5100_tco_platform_device)) {
	466	err = PTR_ERR(sp5100_tco_platform_device);
	467	goto unreg_platform_driver;
	468	}
	469
	470	return 0;
	471
	472	unreg_platform_driver:
	473	platform_driver_unregister(&sp5100_tco_driver);
	474	return err;
	475	}
	476
5bbecc5d	477	static void __exit sp5100_tco_exit(void)
15e28bf1 PG	478	{
	479	platform_device_unregister(sp5100_tco_platform_device);
	480	platform_driver_unregister(&sp5100_tco_driver);
15e28bf1 PG	481	}
15e28bf1 PG	482
5bbecc5d GR	483	module_init(sp5100_tco_init);
5bbecc5d GR	484	module_exit(sp5100_tco_exit);
15e28bf1 PG	485
15e28bf1 PG	486	MODULE_AUTHOR("Priyanka Gupta");
740fbddf	487	MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
15e28bf1	488	MODULE_LICENSE("GPL");