[linux-block.git] / drivers / watchdog / sp5100_tco.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *	sp5100_tco :	TCO timer driver for sp5100 chipsets
 *
 *	(c) Copyright 2009 Google Inc., All Rights Reserved.
 *
 *	Based on i8xx_tco.c:
 *	(c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
 *	Reserved.
 *				https://www.kernelconcepts.de
 *
 *	See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
 *	    AMD Publication 44413 "AMD SP5100 Register Reference Guide"
 *	    AMD Publication 45482 "AMD SB800-Series Southbridges Register
 *	                                                      Reference Guide"
 *	    AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
 *				for AMD Family 16h Models 00h-0Fh Processors"
 *	    AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
 *	    AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
 *				for AMD Family 16h Models 30h-3Fh Processors"
 *	    AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
 *				for AMD Family 17h Model 18h, Revision B1
 *				Processors (PUB)
 *	    AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
 *				for AMD Family 17h Model 20h, Revision A1
 *				Processors (PUB)
 */

/*
 *	Includes, defines, variables, module parameters, ...
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>

#include "sp5100_tco.h"

#define TCO_DRIVER_NAME	"sp5100-tco"

/* internal variables */

enum tco_reg_layout {
	sp5100, sb800, efch, efch_mmio
};

struct sp5100_tco {
	struct watchdog_device wdd;
	void __iomem *tcobase;
	enum tco_reg_layout tco_reg_layout;
};

/* the watchdog platform device */
static struct platform_device *sp5100_tco_platform_device;
/* the associated PCI device */
static struct pci_dev *sp5100_tco_pci;

/* module parameters */

#define WATCHDOG_ACTION 0
static bool action = WATCHDOG_ACTION;
module_param(action, bool, 0);
MODULE_PARM_DESC(action, "Action taken when watchdog expires, 0 to reset, 1 to poweroff (default="
		 __MODULE_STRING(WATCHDOG_ACTION) ")");

#define WATCHDOG_HEARTBEAT 60	/* 60 sec default heartbeat. */
static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
		 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
		" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

/*
 * Some TCO specific functions
 */

static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
{
	if (dev->vendor == PCI_VENDOR_ID_ATI &&
	    dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	    dev->revision < 0x40) {
		return sp5100;
	} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    sp5100_tco_pci->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
	    sp5100_tco_pci->revision >= AMD_ZEN_SMBUS_PCI_REV) {
		return efch_mmio;
	} else if ((dev->vendor == PCI_VENDOR_ID_AMD || dev->vendor == PCI_VENDOR_ID_HYGON) &&
	    ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
	     dev->revision >= 0x41) ||
	    (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
	     dev->revision >= 0x49))) {
		return efch;
	}
	return sb800;
}

static int tco_timer_start(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val |= SP5100_WDT_START_STOP_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	/* This must be a distinct write. */
	val |= SP5100_WDT_TRIGGER_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_stop(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val &= ~SP5100_WDT_START_STOP_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_ping(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	val |= SP5100_WDT_TRIGGER_BIT;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	return 0;
}

static int tco_timer_set_timeout(struct watchdog_device *wdd,
				 unsigned int t)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);

	/* Write new heartbeat to watchdog */
	writel(t, SP5100_WDT_COUNT(tco->tcobase));

	wdd->timeout = t;

	return 0;
}

static unsigned int tco_timer_get_timeleft(struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);

	return readl(SP5100_WDT_COUNT(tco->tcobase));
}

static u8 sp5100_tco_read_pm_reg8(u8 index)
{
	outb(index, SP5100_IO_PM_INDEX_REG);
	return inb(SP5100_IO_PM_DATA_REG);
}

static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
{
	u8 val;

	outb(index, SP5100_IO_PM_INDEX_REG);
	val = inb(SP5100_IO_PM_DATA_REG);
	val &= reset;
	val |= set;
	outb(val, SP5100_IO_PM_DATA_REG);
}

static void tco_timer_enable(struct sp5100_tco *tco)
{
	u32 val;

	switch (tco->tco_reg_layout) {
	case sb800:
		/* For SB800 or later */
		/* Set the Watchdog timer resolution to 1 sec */
		sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
					  0xff, SB800_PM_WATCHDOG_SECOND_RES);

		/* Enable watchdog decode bit and watchdog timer */
		sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
					  ~SB800_PM_WATCHDOG_DISABLE,
					  SB800_PCI_WATCHDOG_DECODE_EN);
		break;
	case sp5100:
		/* For SP5100 or SB7x0 */
		/* Enable watchdog decode bit */
		pci_read_config_dword(sp5100_tco_pci,
				      SP5100_PCI_WATCHDOG_MISC_REG,
				      &val);

		val |= SP5100_PCI_WATCHDOG_DECODE_EN;

		pci_write_config_dword(sp5100_tco_pci,
				       SP5100_PCI_WATCHDOG_MISC_REG,
				       val);

		/* Enable Watchdog timer and set the resolution to 1 sec */
		sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
					  ~SP5100_PM_WATCHDOG_DISABLE,
					  SP5100_PM_WATCHDOG_SECOND_RES);
		break;
	case efch:
		/* Set the Watchdog timer resolution to 1 sec and enable */
		sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
					  ~EFCH_PM_WATCHDOG_DISABLE,
					  EFCH_PM_DECODEEN_SECOND_RES);
		break;
	default:
		break;
	}
}

static u32 sp5100_tco_read_pm_reg32(u8 index)
{
	u32 val = 0;
	int i;

	for (i = 3; i >= 0; i--)
		val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);

	return val;
}

static u32 sp5100_tco_request_region(struct device *dev,
				     u32 mmio_addr,
				     const char *dev_name)
{
	if (!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
				     dev_name)) {
		dev_dbg(dev, "MMIO address 0x%08x already in use\n", mmio_addr);
		return 0;
	}

	return mmio_addr;
}

static u32 sp5100_tco_prepare_base(struct sp5100_tco *tco,
				   u32 mmio_addr,
				   u32 alt_mmio_addr,
				   const char *dev_name)
{
	struct device *dev = tco->wdd.parent;

	dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n", mmio_addr);

	if (!mmio_addr && !alt_mmio_addr)
		return -ENODEV;

	/* Check for MMIO address and alternate MMIO address conflicts */
	if (mmio_addr)
		mmio_addr = sp5100_tco_request_region(dev, mmio_addr, dev_name);

	if (!mmio_addr && alt_mmio_addr)
		mmio_addr = sp5100_tco_request_region(dev, alt_mmio_addr, dev_name);

	if (!mmio_addr) {
		dev_err(dev, "Failed to reserve MMIO or alternate MMIO region\n");
		return -EBUSY;
	}

	tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
	if (!tco->tcobase) {
		dev_err(dev, "MMIO address 0x%08x failed mapping\n", mmio_addr);
		devm_release_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
		return -ENOMEM;
	}

	dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);

	return 0;
}

static int sp5100_tco_timer_init(struct sp5100_tco *tco)
{
	struct watchdog_device *wdd = &tco->wdd;
	struct device *dev = wdd->parent;
	u32 val;

	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	if (val & SP5100_WDT_DISABLED) {
		dev_err(dev, "Watchdog hardware is disabled\n");
		return -ENODEV;
	}

	/*
	 * Save WatchDogFired status, because WatchDogFired flag is
	 * cleared here.
	 */
	if (val & SP5100_WDT_FIRED)
		wdd->bootstatus = WDIOF_CARDRESET;

	/* Set watchdog action */
	if (action)
		val |= SP5100_WDT_ACTION_RESET;
	else
		val &= ~SP5100_WDT_ACTION_RESET;
	writel(val, SP5100_WDT_CONTROL(tco->tcobase));

	/* Set a reasonable heartbeat before we stop the timer */
	tco_timer_set_timeout(wdd, wdd->timeout);

	/*
	 * Stop the TCO before we change anything so we don't race with
	 * a zeroed timer.
	 */
	tco_timer_stop(wdd);

	return 0;
}

static u8 efch_read_pm_reg8(void __iomem *addr, u8 index)
{
	return readb(addr + index);
}

static void efch_update_pm_reg8(void __iomem *addr, u8 index, u8 reset, u8 set)
{
	u8 val;

	val = readb(addr + index);
	val &= reset;
	val |= set;
	writeb(val, addr + index);
}

static void tco_timer_enable_mmio(void __iomem *addr)
{
	efch_update_pm_reg8(addr, EFCH_PM_DECODEEN3,
			    ~EFCH_PM_WATCHDOG_DISABLE,
			    EFCH_PM_DECODEEN_SECOND_RES);
}

static int sp5100_tco_setupdevice_mmio(struct device *dev,
				       struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	const char *dev_name = SB800_DEVNAME;
	u32 mmio_addr = 0, alt_mmio_addr = 0;
	struct resource *res;
	void __iomem *addr;
	int ret;
	u32 val;

	res = request_mem_region_muxed(EFCH_PM_ACPI_MMIO_PM_ADDR,
				       EFCH_PM_ACPI_MMIO_PM_SIZE,
				       "sp5100_tco");

	if (!res) {
		dev_err(dev,
			"Memory region 0x%08x already in use\n",
			EFCH_PM_ACPI_MMIO_PM_ADDR);
		return -EBUSY;
	}

	addr = ioremap(EFCH_PM_ACPI_MMIO_PM_ADDR, EFCH_PM_ACPI_MMIO_PM_SIZE);
	if (!addr) {
		dev_err(dev, "Address mapping failed\n");
		ret = -ENOMEM;
		goto out;
	}

	/*
	 * EFCH_PM_DECODEEN_WDT_TMREN is dual purpose. This bitfield
	 * enables sp5100_tco register MMIO space decoding. The bitfield
	 * also starts the timer operation. Enable if not already enabled.
	 */
	val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
	if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
		efch_update_pm_reg8(addr, EFCH_PM_DECODEEN, 0xff,
				    EFCH_PM_DECODEEN_WDT_TMREN);
	}

	/* Error if the timer could not be enabled */
	val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
	if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
		dev_err(dev, "Failed to enable the timer\n");
		ret = -EFAULT;
		goto out;
	}

	mmio_addr = EFCH_PM_WDT_ADDR;

	/* Determine alternate MMIO base address */
	val = efch_read_pm_reg8(addr, EFCH_PM_ISACONTROL);
	if (val & EFCH_PM_ISACONTROL_MMIOEN)
		alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
			EFCH_PM_ACPI_MMIO_WDT_OFFSET;

	ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
	if (!ret) {
		tco_timer_enable_mmio(addr);
		ret = sp5100_tco_timer_init(tco);
	}

out:
	if (addr)
		iounmap(addr);

	release_resource(res);
	kfree(res);

	return ret;
}

static int sp5100_tco_setupdevice(struct device *dev,
				  struct watchdog_device *wdd)
{
	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	const char *dev_name;
	u32 mmio_addr = 0, val;
	u32 alt_mmio_addr = 0;
	int ret;

	if (tco->tco_reg_layout == efch_mmio)
		return sp5100_tco_setupdevice_mmio(dev, wdd);

	/* Request the IO ports used by this driver */
	if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
				  SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
		dev_err(dev, "I/O address 0x%04x already in use\n",
			SP5100_IO_PM_INDEX_REG);
		return -EBUSY;
	}

	/*
	 * Determine type of southbridge chipset.
	 */
	switch (tco->tco_reg_layout) {
	case sp5100:
		dev_name = SP5100_DEVNAME;
		mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
								0xfffffff8;

		/*
		 * Secondly, find the watchdog timer MMIO address
		 * from SBResource_MMIO register.
		 */

		/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
		pci_read_config_dword(sp5100_tco_pci,
				      SP5100_SB_RESOURCE_MMIO_BASE,
				      &val);

		/* Verify MMIO is enabled and using bar0 */
		if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
			alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
		break;
	case sb800:
		dev_name = SB800_DEVNAME;
		mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
								0xfffffff8;

		/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
		val = sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);

		/* Verify MMIO is enabled and using bar0 */
		if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
			alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
		break;
	case efch:
		dev_name = SB800_DEVNAME;
		val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
		if (val & EFCH_PM_DECODEEN_WDT_TMREN)
			mmio_addr = EFCH_PM_WDT_ADDR;

		val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
		if (val & EFCH_PM_ISACONTROL_MMIOEN)
			alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
				EFCH_PM_ACPI_MMIO_WDT_OFFSET;
		break;
	default:
		return -ENODEV;
	}

	ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
	if (!ret) {
		/* Setup the watchdog timer */
		tco_timer_enable(tco);
		ret = sp5100_tco_timer_init(tco);
	}

	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
	return ret;
}

static struct watchdog_info sp5100_tco_wdt_info = {
	.identity = "SP5100 TCO timer",
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops sp5100_tco_wdt_ops = {
	.owner = THIS_MODULE,
	.start = tco_timer_start,
	.stop = tco_timer_stop,
	.ping = tco_timer_ping,
	.set_timeout = tco_timer_set_timeout,
	.get_timeleft = tco_timer_get_timeleft,
};

static int sp5100_tco_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct sp5100_tco *tco;
	int ret;

	tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
	if (!tco)
		return -ENOMEM;

	tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);

	wdd = &tco->wdd;
	wdd->parent = dev;
	wdd->info = &sp5100_tco_wdt_info;
	wdd->ops = &sp5100_tco_wdt_ops;
	wdd->timeout = WATCHDOG_HEARTBEAT;
	wdd->min_timeout = 1;
	wdd->max_timeout = 0xffff;

	watchdog_init_timeout(wdd, heartbeat, NULL);
	watchdog_set_nowayout(wdd, nowayout);
	watchdog_stop_on_reboot(wdd);
	watchdog_stop_on_unregister(wdd);
	watchdog_set_drvdata(wdd, tco);

	ret = sp5100_tco_setupdevice(dev, wdd);
	if (ret)
		return ret;

	ret = devm_watchdog_register_device(dev, wdd);
	if (ret)
		return ret;

	/* Show module parameters */
	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
		 wdd->timeout, nowayout);

	return 0;
}

static struct platform_driver sp5100_tco_driver = {
	.probe		= sp5100_tco_probe,
	.driver		= {
		.name	= TCO_DRIVER_NAME,
	},
};

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because someone else might
 * want to register another driver on the same PCI id.
 */
static const struct pci_device_id sp5100_tco_pci_tbl[] = {
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ 0, },			/* End of list */
};
MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);

static int __init sp5100_tco_init(void)
{
	struct pci_dev *dev = NULL;
	int err;

	/* Match the PCI device */
	for_each_pci_dev(dev) {
		if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
			sp5100_tco_pci = dev;
			break;
		}
	}

	if (!sp5100_tco_pci)
		return -ENODEV;

	pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");

	err = platform_driver_register(&sp5100_tco_driver);
	if (err)
		return err;

	sp5100_tco_platform_device =
		platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
	if (IS_ERR(sp5100_tco_platform_device)) {
		err = PTR_ERR(sp5100_tco_platform_device);
		goto unreg_platform_driver;
	}

	return 0;

unreg_platform_driver:
	platform_driver_unregister(&sp5100_tco_driver);
	return err;
}

static void __exit sp5100_tco_exit(void)
{
	platform_device_unregister(sp5100_tco_platform_device);
	platform_driver_unregister(&sp5100_tco_driver);
}

module_init(sp5100_tco_init);
module_exit(sp5100_tco_exit);

MODULE_AUTHOR("Priyanka Gupta");
MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
15e28bf1 PG	2	/*
	3	* sp5100_tco : TCO timer driver for sp5100 chipsets
	4	*
	5	* (c) Copyright 2009 Google Inc., All Rights Reserved.
	6	*
	7	* Based on i8xx_tco.c:
	8	* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
	9	* Reserved.
2ab77a34	10	* https://www.kernelconcepts.de
15e28bf1	11	*
740fbddf	12	* See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
4d3d50f6	13	* AMD Publication 44413 "AMD SP5100 Register Reference Guide"
740fbddf TT	14	* AMD Publication 45482 "AMD SB800-Series Southbridges Register
740fbddf TT	15	* Reference Guide"
887d2ec5 GR	16	* AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
	17	* for AMD Family 16h Models 00h-0Fh Processors"
	18	* AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
	19	* AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
	20	* for AMD Family 16h Models 30h-3Fh Processors"
09da89ab GR	21	* AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
	22	* for AMD Family 17h Model 18h, Revision B1
	23	* Processors (PUB)
	24	* AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
	25	* for AMD Family 17h Model 20h, Revision A1
	26	* Processors (PUB)
15e28bf1 PG	27	*/
	28
	29	/*
	30	* Includes, defines, variables, module parameters, ...
	31	*/
	32
27c766aa JP	33	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	34
7cd9d5ff GR	35	#include <linux/init.h>
	36	#include <linux/io.h>
	37	#include <linux/ioport.h>
15e28bf1 PG	38	#include <linux/module.h>
15e28bf1 PG	39	#include <linux/moduleparam.h>
15e28bf1	40	#include <linux/pci.h>
15e28bf1	41	#include <linux/platform_device.h>
7cd9d5ff GR	42	#include <linux/types.h>
7cd9d5ff GR	43	#include <linux/watchdog.h>
15e28bf1 PG	44
	45	#include "sp5100_tco.h"
	46
7cd9d5ff	47	#define TCO_DRIVER_NAME "sp5100-tco"
15e28bf1 PG	48
15e28bf1 PG	49	/* internal variables */
7cd9d5ff	50
887d2ec5	51	enum tco_reg_layout {
0578fff4	52	sp5100, sb800, efch, efch_mmio
887d2ec5 GR	53	};
887d2ec5 GR	54
7cd9d5ff GR	55	struct sp5100_tco {
	56	struct watchdog_device wdd;
	57	void __iomem *tcobase;
887d2ec5	58	enum tco_reg_layout tco_reg_layout;
7cd9d5ff	59	};
15e28bf1 PG	60
	61	/* the watchdog platform device */
	62	static struct platform_device *sp5100_tco_platform_device;
7cd9d5ff GR	63	/* the associated PCI device */
7cd9d5ff GR	64	static struct pci_dev *sp5100_tco_pci;
15e28bf1 PG	65
	66	/* module parameters */
	67
081574f7 VP	68	#define WATCHDOG_ACTION 0
	69	static bool action = WATCHDOG_ACTION;
	70	module_param(action, bool, 0);
	71	MODULE_PARM_DESC(action, "Action taken when watchdog expires, 0 to reset, 1 to poweroff (default="
	72	__MODULE_STRING(WATCHDOG_ACTION) ")");
	73
15e28bf1 PG	74	#define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
	75	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
	76	module_param(heartbeat, int, 0);
	77	MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
	78	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
	79
86a1e189 WVS	80	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	81	module_param(nowayout, bool, 0);
740fbddf	82	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
15e28bf1 PG	83	" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	84
	85	/*
	86	* Some TCO specific functions
	87	*/
46856fab	88
887d2ec5	89	static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
46856fab	90	{
887d2ec5 GR	91	if (dev->vendor == PCI_VENDOR_ID_ATI &&
	92	dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	93	dev->revision < 0x40) {
	94	return sp5100;
82627037 TB	95	} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	96	sp5100_tco_pci->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
	97	sp5100_tco_pci->revision >= AMD_ZEN_SMBUS_PCI_REV) {
	98	return efch_mmio;
009637de	99	} else if ((dev->vendor == PCI_VENDOR_ID_AMD \|\| dev->vendor == PCI_VENDOR_ID_HYGON) &&
887d2ec5 GR	100	((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
	101	dev->revision >= 0x41) \|\|
	102	(dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
	103	dev->revision >= 0x49))) {
	104	return efch;
	105	}
	106	return sb800;
46856fab LS	107	}
46856fab LS	108
7cd9d5ff	109	static int tco_timer_start(struct watchdog_device *wdd)
15e28bf1	110	{
7cd9d5ff	111	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	112	u32 val;
15e28bf1	113
7cd9d5ff	114	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	115	val \|= SP5100_WDT_START_STOP_BIT;
7cd9d5ff GR	116	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
7cd9d5ff GR	117
4eda19cc GO	118	/* This must be a distinct write. */
	119	val \|= SP5100_WDT_TRIGGER_BIT;
	120	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	121
7cd9d5ff	122	return 0;
15e28bf1 PG	123	}
15e28bf1 PG	124
7cd9d5ff	125	static int tco_timer_stop(struct watchdog_device *wdd)
15e28bf1	126	{
7cd9d5ff	127	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	128	u32 val;
15e28bf1	129
7cd9d5ff	130	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	131	val &= ~SP5100_WDT_START_STOP_BIT;
7cd9d5ff GR	132	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	133
	134	return 0;
15e28bf1 PG	135	}
15e28bf1 PG	136
7cd9d5ff	137	static int tco_timer_ping(struct watchdog_device *wdd)
15e28bf1	138	{
7cd9d5ff	139	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1	140	u32 val;
15e28bf1	141
7cd9d5ff	142	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
15e28bf1	143	val \|= SP5100_WDT_TRIGGER_BIT;
7cd9d5ff GR	144	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	145
	146	return 0;
15e28bf1 PG	147	}
15e28bf1 PG	148
7cd9d5ff GR	149	static int tco_timer_set_timeout(struct watchdog_device *wdd,
7cd9d5ff GR	150	unsigned int t)
15e28bf1	151	{
7cd9d5ff	152	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
15e28bf1 PG	153
15e28bf1 PG	154	/* Write new heartbeat to watchdog */
7cd9d5ff GR	155	writel(t, SP5100_WDT_COUNT(tco->tcobase));
	156
	157	wdd->timeout = t;
15e28bf1	158
15e28bf1 PG	159	return 0;
	160	}
	161
4d3d50f6 TW	162	static unsigned int tco_timer_get_timeleft(struct watchdog_device *wdd)
	163	{
	164	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	165
	166	return readl(SP5100_WDT_COUNT(tco->tcobase));
	167	}
	168
2b750cff GR	169	static u8 sp5100_tco_read_pm_reg8(u8 index)
	170	{
	171	outb(index, SP5100_IO_PM_INDEX_REG);
	172	return inb(SP5100_IO_PM_DATA_REG);
	173	}
	174
	175	static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
740fbddf	176	{
2b750cff	177	u8 val;
740fbddf	178
2b750cff GR	179	outb(index, SP5100_IO_PM_INDEX_REG);
	180	val = inb(SP5100_IO_PM_DATA_REG);
	181	val &= reset;
	182	val \|= set;
	183	outb(val, SP5100_IO_PM_DATA_REG);
	184	}
	185
887d2ec5	186	static void tco_timer_enable(struct sp5100_tco *tco)
2b750cff	187	{
887d2ec5 GR	188	u32 val;
	189
	190	switch (tco->tco_reg_layout) {
	191	case sb800:
740fbddf TT	192	/* For SB800 or later */
740fbddf TT	193	/* Set the Watchdog timer resolution to 1 sec */
2b750cff GR	194	sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
2b750cff GR	195	0xff, SB800_PM_WATCHDOG_SECOND_RES);
740fbddf TT	196
740fbddf TT	197	/* Enable watchdog decode bit and watchdog timer */
2b750cff GR	198	sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
	199	~SB800_PM_WATCHDOG_DISABLE,
	200	SB800_PCI_WATCHDOG_DECODE_EN);
887d2ec5 GR	201	break;
887d2ec5 GR	202	case sp5100:
740fbddf TT	203	/* For SP5100 or SB7x0 */
	204	/* Enable watchdog decode bit */
	205	pci_read_config_dword(sp5100_tco_pci,
	206	SP5100_PCI_WATCHDOG_MISC_REG,
	207	&val);
	208
	209	val \|= SP5100_PCI_WATCHDOG_DECODE_EN;
	210
	211	pci_write_config_dword(sp5100_tco_pci,
	212	SP5100_PCI_WATCHDOG_MISC_REG,
	213	val);
	214
	215	/* Enable Watchdog timer and set the resolution to 1 sec */
2b750cff GR	216	sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
	217	~SP5100_PM_WATCHDOG_DISABLE,
	218	SP5100_PM_WATCHDOG_SECOND_RES);
887d2ec5 GR	219	break;
	220	case efch:
	221	/* Set the Watchdog timer resolution to 1 sec and enable */
	222	sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
	223	~EFCH_PM_WATCHDOG_DISABLE,
	224	EFCH_PM_DECODEEN_SECOND_RES);
	225	break;
0578fff4 TB	226	default:
0578fff4 TB	227	break;
740fbddf TT	228	}
	229	}
	230
7cd9d5ff	231	static u32 sp5100_tco_read_pm_reg32(u8 index)
2b750cff GR	232	{
	233	u32 val = 0;
	234	int i;
	235
	236	for (i = 3; i >= 0; i--)
	237	val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
	238
	239	return val;
	240	}
	241
1f182aca TB	242	static u32 sp5100_tco_request_region(struct device *dev,
	243	u32 mmio_addr,
	244	const char *dev_name)
	245	{
	246	if (!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
	247	dev_name)) {
	248	dev_dbg(dev, "MMIO address 0x%08x already in use\n", mmio_addr);
	249	return 0;
	250	}
	251
	252	return mmio_addr;
	253	}
	254
	255	static u32 sp5100_tco_prepare_base(struct sp5100_tco *tco,
	256	u32 mmio_addr,
	257	u32 alt_mmio_addr,
	258	const char *dev_name)
	259	{
	260	struct device *dev = tco->wdd.parent;
	261
	262	dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n", mmio_addr);
	263
	264	if (!mmio_addr && !alt_mmio_addr)
	265	return -ENODEV;
	266
	267	/* Check for MMIO address and alternate MMIO address conflicts */
	268	if (mmio_addr)
	269	mmio_addr = sp5100_tco_request_region(dev, mmio_addr, dev_name);
	270
	271	if (!mmio_addr && alt_mmio_addr)
	272	mmio_addr = sp5100_tco_request_region(dev, alt_mmio_addr, dev_name);
	273
	274	if (!mmio_addr) {
	275	dev_err(dev, "Failed to reserve MMIO or alternate MMIO region\n");
	276	return -EBUSY;
	277	}
	278
	279	tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
	280	if (!tco->tcobase) {
	281	dev_err(dev, "MMIO address 0x%08x failed mapping\n", mmio_addr);
	282	devm_release_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
	283	return -ENOMEM;
	284	}
	285
	286	dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
	287
	288	return 0;
	289	}
	290
abd71a94 TB	291	static int sp5100_tco_timer_init(struct sp5100_tco *tco)
	292	{
	293	struct watchdog_device *wdd = &tco->wdd;
	294	struct device *dev = wdd->parent;
	295	u32 val;
	296
	297	val = readl(SP5100_WDT_CONTROL(tco->tcobase));
	298	if (val & SP5100_WDT_DISABLED) {
	299	dev_err(dev, "Watchdog hardware is disabled\n");
	300	return -ENODEV;
	301	}
	302
	303	/*
	304	* Save WatchDogFired status, because WatchDogFired flag is
	305	* cleared here.
	306	*/
	307	if (val & SP5100_WDT_FIRED)
	308	wdd->bootstatus = WDIOF_CARDRESET;
	309
081574f7 VP	310	/* Set watchdog action */
	311	if (action)
	312	val \|= SP5100_WDT_ACTION_RESET;
	313	else
	314	val &= ~SP5100_WDT_ACTION_RESET;
abd71a94 TB	315	writel(val, SP5100_WDT_CONTROL(tco->tcobase));
	316
	317	/* Set a reasonable heartbeat before we stop the timer */
	318	tco_timer_set_timeout(wdd, wdd->timeout);
	319
	320	/*
	321	* Stop the TCO before we change anything so we don't race with
	322	* a zeroed timer.
	323	*/
	324	tco_timer_stop(wdd);
	325
	326	return 0;
	327	}
	328
0578fff4 TB	329	static u8 efch_read_pm_reg8(void __iomem *addr, u8 index)
	330	{
	331	return readb(addr + index);
	332	}
	333
	334	static void efch_update_pm_reg8(void __iomem *addr, u8 index, u8 reset, u8 set)
	335	{
	336	u8 val;
	337
	338	val = readb(addr + index);
	339	val &= reset;
	340	val \|= set;
	341	writeb(val, addr + index);
	342	}
	343
	344	static void tco_timer_enable_mmio(void __iomem *addr)
	345	{
	346	efch_update_pm_reg8(addr, EFCH_PM_DECODEEN3,
	347	~EFCH_PM_WATCHDOG_DISABLE,
	348	EFCH_PM_DECODEEN_SECOND_RES);
	349	}
	350
	351	static int sp5100_tco_setupdevice_mmio(struct device *dev,
	352	struct watchdog_device *wdd)
	353	{
	354	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
	355	const char *dev_name = SB800_DEVNAME;
	356	u32 mmio_addr = 0, alt_mmio_addr = 0;
	357	struct resource *res;
	358	void __iomem *addr;
	359	int ret;
	360	u32 val;
	361
	362	res = request_mem_region_muxed(EFCH_PM_ACPI_MMIO_PM_ADDR,
	363	EFCH_PM_ACPI_MMIO_PM_SIZE,
	364	"sp5100_tco");
	365
	366	if (!res) {
	367	dev_err(dev,
	368	"Memory region 0x%08x already in use\n",
	369	EFCH_PM_ACPI_MMIO_PM_ADDR);
	370	return -EBUSY;
	371	}
	372
	373	addr = ioremap(EFCH_PM_ACPI_MMIO_PM_ADDR, EFCH_PM_ACPI_MMIO_PM_SIZE);
	374	if (!addr) {
	375	dev_err(dev, "Address mapping failed\n");
	376	ret = -ENOMEM;
	377	goto out;
	378	}
	379
	380	/*
	381	* EFCH_PM_DECODEEN_WDT_TMREN is dual purpose. This bitfield
	382	* enables sp5100_tco register MMIO space decoding. The bitfield
	383	* also starts the timer operation. Enable if not already enabled.
	384	*/
	385	val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
	386	if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
	387	efch_update_pm_reg8(addr, EFCH_PM_DECODEEN, 0xff,
	388	EFCH_PM_DECODEEN_WDT_TMREN);
	389	}
	390
	391	/* Error if the timer could not be enabled */
	392	val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
393	if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
394	dev_err(dev, "Failed to enable the timer\n");
395	ret = -EFAULT;
396	goto out;
397	}
398
399	mmio_addr = EFCH_PM_WDT_ADDR;
400
401	/* Determine alternate MMIO base address */
402	val = efch_read_pm_reg8(addr, EFCH_PM_ISACONTROL);
403	if (val & EFCH_PM_ISACONTROL_MMIOEN)
404	alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
405	EFCH_PM_ACPI_MMIO_WDT_OFFSET;
406
407	ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
408	if (!ret) {
409	tco_timer_enable_mmio(addr);
410	ret = sp5100_tco_timer_init(tco);
411	}
412
413	out:
414	if (addr)
415	iounmap(addr);
416
417	release_resource(res);
c6d9c079	418	kfree(res);
0578fff4 TB	419
	420	return ret;
	421	}
	422
7cd9d5ff GR	423	static int sp5100_tco_setupdevice(struct device *dev,
7cd9d5ff GR	424	struct watchdog_device *wdd)
15e28bf1	425	{
7cd9d5ff GR	426	struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
7cd9d5ff GR	427	const char *dev_name;
887d2ec5	428	u32 mmio_addr = 0, val;
1f182aca	429	u32 alt_mmio_addr = 0;
23dfe140	430	int ret;
15e28bf1	431
0578fff4 TB	432	if (tco->tco_reg_layout == efch_mmio)
	433	return sp5100_tco_setupdevice_mmio(dev, wdd);
	434
15e28bf1	435	/* Request the IO ports used by this driver */
16e7730b	436	if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
887d2ec5	437	SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
fd8f9093 GR	438	dev_err(dev, "I/O address 0x%04x already in use\n",
fd8f9093 GR	439	SP5100_IO_PM_INDEX_REG);
23dfe140	440	return -EBUSY;
15e28bf1 PG	441	}
15e28bf1 PG	442
740fbddf	443	/*
887d2ec5	444	* Determine type of southbridge chipset.
740fbddf	445	*/
887d2ec5 GR	446	switch (tco->tco_reg_layout) {
	447	case sp5100:
	448	dev_name = SP5100_DEVNAME;
	449	mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
	450	0xfffffff8;
1f182aca TB	451
	452	/*
	453	* Secondly, find the watchdog timer MMIO address
	454	* from SBResource_MMIO register.
	455	*/
	456
	457	/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
	458	pci_read_config_dword(sp5100_tco_pci,
	459	SP5100_SB_RESOURCE_MMIO_BASE,
	460	&val);
	461
	462	/* Verify MMIO is enabled and using bar0 */
	463	if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
	464	alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
887d2ec5 GR	465	break;
	466	case sb800:
	467	dev_name = SB800_DEVNAME;
	468	mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
	469	0xfffffff8;
1f182aca TB	470
	471	/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
	472	val = sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
	473
	474	/* Verify MMIO is enabled and using bar0 */
	475	if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
	476	alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
887d2ec5 GR	477	break;
	478	case efch:
	479	dev_name = SB800_DEVNAME;
	480	val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
	481	if (val & EFCH_PM_DECODEEN_WDT_TMREN)
	482	mmio_addr = EFCH_PM_WDT_ADDR;
1f182aca TB	483
	484	val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
	485	if (val & EFCH_PM_ISACONTROL_MMIOEN)
	486	alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
	487	EFCH_PM_ACPI_MMIO_WDT_OFFSET;
887d2ec5 GR	488	break;
	489	default:
	490	return -ENODEV;
	491	}
740fbddf	492
1f182aca TB	493	ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
	494	if (!ret) {
	495	/* Setup the watchdog timer */
	496	tco_timer_enable(tco);
	497	ret = sp5100_tco_timer_init(tco);
15e28bf1 PG	498	}
15e28bf1 PG	499
2b750cff	500	release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
23dfe140	501	return ret;
15e28bf1 PG	502	}
15e28bf1 PG	503
7cd9d5ff GR	504	static struct watchdog_info sp5100_tco_wdt_info = {
	505	.identity = "SP5100 TCO timer",
	506	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	507	};
	508
	509	static const struct watchdog_ops sp5100_tco_wdt_ops = {
	510	.owner = THIS_MODULE,
	511	.start = tco_timer_start,
	512	.stop = tco_timer_stop,
	513	.ping = tco_timer_ping,
	514	.set_timeout = tco_timer_set_timeout,
4d3d50f6	515	.get_timeleft = tco_timer_get_timeleft,
7cd9d5ff GR	516	};
7cd9d5ff GR	517
5bbecc5d	518	static int sp5100_tco_probe(struct platform_device *pdev)
15e28bf1	519	{
fd8f9093	520	struct device *dev = &pdev->dev;
7cd9d5ff GR	521	struct watchdog_device *wdd;
7cd9d5ff GR	522	struct sp5100_tco *tco;
15e28bf1	523	int ret;
15e28bf1	524
7cd9d5ff GR	525	tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
	526	if (!tco)
	527	return -ENOMEM;
	528
887d2ec5 GR	529	tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
887d2ec5 GR	530
7cd9d5ff GR	531	wdd = &tco->wdd;
	532	wdd->parent = dev;
	533	wdd->info = &sp5100_tco_wdt_info;
	534	wdd->ops = &sp5100_tco_wdt_ops;
	535	wdd->timeout = WATCHDOG_HEARTBEAT;
	536	wdd->min_timeout = 1;
	537	wdd->max_timeout = 0xffff;
	538
2d505e3e	539	watchdog_init_timeout(wdd, heartbeat, NULL);
7cd9d5ff GR	540	watchdog_set_nowayout(wdd, nowayout);
	541	watchdog_stop_on_reboot(wdd);
	542	watchdog_stop_on_unregister(wdd);
	543	watchdog_set_drvdata(wdd, tco);
	544
	545	ret = sp5100_tco_setupdevice(dev, wdd);
23dfe140 GR	546	if (ret)
23dfe140 GR	547	return ret;
15e28bf1	548
7cd9d5ff	549	ret = devm_watchdog_register_device(dev, wdd);
d41e3f4e	550	if (ret)
7cd9d5ff	551	return ret;
15e28bf1	552
740fbddf	553	/* Show module parameters */
7cd9d5ff GR	554	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
7cd9d5ff GR	555	wdd->timeout, nowayout);
15e28bf1 PG	556
15e28bf1 PG	557	return 0;
15e28bf1 PG	558	}
	559
	560	static struct platform_driver sp5100_tco_driver = {
5bbecc5d	561	.probe = sp5100_tco_probe,
15e28bf1	562	.driver = {
7cd9d5ff	563	.name = TCO_DRIVER_NAME,
15e28bf1 PG	564	},
	565	};
	566
a3483443 GR	567	/*
	568	* Data for PCI driver interface
	569	*
	570	* This data only exists for exporting the supported
	571	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
	572	* register a pci_driver, because someone else might
	573	* want to register another driver on the same PCI id.
	574	*/
	575	static const struct pci_device_id sp5100_tco_pci_tbl[] = {
	576	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
	577	PCI_ANY_ID, },
	578	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
	579	PCI_ANY_ID, },
	580	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
	581	PCI_ANY_ID, },
009637de YZ	582	{ PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
009637de YZ	583	PCI_ANY_ID, },
a3483443 GR	584	{ 0, }, /* End of list */
	585	};
	586	MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
	587
5bbecc5d	588	static int __init sp5100_tco_init(void)
15e28bf1	589	{
a3483443	590	struct pci_dev *dev = NULL;
15e28bf1 PG	591	int err;
15e28bf1 PG	592
a3483443 GR	593	/* Match the PCI device */
	594	for_each_pci_dev(dev) {
	595	if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
	596	sp5100_tco_pci = dev;
	597	break;
	598	}
	599	}
	600
	601	if (!sp5100_tco_pci)
	602	return -ENODEV;
	603
7cd9d5ff	604	pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
15e28bf1 PG	605
	606	err = platform_driver_register(&sp5100_tco_driver);
	607	if (err)
	608	return err;
	609
7cd9d5ff GR	610	sp5100_tco_platform_device =
7cd9d5ff GR	611	platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
15e28bf1 PG	612	if (IS_ERR(sp5100_tco_platform_device)) {
	613	err = PTR_ERR(sp5100_tco_platform_device);
	614	goto unreg_platform_driver;
	615	}
	616
	617	return 0;
	618
	619	unreg_platform_driver:
	620	platform_driver_unregister(&sp5100_tco_driver);
	621	return err;
	622	}
	623
5bbecc5d	624	static void __exit sp5100_tco_exit(void)
15e28bf1 PG	625	{
	626	platform_device_unregister(sp5100_tco_platform_device);
	627	platform_driver_unregister(&sp5100_tco_driver);
15e28bf1 PG	628	}
15e28bf1 PG	629
5bbecc5d GR	630	module_init(sp5100_tco_init);
5bbecc5d GR	631	module_exit(sp5100_tco_exit);
15e28bf1 PG	632
15e28bf1 PG	633	MODULE_AUTHOR("Priyanka Gupta");
740fbddf	634	MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
15e28bf1	635	MODULE_LICENSE("GPL");