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f50a7f3d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
76534860 WY |
2 | /* |
3 | * Driver for Atmel SAMA5D4 Watchdog Timer | |
4 | * | |
5 | * Copyright (C) 2015 Atmel Corporation | |
76534860 WY |
6 | */ |
7 | ||
ddd6d240 | 8 | #include <linux/delay.h> |
76534860 WY |
9 | #include <linux/interrupt.h> |
10 | #include <linux/io.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_irq.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/reboot.h> | |
17 | #include <linux/watchdog.h> | |
18 | ||
19 | #include "at91sam9_wdt.h" | |
20 | ||
21 | /* minimum and maximum watchdog timeout, in seconds */ | |
22 | #define MIN_WDT_TIMEOUT 1 | |
23 | #define MAX_WDT_TIMEOUT 16 | |
24 | #define WDT_DEFAULT_TIMEOUT MAX_WDT_TIMEOUT | |
25 | ||
26 | #define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0) | |
27 | ||
28 | struct sama5d4_wdt { | |
29 | struct watchdog_device wdd; | |
30 | void __iomem *reg_base; | |
722ce635 | 31 | u32 mr; |
ddd6d240 | 32 | unsigned long last_ping; |
76534860 WY |
33 | }; |
34 | ||
976932e4 | 35 | static int wdt_timeout; |
76534860 WY |
36 | static bool nowayout = WATCHDOG_NOWAYOUT; |
37 | ||
38 | module_param(wdt_timeout, int, 0); | |
39 | MODULE_PARM_DESC(wdt_timeout, | |
40 | "Watchdog timeout in seconds. (default = " | |
41 | __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")"); | |
42 | ||
43 | module_param(nowayout, bool, 0); | |
44 | MODULE_PARM_DESC(nowayout, | |
45 | "Watchdog cannot be stopped once started (default=" | |
46 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
47 | ||
015b5286 AB |
48 | #define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS)) |
49 | ||
76534860 WY |
50 | #define wdt_read(wdt, field) \ |
51 | readl_relaxed((wdt)->reg_base + (field)) | |
52 | ||
ddd6d240 AB |
53 | /* 4 slow clock periods is 4/32768 = 122.07µs*/ |
54 | #define WDT_DELAY usecs_to_jiffies(123) | |
55 | ||
56 | static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) | |
57 | { | |
58 | /* | |
59 | * WDT_CR and WDT_MR must not be modified within three slow clock | |
60 | * periods following a restart of the watchdog performed by a write | |
61 | * access in WDT_CR. | |
62 | */ | |
63 | while (time_before(jiffies, wdt->last_ping + WDT_DELAY)) | |
64 | usleep_range(30, 125); | |
65 | writel_relaxed(val, wdt->reg_base + field); | |
66 | wdt->last_ping = jiffies; | |
67 | } | |
68 | ||
69 | static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val) | |
70 | { | |
71 | if (time_before(jiffies, wdt->last_ping + WDT_DELAY)) | |
72 | udelay(123); | |
73 | writel_relaxed(val, wdt->reg_base + field); | |
74 | wdt->last_ping = jiffies; | |
75 | } | |
76534860 WY |
76 | |
77 | static int sama5d4_wdt_start(struct watchdog_device *wdd) | |
78 | { | |
79 | struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd); | |
76534860 | 80 | |
722ce635 AB |
81 | wdt->mr &= ~AT91_WDT_WDDIS; |
82 | wdt_write(wdt, AT91_WDT_MR, wdt->mr); | |
76534860 WY |
83 | |
84 | return 0; | |
85 | } | |
86 | ||
87 | static int sama5d4_wdt_stop(struct watchdog_device *wdd) | |
88 | { | |
89 | struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd); | |
76534860 | 90 | |
722ce635 AB |
91 | wdt->mr |= AT91_WDT_WDDIS; |
92 | wdt_write(wdt, AT91_WDT_MR, wdt->mr); | |
76534860 WY |
93 | |
94 | return 0; | |
95 | } | |
96 | ||
97 | static int sama5d4_wdt_ping(struct watchdog_device *wdd) | |
98 | { | |
99 | struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd); | |
100 | ||
101 | wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd, | |
107 | unsigned int timeout) | |
108 | { | |
109 | struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd); | |
110 | u32 value = WDT_SEC2TICKS(timeout); | |
76534860 | 111 | |
722ce635 | 112 | wdt->mr &= ~AT91_WDT_WDV; |
722ce635 | 113 | wdt->mr |= AT91_WDT_SET_WDV(value); |
015b5286 AB |
114 | |
115 | /* | |
116 | * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When | |
117 | * setting the WDDIS bit, and while it is set, the fields WDV and WDD | |
118 | * must not be modified. | |
119 | * If the watchdog is enabled, then the timeout can be updated. Else, | |
120 | * wait that the user enables it. | |
121 | */ | |
122 | if (wdt_enabled) | |
123 | wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS); | |
76534860 WY |
124 | |
125 | wdd->timeout = timeout; | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
130 | static const struct watchdog_info sama5d4_wdt_info = { | |
131 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, | |
132 | .identity = "Atmel SAMA5D4 Watchdog", | |
133 | }; | |
134 | ||
b893e344 | 135 | static const struct watchdog_ops sama5d4_wdt_ops = { |
76534860 WY |
136 | .owner = THIS_MODULE, |
137 | .start = sama5d4_wdt_start, | |
138 | .stop = sama5d4_wdt_stop, | |
139 | .ping = sama5d4_wdt_ping, | |
140 | .set_timeout = sama5d4_wdt_set_timeout, | |
141 | }; | |
142 | ||
143 | static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id) | |
144 | { | |
145 | struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id); | |
146 | ||
147 | if (wdt_read(wdt, AT91_WDT_SR)) { | |
148 | pr_crit("Atmel Watchdog Software Reset\n"); | |
149 | emergency_restart(); | |
150 | pr_crit("Reboot didn't succeed\n"); | |
151 | } | |
152 | ||
153 | return IRQ_HANDLED; | |
154 | } | |
155 | ||
156 | static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt) | |
157 | { | |
158 | const char *tmp; | |
159 | ||
722ce635 | 160 | wdt->mr = AT91_WDT_WDDIS; |
76534860 WY |
161 | |
162 | if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) && | |
163 | !strcmp(tmp, "software")) | |
722ce635 | 164 | wdt->mr |= AT91_WDT_WDFIEN; |
76534860 | 165 | else |
722ce635 | 166 | wdt->mr |= AT91_WDT_WDRSTEN; |
76534860 WY |
167 | |
168 | if (of_property_read_bool(np, "atmel,idle-halt")) | |
722ce635 | 169 | wdt->mr |= AT91_WDT_WDIDLEHLT; |
76534860 WY |
170 | |
171 | if (of_property_read_bool(np, "atmel,dbg-halt")) | |
722ce635 | 172 | wdt->mr |= AT91_WDT_WDDBGHLT; |
76534860 WY |
173 | |
174 | return 0; | |
175 | } | |
176 | ||
177 | static int sama5d4_wdt_init(struct sama5d4_wdt *wdt) | |
178 | { | |
76534860 | 179 | u32 reg; |
76534860 | 180 | /* |
015b5286 AB |
181 | * When booting and resuming, the bootloader may have changed the |
182 | * watchdog configuration. | |
183 | * If the watchdog is already running, we can safely update it. | |
184 | * Else, we have to disable it properly. | |
76534860 | 185 | */ |
015b5286 | 186 | if (wdt_enabled) { |
ddd6d240 | 187 | wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr); |
015b5286 AB |
188 | } else { |
189 | reg = wdt_read(wdt, AT91_WDT_MR); | |
190 | if (!(reg & AT91_WDT_WDDIS)) | |
ddd6d240 AB |
191 | wdt_write_nosleep(wdt, AT91_WDT_MR, |
192 | reg | AT91_WDT_WDDIS); | |
015b5286 | 193 | } |
76534860 WY |
194 | return 0; |
195 | } | |
196 | ||
197 | static int sama5d4_wdt_probe(struct platform_device *pdev) | |
198 | { | |
dcc3ce0b | 199 | struct device *dev = &pdev->dev; |
76534860 WY |
200 | struct watchdog_device *wdd; |
201 | struct sama5d4_wdt *wdt; | |
76534860 WY |
202 | void __iomem *regs; |
203 | u32 irq = 0; | |
015b5286 | 204 | u32 timeout; |
76534860 WY |
205 | int ret; |
206 | ||
dcc3ce0b | 207 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
76534860 WY |
208 | if (!wdt) |
209 | return -ENOMEM; | |
210 | ||
211 | wdd = &wdt->wdd; | |
976932e4 | 212 | wdd->timeout = WDT_DEFAULT_TIMEOUT; |
76534860 WY |
213 | wdd->info = &sama5d4_wdt_info; |
214 | wdd->ops = &sama5d4_wdt_ops; | |
215 | wdd->min_timeout = MIN_WDT_TIMEOUT; | |
216 | wdd->max_timeout = MAX_WDT_TIMEOUT; | |
ddd6d240 | 217 | wdt->last_ping = jiffies; |
76534860 WY |
218 | |
219 | watchdog_set_drvdata(wdd, wdt); | |
220 | ||
0f0a6a28 | 221 | regs = devm_platform_ioremap_resource(pdev, 0); |
76534860 WY |
222 | if (IS_ERR(regs)) |
223 | return PTR_ERR(regs); | |
224 | ||
225 | wdt->reg_base = regs; | |
226 | ||
dcc3ce0b | 227 | irq = irq_of_parse_and_map(dev->of_node, 0); |
39bd56df | 228 | if (!irq) |
dcc3ce0b | 229 | dev_warn(dev, "failed to get IRQ from DT\n"); |
76534860 | 230 | |
dcc3ce0b | 231 | ret = of_sama5d4_wdt_init(dev->of_node, wdt); |
39bd56df AB |
232 | if (ret) |
233 | return ret; | |
76534860 | 234 | |
722ce635 | 235 | if ((wdt->mr & AT91_WDT_WDFIEN) && irq) { |
dcc3ce0b | 236 | ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler, |
76534860 WY |
237 | IRQF_SHARED | IRQF_IRQPOLL | |
238 | IRQF_NO_SUSPEND, pdev->name, pdev); | |
239 | if (ret) { | |
dcc3ce0b | 240 | dev_err(dev, "cannot register interrupt handler\n"); |
76534860 WY |
241 | return ret; |
242 | } | |
243 | } | |
244 | ||
dcc3ce0b | 245 | watchdog_init_timeout(wdd, wdt_timeout, dev); |
76534860 | 246 | |
015b5286 AB |
247 | timeout = WDT_SEC2TICKS(wdd->timeout); |
248 | ||
86329448 | 249 | wdt->mr |= AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT)); |
015b5286 AB |
250 | wdt->mr |= AT91_WDT_SET_WDV(timeout); |
251 | ||
76534860 WY |
252 | ret = sama5d4_wdt_init(wdt); |
253 | if (ret) | |
254 | return ret; | |
255 | ||
256 | watchdog_set_nowayout(wdd, nowayout); | |
257 | ||
dcc3ce0b GR |
258 | watchdog_stop_on_unregister(wdd); |
259 | ret = devm_watchdog_register_device(dev, wdd); | |
24b8eb74 | 260 | if (ret) |
76534860 | 261 | return ret; |
76534860 WY |
262 | |
263 | platform_set_drvdata(pdev, wdt); | |
264 | ||
dcc3ce0b | 265 | dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n", |
976932e4 | 266 | wdd->timeout, nowayout); |
76534860 WY |
267 | |
268 | return 0; | |
269 | } | |
270 | ||
76534860 WY |
271 | static const struct of_device_id sama5d4_wdt_of_match[] = { |
272 | { .compatible = "atmel,sama5d4-wdt", }, | |
273 | { } | |
274 | }; | |
275 | MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match); | |
276 | ||
f2013532 | 277 | #ifdef CONFIG_PM_SLEEP |
8d209eb0 KS |
278 | static int sama5d4_wdt_suspend_late(struct device *dev) |
279 | { | |
280 | struct sama5d4_wdt *wdt = dev_get_drvdata(dev); | |
281 | ||
282 | if (watchdog_active(&wdt->wdd)) | |
283 | sama5d4_wdt_stop(&wdt->wdd); | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static int sama5d4_wdt_resume_early(struct device *dev) | |
f2013532 AB |
289 | { |
290 | struct sama5d4_wdt *wdt = dev_get_drvdata(dev); | |
291 | ||
5dca80f6 AB |
292 | /* |
293 | * FIXME: writing MR also pings the watchdog which may not be desired. | |
294 | * This should only be done when the registers are lost on suspend but | |
295 | * there is no way to get this information right now. | |
296 | */ | |
015b5286 | 297 | sama5d4_wdt_init(wdt); |
f2013532 | 298 | |
8d209eb0 KS |
299 | if (watchdog_active(&wdt->wdd)) |
300 | sama5d4_wdt_start(&wdt->wdd); | |
301 | ||
f2013532 AB |
302 | return 0; |
303 | } | |
304 | #endif | |
305 | ||
8d209eb0 KS |
306 | static const struct dev_pm_ops sama5d4_wdt_pm_ops = { |
307 | SET_LATE_SYSTEM_SLEEP_PM_OPS(sama5d4_wdt_suspend_late, | |
308 | sama5d4_wdt_resume_early) | |
309 | }; | |
f2013532 | 310 | |
76534860 WY |
311 | static struct platform_driver sama5d4_wdt_driver = { |
312 | .probe = sama5d4_wdt_probe, | |
76534860 WY |
313 | .driver = { |
314 | .name = "sama5d4_wdt", | |
f2013532 | 315 | .pm = &sama5d4_wdt_pm_ops, |
76534860 WY |
316 | .of_match_table = sama5d4_wdt_of_match, |
317 | } | |
318 | }; | |
319 | module_platform_driver(sama5d4_wdt_driver); | |
320 | ||
321 | MODULE_AUTHOR("Atmel Corporation"); | |
322 | MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver"); | |
323 | MODULE_LICENSE("GPL v2"); |