[linux-2.6-block.git] / drivers / watchdog / sama5d4_wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Atmel SAMA5D4 Watchdog Timer
 *
 * Copyright (C) 2015 Atmel Corporation
 */

#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/watchdog.h>

#include "at91sam9_wdt.h"

/* minimum and maximum watchdog timeout, in seconds */
#define MIN_WDT_TIMEOUT		1
#define MAX_WDT_TIMEOUT		16
#define WDT_DEFAULT_TIMEOUT	MAX_WDT_TIMEOUT

#define WDT_SEC2TICKS(s)	((s) ? (((s) << 8) - 1) : 0)

struct sama5d4_wdt {
	struct watchdog_device	wdd;
	void __iomem		*reg_base;
	u32			mr;
	unsigned long		last_ping;
};

static int wdt_timeout;
static bool nowayout = WATCHDOG_NOWAYOUT;

module_param(wdt_timeout, int, 0);
MODULE_PARM_DESC(wdt_timeout,
	"Watchdog timeout in seconds. (default = "
	__MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

#define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))

#define wdt_read(wdt, field) \
	readl_relaxed((wdt)->reg_base + (field))

/* 4 slow clock periods is 4/32768 = 122.07µs*/
#define WDT_DELAY	usecs_to_jiffies(123)

static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val)
{
	/*
	 * WDT_CR and WDT_MR must not be modified within three slow clock
	 * periods following a restart of the watchdog performed by a write
	 * access in WDT_CR.
	 */
	while (time_before(jiffies, wdt->last_ping + WDT_DELAY))
		usleep_range(30, 125);
	writel_relaxed(val, wdt->reg_base + field);
	wdt->last_ping = jiffies;
}

static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val)
{
	if (time_before(jiffies, wdt->last_ping + WDT_DELAY))
		udelay(123);
	writel_relaxed(val, wdt->reg_base + field);
	wdt->last_ping = jiffies;
}

static int sama5d4_wdt_start(struct watchdog_device *wdd)
{
	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);

	wdt->mr &= ~AT91_WDT_WDDIS;
	wdt_write(wdt, AT91_WDT_MR, wdt->mr);

	return 0;
}

static int sama5d4_wdt_stop(struct watchdog_device *wdd)
{
	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);

	wdt->mr |= AT91_WDT_WDDIS;
	wdt_write(wdt, AT91_WDT_MR, wdt->mr);

	return 0;
}

static int sama5d4_wdt_ping(struct watchdog_device *wdd)
{
	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);

	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);

	return 0;
}

static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd,
				 unsigned int timeout)
{
	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
	u32 value = WDT_SEC2TICKS(timeout);

	wdt->mr &= ~AT91_WDT_WDV;
	wdt->mr &= ~AT91_WDT_WDD;
	wdt->mr |= AT91_WDT_SET_WDV(value);
	wdt->mr |= AT91_WDT_SET_WDD(value);

	/*
	 * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When
	 * setting the WDDIS bit, and while it is set, the fields WDV and WDD
	 * must not be modified.
	 * If the watchdog is enabled, then the timeout can be updated. Else,
	 * wait that the user enables it.
	 */
	if (wdt_enabled)
		wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS);

	wdd->timeout = timeout;

	return 0;
}

static const struct watchdog_info sama5d4_wdt_info = {
	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
	.identity = "Atmel SAMA5D4 Watchdog",
};

static const struct watchdog_ops sama5d4_wdt_ops = {
	.owner = THIS_MODULE,
	.start = sama5d4_wdt_start,
	.stop = sama5d4_wdt_stop,
	.ping = sama5d4_wdt_ping,
	.set_timeout = sama5d4_wdt_set_timeout,
};

static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id)
{
	struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id);

	if (wdt_read(wdt, AT91_WDT_SR)) {
		pr_crit("Atmel Watchdog Software Reset\n");
		emergency_restart();
		pr_crit("Reboot didn't succeed\n");
	}

	return IRQ_HANDLED;
}

static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt)
{
	const char *tmp;

	wdt->mr = AT91_WDT_WDDIS;

	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
	    !strcmp(tmp, "software"))
		wdt->mr |= AT91_WDT_WDFIEN;
	else
		wdt->mr |= AT91_WDT_WDRSTEN;

	if (of_property_read_bool(np, "atmel,idle-halt"))
		wdt->mr |= AT91_WDT_WDIDLEHLT;

	if (of_property_read_bool(np, "atmel,dbg-halt"))
		wdt->mr |= AT91_WDT_WDDBGHLT;

	return 0;
}

static int sama5d4_wdt_init(struct sama5d4_wdt *wdt)
{
	u32 reg;
	/*
	 * When booting and resuming, the bootloader may have changed the
	 * watchdog configuration.
	 * If the watchdog is already running, we can safely update it.
	 * Else, we have to disable it properly.
	 */
	if (wdt_enabled) {
		wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr);
	} else {
		reg = wdt_read(wdt, AT91_WDT_MR);
		if (!(reg & AT91_WDT_WDDIS))
			wdt_write_nosleep(wdt, AT91_WDT_MR,
					  reg | AT91_WDT_WDDIS);
	}
	return 0;
}

static int sama5d4_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct sama5d4_wdt *wdt;
	void __iomem *regs;
	u32 irq = 0;
	u32 timeout;
	int ret;

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdd = &wdt->wdd;
	wdd->timeout = WDT_DEFAULT_TIMEOUT;
	wdd->info = &sama5d4_wdt_info;
	wdd->ops = &sama5d4_wdt_ops;
	wdd->min_timeout = MIN_WDT_TIMEOUT;
	wdd->max_timeout = MAX_WDT_TIMEOUT;
	wdt->last_ping = jiffies;

	watchdog_set_drvdata(wdd, wdt);

	regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	wdt->reg_base = regs;

	irq = irq_of_parse_and_map(dev->of_node, 0);
	if (!irq)
		dev_warn(dev, "failed to get IRQ from DT\n");

	ret = of_sama5d4_wdt_init(dev->of_node, wdt);
	if (ret)
		return ret;

	if ((wdt->mr & AT91_WDT_WDFIEN) && irq) {
		ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler,
				       IRQF_SHARED | IRQF_IRQPOLL |
				       IRQF_NO_SUSPEND, pdev->name, pdev);
		if (ret) {
			dev_err(dev, "cannot register interrupt handler\n");
			return ret;
		}
	}

	watchdog_init_timeout(wdd, wdt_timeout, dev);

	timeout = WDT_SEC2TICKS(wdd->timeout);

	wdt->mr |= AT91_WDT_SET_WDD(timeout);
	wdt->mr |= AT91_WDT_SET_WDV(timeout);

	ret = sama5d4_wdt_init(wdt);
	if (ret)
		return ret;

	watchdog_set_nowayout(wdd, nowayout);

	watchdog_stop_on_unregister(wdd);
	ret = devm_watchdog_register_device(dev, wdd);
	if (ret) {
		dev_err(dev, "failed to register watchdog device\n");
		return ret;
	}

	platform_set_drvdata(pdev, wdt);

	dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n",
		 wdd->timeout, nowayout);

	return 0;
}

static const struct of_device_id sama5d4_wdt_of_match[] = {
	{ .compatible = "atmel,sama5d4-wdt", },
	{ }
};
MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);

#ifdef CONFIG_PM_SLEEP
static int sama5d4_wdt_resume(struct device *dev)
{
	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);

	/*
	 * FIXME: writing MR also pings the watchdog which may not be desired.
	 * This should only be done when the registers are lost on suspend but
	 * there is no way to get this information right now.
	 */
	sama5d4_wdt_init(wdt);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(sama5d4_wdt_pm_ops, NULL,
			 sama5d4_wdt_resume);

static struct platform_driver sama5d4_wdt_driver = {
	.probe		= sama5d4_wdt_probe,
	.driver		= {
		.name	= "sama5d4_wdt",
		.pm	= &sama5d4_wdt_pm_ops,
		.of_match_table = sama5d4_wdt_of_match,
	}
};
module_platform_driver(sama5d4_wdt_driver);

MODULE_AUTHOR("Atmel Corporation");
MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f50a7f3d	1	// SPDX-License-Identifier: GPL-2.0-only
76534860 WY	2	/*
	3	* Driver for Atmel SAMA5D4 Watchdog Timer
	4	*
	5	* Copyright (C) 2015 Atmel Corporation
76534860 WY	6	*/
76534860 WY	7
ddd6d240	8	#include <linux/delay.h>
76534860 WY	9	#include <linux/interrupt.h>
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
	14	#include <linux/of_irq.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/reboot.h>
	17	#include <linux/watchdog.h>
	18
	19	#include "at91sam9_wdt.h"
	20
	21	/* minimum and maximum watchdog timeout, in seconds */
	22	#define MIN_WDT_TIMEOUT 1
	23	#define MAX_WDT_TIMEOUT 16
	24	#define WDT_DEFAULT_TIMEOUT MAX_WDT_TIMEOUT
	25
	26	#define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0)
	27
	28	struct sama5d4_wdt {
	29	struct watchdog_device wdd;
	30	void __iomem *reg_base;
722ce635	31	u32 mr;
ddd6d240	32	unsigned long last_ping;
76534860 WY	33	};
76534860 WY	34
976932e4	35	static int wdt_timeout;
76534860 WY	36	static bool nowayout = WATCHDOG_NOWAYOUT;
	37
	38	module_param(wdt_timeout, int, 0);
	39	MODULE_PARM_DESC(wdt_timeout,
	40	"Watchdog timeout in seconds. (default = "
	41	__MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
	42
	43	module_param(nowayout, bool, 0);
	44	MODULE_PARM_DESC(nowayout,
	45	"Watchdog cannot be stopped once started (default="
	46	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	47
015b5286 AB	48	#define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))
015b5286 AB	49
76534860 WY	50	#define wdt_read(wdt, field) \
	51	readl_relaxed((wdt)->reg_base + (field))
	52
ddd6d240 AB	53	/* 4 slow clock periods is 4/32768 = 122.07µs*/
	54	#define WDT_DELAY usecs_to_jiffies(123)
	55
	56	static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val)
	57	{
	58	/*
	59	* WDT_CR and WDT_MR must not be modified within three slow clock
	60	* periods following a restart of the watchdog performed by a write
	61	* access in WDT_CR.
	62	*/
	63	while (time_before(jiffies, wdt->last_ping + WDT_DELAY))
	64	usleep_range(30, 125);
	65	writel_relaxed(val, wdt->reg_base + field);
	66	wdt->last_ping = jiffies;
	67	}
	68
	69	static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val)
	70	{
	71	if (time_before(jiffies, wdt->last_ping + WDT_DELAY))
	72	udelay(123);
	73	writel_relaxed(val, wdt->reg_base + field);
	74	wdt->last_ping = jiffies;
	75	}
76534860 WY	76
	77	static int sama5d4_wdt_start(struct watchdog_device *wdd)
	78	{
	79	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
76534860	80
722ce635 AB	81	wdt->mr &= ~AT91_WDT_WDDIS;
722ce635 AB	82	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
76534860 WY	83
	84	return 0;
	85	}
	86
	87	static int sama5d4_wdt_stop(struct watchdog_device *wdd)
	88	{
	89	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
76534860	90
722ce635 AB	91	wdt->mr \|= AT91_WDT_WDDIS;
722ce635 AB	92	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
76534860 WY	93
	94	return 0;
	95	}
	96
	97	static int sama5d4_wdt_ping(struct watchdog_device *wdd)
	98	{
	99	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
	100
	101	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY \| AT91_WDT_WDRSTT);
	102
	103	return 0;
	104	}
	105
	106	static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd,
	107	unsigned int timeout)
	108	{
	109	struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
	110	u32 value = WDT_SEC2TICKS(timeout);
76534860	111
722ce635 AB	112	wdt->mr &= ~AT91_WDT_WDV;
	113	wdt->mr &= ~AT91_WDT_WDD;
	114	wdt->mr \|= AT91_WDT_SET_WDV(value);
	115	wdt->mr \|= AT91_WDT_SET_WDD(value);
015b5286 AB	116
	117	/*
	118	* WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When
	119	* setting the WDDIS bit, and while it is set, the fields WDV and WDD
	120	* must not be modified.
	121	* If the watchdog is enabled, then the timeout can be updated. Else,
	122	* wait that the user enables it.
	123	*/
	124	if (wdt_enabled)
	125	wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS);
76534860 WY	126
	127	wdd->timeout = timeout;
	128
	129	return 0;
	130	}
	131
	132	static const struct watchdog_info sama5d4_wdt_info = {
	133	.options = WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING,
	134	.identity = "Atmel SAMA5D4 Watchdog",
	135	};
	136
b893e344	137	static const struct watchdog_ops sama5d4_wdt_ops = {
76534860 WY	138	.owner = THIS_MODULE,
	139	.start = sama5d4_wdt_start,
	140	.stop = sama5d4_wdt_stop,
	141	.ping = sama5d4_wdt_ping,
	142	.set_timeout = sama5d4_wdt_set_timeout,
	143	};
	144
	145	static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id)
	146	{
	147	struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id);
	148
	149	if (wdt_read(wdt, AT91_WDT_SR)) {
	150	pr_crit("Atmel Watchdog Software Reset\n");
	151	emergency_restart();
	152	pr_crit("Reboot didn't succeed\n");
	153	}
	154
	155	return IRQ_HANDLED;
	156	}
	157
	158	static int of_sama5d4_wdt_init(struct device_node np, struct sama5d4_wdt wdt)
	159	{
	160	const char *tmp;
	161
722ce635	162	wdt->mr = AT91_WDT_WDDIS;
76534860 WY	163
	164	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
	165	!strcmp(tmp, "software"))
722ce635	166	wdt->mr \|= AT91_WDT_WDFIEN;
76534860	167	else
722ce635	168	wdt->mr \|= AT91_WDT_WDRSTEN;
76534860 WY	169
76534860 WY	170	if (of_property_read_bool(np, "atmel,idle-halt"))
722ce635	171	wdt->mr \|= AT91_WDT_WDIDLEHLT;
76534860 WY	172
76534860 WY	173	if (of_property_read_bool(np, "atmel,dbg-halt"))
722ce635	174	wdt->mr \|= AT91_WDT_WDDBGHLT;
76534860 WY	175
	176	return 0;
	177	}
	178
	179	static int sama5d4_wdt_init(struct sama5d4_wdt *wdt)
	180	{
76534860	181	u32 reg;
76534860	182	/*
015b5286 AB	183	* When booting and resuming, the bootloader may have changed the
	184	* watchdog configuration.
	185	* If the watchdog is already running, we can safely update it.
	186	* Else, we have to disable it properly.
76534860	187	*/
015b5286	188	if (wdt_enabled) {
ddd6d240	189	wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr);
015b5286 AB	190	} else {
	191	reg = wdt_read(wdt, AT91_WDT_MR);
	192	if (!(reg & AT91_WDT_WDDIS))
ddd6d240 AB	193	wdt_write_nosleep(wdt, AT91_WDT_MR,
ddd6d240 AB	194	reg \| AT91_WDT_WDDIS);
015b5286	195	}
76534860 WY	196	return 0;
	197	}
	198
	199	static int sama5d4_wdt_probe(struct platform_device *pdev)
	200	{
dcc3ce0b	201	struct device *dev = &pdev->dev;
76534860 WY	202	struct watchdog_device *wdd;
76534860 WY	203	struct sama5d4_wdt *wdt;
76534860 WY	204	void __iomem *regs;
76534860 WY	205	u32 irq = 0;
015b5286	206	u32 timeout;
76534860 WY	207	int ret;
76534860 WY	208
dcc3ce0b	209	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
76534860 WY	210	if (!wdt)
	211	return -ENOMEM;
	212
	213	wdd = &wdt->wdd;
976932e4	214	wdd->timeout = WDT_DEFAULT_TIMEOUT;
76534860 WY	215	wdd->info = &sama5d4_wdt_info;
	216	wdd->ops = &sama5d4_wdt_ops;
	217	wdd->min_timeout = MIN_WDT_TIMEOUT;
	218	wdd->max_timeout = MAX_WDT_TIMEOUT;
ddd6d240	219	wdt->last_ping = jiffies;
76534860 WY	220
	221	watchdog_set_drvdata(wdd, wdt);
	222
0f0a6a28	223	regs = devm_platform_ioremap_resource(pdev, 0);
76534860 WY	224	if (IS_ERR(regs))
	225	return PTR_ERR(regs);
	226
	227	wdt->reg_base = regs;
	228
dcc3ce0b	229	irq = irq_of_parse_and_map(dev->of_node, 0);
39bd56df	230	if (!irq)
dcc3ce0b	231	dev_warn(dev, "failed to get IRQ from DT\n");
76534860	232
dcc3ce0b	233	ret = of_sama5d4_wdt_init(dev->of_node, wdt);
39bd56df AB	234	if (ret)
39bd56df AB	235	return ret;
76534860	236
722ce635	237	if ((wdt->mr & AT91_WDT_WDFIEN) && irq) {
dcc3ce0b	238	ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler,
76534860 WY	239	IRQF_SHARED \| IRQF_IRQPOLL \|
	240	IRQF_NO_SUSPEND, pdev->name, pdev);
	241	if (ret) {
dcc3ce0b	242	dev_err(dev, "cannot register interrupt handler\n");
76534860 WY	243	return ret;
	244	}
	245	}
	246
dcc3ce0b	247	watchdog_init_timeout(wdd, wdt_timeout, dev);
76534860	248
015b5286 AB	249	timeout = WDT_SEC2TICKS(wdd->timeout);
	250
	251	wdt->mr \|= AT91_WDT_SET_WDD(timeout);
	252	wdt->mr \|= AT91_WDT_SET_WDV(timeout);
	253
76534860 WY	254	ret = sama5d4_wdt_init(wdt);
	255	if (ret)
	256	return ret;
	257
	258	watchdog_set_nowayout(wdd, nowayout);
	259
dcc3ce0b GR	260	watchdog_stop_on_unregister(wdd);
dcc3ce0b GR	261	ret = devm_watchdog_register_device(dev, wdd);
76534860	262	if (ret) {
dcc3ce0b	263	dev_err(dev, "failed to register watchdog device\n");
76534860 WY	264	return ret;
	265	}
	266
	267	platform_set_drvdata(pdev, wdt);
	268
dcc3ce0b	269	dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n",
976932e4	270	wdd->timeout, nowayout);
76534860 WY	271
	272	return 0;
	273	}
	274
76534860 WY	275	static const struct of_device_id sama5d4_wdt_of_match[] = {
	276	{ .compatible = "atmel,sama5d4-wdt", },
	277	{ }
	278	};
	279	MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);
	280
f2013532 AB	281	#ifdef CONFIG_PM_SLEEP
	282	static int sama5d4_wdt_resume(struct device *dev)
	283	{
	284	struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
	285
5dca80f6 AB	286	/*
	287	* FIXME: writing MR also pings the watchdog which may not be desired.
	288	* This should only be done when the registers are lost on suspend but
	289	* there is no way to get this information right now.
	290	*/
015b5286	291	sama5d4_wdt_init(wdt);
f2013532 AB	292
	293	return 0;
	294	}
	295	#endif
	296
	297	static SIMPLE_DEV_PM_OPS(sama5d4_wdt_pm_ops, NULL,
	298	sama5d4_wdt_resume);
	299
76534860 WY	300	static struct platform_driver sama5d4_wdt_driver = {
76534860 WY	301	.probe = sama5d4_wdt_probe,
76534860 WY	302	.driver = {
76534860 WY	303	.name = "sama5d4_wdt",
f2013532	304	.pm = &sama5d4_wdt_pm_ops,
76534860 WY	305	.of_match_table = sama5d4_wdt_of_match,
	306	}
	307	};
	308	module_platform_driver(sama5d4_wdt_driver);
	309
	310	MODULE_AUTHOR("Atmel Corporation");
	311	MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver");
	312	MODULE_LICENSE("GPL v2");