Commit | Line | Data |
---|---|---|
f50a7f3d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
76534860 WY |
2 | /* |
3 | * Driver for Atmel SAMA5D4 Watchdog Timer | |
4 | * | |
bb44aa09 | 5 | * Copyright (C) 2015-2019 Microchip Technology Inc. and its subsidiaries |
76534860 WY |
6 | */ |
7 | ||
ddd6d240 | 8 | #include <linux/delay.h> |
76534860 WY |
9 | #include <linux/interrupt.h> |
10 | #include <linux/io.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
bb44aa09 | 14 | #include <linux/of_device.h> |
76534860 WY |
15 | #include <linux/of_irq.h> |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/reboot.h> | |
18 | #include <linux/watchdog.h> | |
19 | ||
20 | #include "at91sam9_wdt.h" | |
21 | ||
22 | /* minimum and maximum watchdog timeout, in seconds */ | |
23 | #define MIN_WDT_TIMEOUT 1 | |
24 | #define MAX_WDT_TIMEOUT 16 | |
25 | #define WDT_DEFAULT_TIMEOUT MAX_WDT_TIMEOUT | |
26 | ||
27 | #define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0) | |
28 | ||
29 | struct sama5d4_wdt { | |
30 | struct watchdog_device wdd; | |
31 | void __iomem *reg_base; | |
722ce635 | 32 | u32 mr; |
bb44aa09 | 33 | u32 ir; |
ddd6d240 | 34 | unsigned long last_ping; |
bb44aa09 EH |
35 | bool need_irq; |
36 | bool sam9x60_support; | |
76534860 WY |
37 | }; |
38 | ||
976932e4 | 39 | static int wdt_timeout; |
76534860 WY |
40 | static bool nowayout = WATCHDOG_NOWAYOUT; |
41 | ||
42 | module_param(wdt_timeout, int, 0); | |
43 | MODULE_PARM_DESC(wdt_timeout, | |
44 | "Watchdog timeout in seconds. (default = " | |
45 | __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")"); | |
46 | ||
47 | module_param(nowayout, bool, 0); | |
48 | MODULE_PARM_DESC(nowayout, | |
49 | "Watchdog cannot be stopped once started (default=" | |
50 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
51 | ||
015b5286 AB |
52 | #define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS)) |
53 | ||
76534860 WY |
54 | #define wdt_read(wdt, field) \ |
55 | readl_relaxed((wdt)->reg_base + (field)) | |
56 | ||
ddd6d240 AB |
57 | /* 4 slow clock periods is 4/32768 = 122.07µs*/ |
58 | #define WDT_DELAY usecs_to_jiffies(123) | |
59 | ||
60 | static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) | |
61 | { | |
62 | /* | |
63 | * WDT_CR and WDT_MR must not be modified within three slow clock | |
64 | * periods following a restart of the watchdog performed by a write | |
65 | * access in WDT_CR. | |
66 | */ | |
67 | while (time_before(jiffies, wdt->last_ping + WDT_DELAY)) | |
68 | usleep_range(30, 125); | |
69 | writel_relaxed(val, wdt->reg_base + field); | |
70 | wdt->last_ping = jiffies; | |
71 | } | |
72 | ||
73 | static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val) | |
74 | { | |
75 | if (time_before(jiffies, wdt->last_ping + WDT_DELAY)) | |
76 | udelay(123); | |
77 | writel_relaxed(val, wdt->reg_base + field); | |
78 | wdt->last_ping = jiffies; | |
79 | } | |
76534860 WY |
80 | |
81 | static int sama5d4_wdt_start(struct watchdog_device *wdd) | |
82 | { | |
83 | struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd); | |
76534860 | 84 | |
bb44aa09 EH |
85 | if (wdt->sam9x60_support) { |
86 | writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER); | |
87 | wdt->mr &= ~AT91_SAM9X60_WDDIS; | |
88 | } else { | |
89 | wdt->mr &= ~AT91_WDT_WDDIS; | |
90 | } | |
722ce635 | 91 | wdt_write(wdt, AT91_WDT_MR, wdt->mr); |
76534860 WY |
92 | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int sama5d4_wdt_stop(struct watchdog_device *wdd) | |
97 | { | |
98 | struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd); | |
76534860 | 99 | |
bb44aa09 EH |
100 | if (wdt->sam9x60_support) { |
101 | writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR); | |
102 | wdt->mr |= AT91_SAM9X60_WDDIS; | |
103 | } else { | |
104 | wdt->mr |= AT91_WDT_WDDIS; | |
105 | } | |
722ce635 | 106 | wdt_write(wdt, AT91_WDT_MR, wdt->mr); |
76534860 WY |
107 | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static int sama5d4_wdt_ping(struct watchdog_device *wdd) | |
112 | { | |
113 | struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd); | |
114 | ||
115 | wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
120 | static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd, | |
121 | unsigned int timeout) | |
122 | { | |
123 | struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd); | |
124 | u32 value = WDT_SEC2TICKS(timeout); | |
76534860 | 125 | |
bb44aa09 EH |
126 | if (wdt->sam9x60_support) { |
127 | wdt_write(wdt, AT91_SAM9X60_WLR, | |
128 | AT91_SAM9X60_SET_COUNTER(value)); | |
129 | ||
130 | wdd->timeout = timeout; | |
131 | return 0; | |
132 | } | |
133 | ||
722ce635 | 134 | wdt->mr &= ~AT91_WDT_WDV; |
722ce635 | 135 | wdt->mr |= AT91_WDT_SET_WDV(value); |
015b5286 AB |
136 | |
137 | /* | |
138 | * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When | |
139 | * setting the WDDIS bit, and while it is set, the fields WDV and WDD | |
140 | * must not be modified. | |
141 | * If the watchdog is enabled, then the timeout can be updated. Else, | |
142 | * wait that the user enables it. | |
143 | */ | |
144 | if (wdt_enabled) | |
145 | wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS); | |
76534860 WY |
146 | |
147 | wdd->timeout = timeout; | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | static const struct watchdog_info sama5d4_wdt_info = { | |
153 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, | |
154 | .identity = "Atmel SAMA5D4 Watchdog", | |
155 | }; | |
156 | ||
b893e344 | 157 | static const struct watchdog_ops sama5d4_wdt_ops = { |
76534860 WY |
158 | .owner = THIS_MODULE, |
159 | .start = sama5d4_wdt_start, | |
160 | .stop = sama5d4_wdt_stop, | |
161 | .ping = sama5d4_wdt_ping, | |
162 | .set_timeout = sama5d4_wdt_set_timeout, | |
163 | }; | |
164 | ||
165 | static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id) | |
166 | { | |
167 | struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id); | |
bb44aa09 | 168 | u32 reg; |
76534860 | 169 | |
bb44aa09 EH |
170 | if (wdt->sam9x60_support) |
171 | reg = wdt_read(wdt, AT91_SAM9X60_ISR); | |
172 | else | |
173 | reg = wdt_read(wdt, AT91_WDT_SR); | |
174 | ||
175 | if (reg) { | |
76534860 WY |
176 | pr_crit("Atmel Watchdog Software Reset\n"); |
177 | emergency_restart(); | |
178 | pr_crit("Reboot didn't succeed\n"); | |
179 | } | |
180 | ||
181 | return IRQ_HANDLED; | |
182 | } | |
183 | ||
184 | static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt) | |
185 | { | |
186 | const char *tmp; | |
187 | ||
bb44aa09 EH |
188 | if (wdt->sam9x60_support) |
189 | wdt->mr = AT91_SAM9X60_WDDIS; | |
190 | else | |
191 | wdt->mr = AT91_WDT_WDDIS; | |
76534860 WY |
192 | |
193 | if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) && | |
194 | !strcmp(tmp, "software")) | |
bb44aa09 | 195 | wdt->need_irq = true; |
76534860 WY |
196 | |
197 | if (of_property_read_bool(np, "atmel,idle-halt")) | |
722ce635 | 198 | wdt->mr |= AT91_WDT_WDIDLEHLT; |
76534860 WY |
199 | |
200 | if (of_property_read_bool(np, "atmel,dbg-halt")) | |
722ce635 | 201 | wdt->mr |= AT91_WDT_WDDBGHLT; |
76534860 WY |
202 | |
203 | return 0; | |
204 | } | |
205 | ||
206 | static int sama5d4_wdt_init(struct sama5d4_wdt *wdt) | |
207 | { | |
bb44aa09 EH |
208 | u32 reg, val; |
209 | ||
210 | val = WDT_SEC2TICKS(WDT_DEFAULT_TIMEOUT); | |
76534860 | 211 | /* |
015b5286 AB |
212 | * When booting and resuming, the bootloader may have changed the |
213 | * watchdog configuration. | |
214 | * If the watchdog is already running, we can safely update it. | |
215 | * Else, we have to disable it properly. | |
76534860 | 216 | */ |
bb44aa09 | 217 | if (!wdt_enabled) { |
015b5286 | 218 | reg = wdt_read(wdt, AT91_WDT_MR); |
bb44aa09 EH |
219 | if (wdt->sam9x60_support && (!(reg & AT91_SAM9X60_WDDIS))) |
220 | wdt_write_nosleep(wdt, AT91_WDT_MR, | |
221 | reg | AT91_SAM9X60_WDDIS); | |
222 | else if (!wdt->sam9x60_support && | |
223 | (!(reg & AT91_WDT_WDDIS))) | |
ddd6d240 AB |
224 | wdt_write_nosleep(wdt, AT91_WDT_MR, |
225 | reg | AT91_WDT_WDDIS); | |
015b5286 | 226 | } |
bb44aa09 EH |
227 | |
228 | if (wdt->sam9x60_support) { | |
229 | if (wdt->need_irq) | |
230 | wdt->ir = AT91_SAM9X60_PERINT; | |
231 | else | |
232 | wdt->mr |= AT91_SAM9X60_PERIODRST; | |
233 | ||
234 | wdt_write(wdt, AT91_SAM9X60_IER, wdt->ir); | |
235 | wdt_write(wdt, AT91_SAM9X60_WLR, AT91_SAM9X60_SET_COUNTER(val)); | |
236 | } else { | |
237 | wdt->mr |= AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT)); | |
238 | wdt->mr |= AT91_WDT_SET_WDV(val); | |
239 | ||
240 | if (wdt->need_irq) | |
241 | wdt->mr |= AT91_WDT_WDFIEN; | |
242 | else | |
243 | wdt->mr |= AT91_WDT_WDRSTEN; | |
244 | } | |
245 | ||
246 | wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr); | |
247 | ||
76534860 WY |
248 | return 0; |
249 | } | |
250 | ||
251 | static int sama5d4_wdt_probe(struct platform_device *pdev) | |
252 | { | |
dcc3ce0b | 253 | struct device *dev = &pdev->dev; |
76534860 WY |
254 | struct watchdog_device *wdd; |
255 | struct sama5d4_wdt *wdt; | |
76534860 WY |
256 | void __iomem *regs; |
257 | u32 irq = 0; | |
258 | int ret; | |
259 | ||
dcc3ce0b | 260 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
76534860 WY |
261 | if (!wdt) |
262 | return -ENOMEM; | |
263 | ||
264 | wdd = &wdt->wdd; | |
976932e4 | 265 | wdd->timeout = WDT_DEFAULT_TIMEOUT; |
76534860 WY |
266 | wdd->info = &sama5d4_wdt_info; |
267 | wdd->ops = &sama5d4_wdt_ops; | |
268 | wdd->min_timeout = MIN_WDT_TIMEOUT; | |
269 | wdd->max_timeout = MAX_WDT_TIMEOUT; | |
ddd6d240 | 270 | wdt->last_ping = jiffies; |
5ae233fb EH |
271 | |
272 | if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") || | |
273 | of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt")) | |
274 | wdt->sam9x60_support = true; | |
76534860 WY |
275 | |
276 | watchdog_set_drvdata(wdd, wdt); | |
277 | ||
0f0a6a28 | 278 | regs = devm_platform_ioremap_resource(pdev, 0); |
76534860 WY |
279 | if (IS_ERR(regs)) |
280 | return PTR_ERR(regs); | |
281 | ||
282 | wdt->reg_base = regs; | |
283 | ||
dcc3ce0b | 284 | ret = of_sama5d4_wdt_init(dev->of_node, wdt); |
39bd56df AB |
285 | if (ret) |
286 | return ret; | |
76534860 | 287 | |
bb44aa09 EH |
288 | if (wdt->need_irq) { |
289 | irq = irq_of_parse_and_map(dev->of_node, 0); | |
290 | if (!irq) { | |
291 | dev_warn(dev, "failed to get IRQ from DT\n"); | |
292 | wdt->need_irq = false; | |
293 | } | |
294 | } | |
295 | ||
296 | if (wdt->need_irq) { | |
dcc3ce0b | 297 | ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler, |
76534860 WY |
298 | IRQF_SHARED | IRQF_IRQPOLL | |
299 | IRQF_NO_SUSPEND, pdev->name, pdev); | |
300 | if (ret) { | |
dcc3ce0b | 301 | dev_err(dev, "cannot register interrupt handler\n"); |
76534860 WY |
302 | return ret; |
303 | } | |
304 | } | |
305 | ||
dcc3ce0b | 306 | watchdog_init_timeout(wdd, wdt_timeout, dev); |
76534860 WY |
307 | |
308 | ret = sama5d4_wdt_init(wdt); | |
309 | if (ret) | |
310 | return ret; | |
311 | ||
312 | watchdog_set_nowayout(wdd, nowayout); | |
313 | ||
dcc3ce0b GR |
314 | watchdog_stop_on_unregister(wdd); |
315 | ret = devm_watchdog_register_device(dev, wdd); | |
24b8eb74 | 316 | if (ret) |
76534860 | 317 | return ret; |
76534860 WY |
318 | |
319 | platform_set_drvdata(pdev, wdt); | |
320 | ||
dcc3ce0b | 321 | dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n", |
976932e4 | 322 | wdd->timeout, nowayout); |
76534860 WY |
323 | |
324 | return 0; | |
325 | } | |
326 | ||
76534860 | 327 | static const struct of_device_id sama5d4_wdt_of_match[] = { |
bb44aa09 EH |
328 | { |
329 | .compatible = "atmel,sama5d4-wdt", | |
330 | }, | |
331 | { | |
332 | .compatible = "microchip,sam9x60-wdt", | |
333 | }, | |
5ae233fb EH |
334 | { |
335 | .compatible = "microchip,sama7g5-wdt", | |
336 | }, | |
337 | ||
76534860 WY |
338 | { } |
339 | }; | |
340 | MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match); | |
341 | ||
8d209eb0 KS |
342 | static int sama5d4_wdt_suspend_late(struct device *dev) |
343 | { | |
344 | struct sama5d4_wdt *wdt = dev_get_drvdata(dev); | |
345 | ||
346 | if (watchdog_active(&wdt->wdd)) | |
347 | sama5d4_wdt_stop(&wdt->wdd); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | static int sama5d4_wdt_resume_early(struct device *dev) | |
f2013532 AB |
353 | { |
354 | struct sama5d4_wdt *wdt = dev_get_drvdata(dev); | |
355 | ||
5dca80f6 AB |
356 | /* |
357 | * FIXME: writing MR also pings the watchdog which may not be desired. | |
358 | * This should only be done when the registers are lost on suspend but | |
359 | * there is no way to get this information right now. | |
360 | */ | |
015b5286 | 361 | sama5d4_wdt_init(wdt); |
f2013532 | 362 | |
8d209eb0 KS |
363 | if (watchdog_active(&wdt->wdd)) |
364 | sama5d4_wdt_start(&wdt->wdd); | |
365 | ||
f2013532 AB |
366 | return 0; |
367 | } | |
f2013532 | 368 | |
8d209eb0 | 369 | static const struct dev_pm_ops sama5d4_wdt_pm_ops = { |
5c040ea2 PC |
370 | LATE_SYSTEM_SLEEP_PM_OPS(sama5d4_wdt_suspend_late, |
371 | sama5d4_wdt_resume_early) | |
8d209eb0 | 372 | }; |
f2013532 | 373 | |
76534860 WY |
374 | static struct platform_driver sama5d4_wdt_driver = { |
375 | .probe = sama5d4_wdt_probe, | |
76534860 WY |
376 | .driver = { |
377 | .name = "sama5d4_wdt", | |
5c040ea2 | 378 | .pm = pm_sleep_ptr(&sama5d4_wdt_pm_ops), |
76534860 WY |
379 | .of_match_table = sama5d4_wdt_of_match, |
380 | } | |
381 | }; | |
382 | module_platform_driver(sama5d4_wdt_driver); | |
383 | ||
384 | MODULE_AUTHOR("Atmel Corporation"); | |
385 | MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver"); | |
386 | MODULE_LICENSE("GPL v2"); |