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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/moduleparam.h> | |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/timer.h> | |
1da177e4 | 30 | #include <linux/watchdog.h> |
d052d1be | 31 | #include <linux/platform_device.h> |
1da177e4 | 32 | #include <linux/interrupt.h> |
f8ce2547 | 33 | #include <linux/clk.h> |
41dc8b72 AC |
34 | #include <linux/uaccess.h> |
35 | #include <linux/io.h> | |
e02f838e | 36 | #include <linux/cpufreq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
25dc46e3 | 38 | #include <linux/err.h> |
3016a552 | 39 | #include <linux/of.h> |
4f1f653a LKA |
40 | #include <linux/mfd/syscon.h> |
41 | #include <linux/regmap.h> | |
f286e133 | 42 | #include <linux/delay.h> |
1da177e4 | 43 | |
a8f5401a TF |
44 | #define S3C2410_WTCON 0x00 |
45 | #define S3C2410_WTDAT 0x04 | |
46 | #define S3C2410_WTCNT 0x08 | |
0b445549 | 47 | #define S3C2410_WTCLRINT 0x0c |
1da177e4 | 48 | |
882dec1f JMC |
49 | #define S3C2410_WTCNT_MAXCNT 0xffff |
50 | ||
a8f5401a TF |
51 | #define S3C2410_WTCON_RSTEN (1 << 0) |
52 | #define S3C2410_WTCON_INTEN (1 << 2) | |
53 | #define S3C2410_WTCON_ENABLE (1 << 5) | |
1da177e4 | 54 | |
a8f5401a TF |
55 | #define S3C2410_WTCON_DIV16 (0 << 3) |
56 | #define S3C2410_WTCON_DIV32 (1 << 3) | |
57 | #define S3C2410_WTCON_DIV64 (2 << 3) | |
58 | #define S3C2410_WTCON_DIV128 (3 << 3) | |
59 | ||
882dec1f JMC |
60 | #define S3C2410_WTCON_MAXDIV 0x80 |
61 | ||
a8f5401a TF |
62 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) |
63 | #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) | |
882dec1f | 64 | #define S3C2410_WTCON_PRESCALE_MAX 0xff |
1da177e4 | 65 | |
4f21195d KK |
66 | #define S3C2410_WATCHDOG_ATBOOT (0) |
67 | #define S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
1da177e4 | 68 | |
cffc9a60 | 69 | #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
4f1f653a LKA |
70 | #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
71 | #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c | |
72 | #define QUIRK_HAS_PMU_CONFIG (1 << 0) | |
cffc9a60 | 73 | #define QUIRK_HAS_RST_STAT (1 << 1) |
0b445549 | 74 | #define QUIRK_HAS_WTCLRINT_REG (1 << 2) |
cffc9a60 DA |
75 | |
76 | /* These quirks require that we have a PMU register map */ | |
77 | #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ | |
78 | QUIRK_HAS_RST_STAT) | |
4f1f653a | 79 | |
86a1e189 | 80 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 81 | static int tmr_margin; |
4f21195d | 82 | static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 | 83 | static int soft_noboot; |
1da177e4 LT |
84 | |
85 | module_param(tmr_margin, int, 0); | |
86 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 87 | module_param(nowayout, bool, 0); |
1da177e4 | 88 | module_param(soft_noboot, int, 0); |
1da177e4 | 89 | |
76550d32 | 90 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
4f21195d | 91 | __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
41dc8b72 AC |
92 | MODULE_PARM_DESC(tmr_atboot, |
93 | "Watchdog is started at boot time if set to 1, default=" | |
4f21195d | 94 | __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT)); |
41dc8b72 AC |
95 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
96 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e | 97 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
76550d32 | 98 | "0 to reboot (default 0)"); |
1da177e4 | 99 | |
4f1f653a LKA |
100 | /** |
101 | * struct s3c2410_wdt_variant - Per-variant config data | |
102 | * | |
103 | * @disable_reg: Offset in pmureg for the register that disables the watchdog | |
104 | * timer reset functionality. | |
105 | * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog | |
106 | * timer reset functionality. | |
107 | * @mask_bit: Bit number for the watchdog timer in the disable register and the | |
108 | * mask reset register. | |
cffc9a60 DA |
109 | * @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
110 | * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog | |
111 | * reset. | |
4f1f653a LKA |
112 | * @quirks: A bitfield of quirks. |
113 | */ | |
114 | ||
115 | struct s3c2410_wdt_variant { | |
116 | int disable_reg; | |
117 | int mask_reset_reg; | |
118 | int mask_bit; | |
cffc9a60 DA |
119 | int rst_stat_reg; |
120 | int rst_stat_bit; | |
4f1f653a LKA |
121 | u32 quirks; |
122 | }; | |
123 | ||
af4ea631 LKA |
124 | struct s3c2410_wdt { |
125 | struct device *dev; | |
126 | struct clk *clock; | |
127 | void __iomem *reg_base; | |
128 | unsigned int count; | |
129 | spinlock_t lock; | |
130 | unsigned long wtcon_save; | |
131 | unsigned long wtdat_save; | |
132 | struct watchdog_device wdt_device; | |
133 | struct notifier_block freq_transition; | |
58415efe | 134 | const struct s3c2410_wdt_variant *drv_data; |
4f1f653a LKA |
135 | struct regmap *pmureg; |
136 | }; | |
137 | ||
138 | static const struct s3c2410_wdt_variant drv_data_s3c2410 = { | |
139 | .quirks = 0 | |
140 | }; | |
141 | ||
142 | #ifdef CONFIG_OF | |
0b445549 KK |
143 | static const struct s3c2410_wdt_variant drv_data_s3c6410 = { |
144 | .quirks = QUIRK_HAS_WTCLRINT_REG, | |
145 | }; | |
146 | ||
4f1f653a LKA |
147 | static const struct s3c2410_wdt_variant drv_data_exynos5250 = { |
148 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
149 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
150 | .mask_bit = 20, | |
cffc9a60 DA |
151 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
152 | .rst_stat_bit = 20, | |
0b445549 KK |
153 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
154 | | QUIRK_HAS_WTCLRINT_REG, | |
4f1f653a LKA |
155 | }; |
156 | ||
157 | static const struct s3c2410_wdt_variant drv_data_exynos5420 = { | |
158 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
159 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
160 | .mask_bit = 0, | |
cffc9a60 DA |
161 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
162 | .rst_stat_bit = 9, | |
0b445549 KK |
163 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
164 | | QUIRK_HAS_WTCLRINT_REG, | |
4f1f653a LKA |
165 | }; |
166 | ||
2b9366b6 NKC |
167 | static const struct s3c2410_wdt_variant drv_data_exynos7 = { |
168 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
169 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
5476b2b7 | 170 | .mask_bit = 23, |
2b9366b6 NKC |
171 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
172 | .rst_stat_bit = 23, /* A57 WDTRESET */ | |
0b445549 KK |
173 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
174 | | QUIRK_HAS_WTCLRINT_REG, | |
2b9366b6 NKC |
175 | }; |
176 | ||
4f1f653a LKA |
177 | static const struct of_device_id s3c2410_wdt_match[] = { |
178 | { .compatible = "samsung,s3c2410-wdt", | |
179 | .data = &drv_data_s3c2410 }, | |
0b445549 KK |
180 | { .compatible = "samsung,s3c6410-wdt", |
181 | .data = &drv_data_s3c6410 }, | |
4f1f653a LKA |
182 | { .compatible = "samsung,exynos5250-wdt", |
183 | .data = &drv_data_exynos5250 }, | |
184 | { .compatible = "samsung,exynos5420-wdt", | |
185 | .data = &drv_data_exynos5420 }, | |
2b9366b6 NKC |
186 | { .compatible = "samsung,exynos7-wdt", |
187 | .data = &drv_data_exynos7 }, | |
4f1f653a | 188 | {}, |
af4ea631 | 189 | }; |
4f1f653a LKA |
190 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
191 | #endif | |
192 | ||
193 | static const struct platform_device_id s3c2410_wdt_ids[] = { | |
194 | { | |
195 | .name = "s3c2410-wdt", | |
196 | .driver_data = (unsigned long)&drv_data_s3c2410, | |
197 | }, | |
198 | {} | |
199 | }; | |
200 | MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); | |
1da177e4 | 201 | |
1da177e4 LT |
202 | /* functions */ |
203 | ||
882dec1f JMC |
204 | static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock) |
205 | { | |
206 | unsigned long freq = clk_get_rate(clock); | |
207 | ||
208 | return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) | |
209 | / S3C2410_WTCON_MAXDIV); | |
210 | } | |
211 | ||
af4ea631 LKA |
212 | static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
213 | { | |
214 | return container_of(nb, struct s3c2410_wdt, freq_transition); | |
215 | } | |
216 | ||
4f1f653a LKA |
217 | static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) |
218 | { | |
219 | int ret; | |
220 | u32 mask_val = 1 << wdt->drv_data->mask_bit; | |
221 | u32 val = 0; | |
222 | ||
223 | /* No need to do anything if no PMU CONFIG needed */ | |
224 | if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) | |
225 | return 0; | |
226 | ||
227 | if (mask) | |
228 | val = mask_val; | |
229 | ||
230 | ret = regmap_update_bits(wdt->pmureg, | |
231 | wdt->drv_data->disable_reg, | |
232 | mask_val, val); | |
233 | if (ret < 0) | |
234 | goto error; | |
235 | ||
236 | ret = regmap_update_bits(wdt->pmureg, | |
237 | wdt->drv_data->mask_reset_reg, | |
238 | mask_val, val); | |
239 | error: | |
240 | if (ret < 0) | |
241 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
242 | ||
243 | return ret; | |
244 | } | |
245 | ||
25dc46e3 | 246 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 247 | { |
af4ea631 LKA |
248 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
249 | ||
250 | spin_lock(&wdt->lock); | |
251 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
252 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
253 | |
254 | return 0; | |
1da177e4 LT |
255 | } |
256 | ||
af4ea631 | 257 | static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
41dc8b72 AC |
258 | { |
259 | unsigned long wtcon; | |
260 | ||
af4ea631 | 261 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
41dc8b72 | 262 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
af4ea631 | 263 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
41dc8b72 AC |
264 | } |
265 | ||
25dc46e3 | 266 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 | 267 | { |
af4ea631 LKA |
268 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
269 | ||
270 | spin_lock(&wdt->lock); | |
271 | __s3c2410wdt_stop(wdt); | |
272 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
273 | |
274 | return 0; | |
1da177e4 LT |
275 | } |
276 | ||
25dc46e3 | 277 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
278 | { |
279 | unsigned long wtcon; | |
af4ea631 | 280 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
1da177e4 | 281 | |
af4ea631 | 282 | spin_lock(&wdt->lock); |
41dc8b72 | 283 | |
af4ea631 | 284 | __s3c2410wdt_stop(wdt); |
1da177e4 | 285 | |
af4ea631 | 286 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
287 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
288 | ||
289 | if (soft_noboot) { | |
290 | wtcon |= S3C2410_WTCON_INTEN; | |
291 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
292 | } else { | |
293 | wtcon &= ~S3C2410_WTCON_INTEN; | |
294 | wtcon |= S3C2410_WTCON_RSTEN; | |
295 | } | |
296 | ||
456f53d6 KK |
297 | dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n", |
298 | wdt->count, wtcon); | |
1da177e4 | 299 | |
af4ea631 LKA |
300 | writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
301 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
302 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
303 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
304 | |
305 | return 0; | |
1da177e4 LT |
306 | } |
307 | ||
af4ea631 | 308 | static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
e02f838e | 309 | { |
af4ea631 | 310 | return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
e02f838e BD |
311 | } |
312 | ||
25dc46e3 | 313 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) |
1da177e4 | 314 | { |
af4ea631 LKA |
315 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
316 | unsigned long freq = clk_get_rate(wdt->clock); | |
1da177e4 LT |
317 | unsigned int count; |
318 | unsigned int divisor = 1; | |
319 | unsigned long wtcon; | |
320 | ||
321 | if (timeout < 1) | |
322 | return -EINVAL; | |
323 | ||
17862440 | 324 | freq = DIV_ROUND_UP(freq, 128); |
1da177e4 LT |
325 | count = timeout * freq; |
326 | ||
456f53d6 KK |
327 | dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n", |
328 | count, timeout, freq); | |
1da177e4 LT |
329 | |
330 | /* if the count is bigger than the watchdog register, | |
331 | then work out what we need to do (and if) we can | |
332 | actually make this value | |
333 | */ | |
334 | ||
335 | if (count >= 0x10000) { | |
17862440 | 336 | divisor = DIV_ROUND_UP(count, 0xffff); |
1da177e4 | 337 | |
17862440 | 338 | if (divisor > 0x100) { |
af4ea631 | 339 | dev_err(wdt->dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
340 | return -EINVAL; |
341 | } | |
342 | } | |
343 | ||
456f53d6 KK |
344 | dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n", |
345 | timeout, divisor, count, DIV_ROUND_UP(count, divisor)); | |
1da177e4 | 346 | |
17862440 | 347 | count = DIV_ROUND_UP(count, divisor); |
af4ea631 | 348 | wdt->count = count; |
1da177e4 LT |
349 | |
350 | /* update the pre-scaler */ | |
af4ea631 | 351 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
352 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
353 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
354 | ||
af4ea631 LKA |
355 | writel(count, wdt->reg_base + S3C2410_WTDAT); |
356 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
1da177e4 | 357 | |
5f2430f5 | 358 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 359 | |
1da177e4 LT |
360 | return 0; |
361 | } | |
362 | ||
4d8b229d GR |
363 | static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, |
364 | void *data) | |
c71f5cd2 DR |
365 | { |
366 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); | |
367 | void __iomem *wdt_base = wdt->reg_base; | |
368 | ||
369 | /* disable watchdog, to be safe */ | |
370 | writel(0, wdt_base + S3C2410_WTCON); | |
371 | ||
372 | /* put initial values into count and data */ | |
373 | writel(0x80, wdt_base + S3C2410_WTCNT); | |
374 | writel(0x80, wdt_base + S3C2410_WTDAT); | |
375 | ||
376 | /* set the watchdog to go and reset... */ | |
377 | writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | | |
378 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), | |
379 | wdt_base + S3C2410_WTCON); | |
380 | ||
381 | /* wait for reset to assert... */ | |
382 | mdelay(500); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
a77dba7e | 387 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 388 | |
41dc8b72 | 389 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
390 | .options = OPTIONS, |
391 | .firmware_version = 0, | |
392 | .identity = "S3C2410 Watchdog", | |
393 | }; | |
394 | ||
b893e344 | 395 | static const struct watchdog_ops s3c2410wdt_ops = { |
25dc46e3 WS |
396 | .owner = THIS_MODULE, |
397 | .start = s3c2410wdt_start, | |
398 | .stop = s3c2410wdt_stop, | |
399 | .ping = s3c2410wdt_keepalive, | |
400 | .set_timeout = s3c2410wdt_set_heartbeat, | |
c71f5cd2 | 401 | .restart = s3c2410wdt_restart, |
1da177e4 LT |
402 | }; |
403 | ||
58415efe | 404 | static const struct watchdog_device s3c2410_wdd = { |
25dc46e3 WS |
405 | .info = &s3c2410_wdt_ident, |
406 | .ops = &s3c2410wdt_ops, | |
4f21195d | 407 | .timeout = S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
408 | }; |
409 | ||
1da177e4 LT |
410 | /* interrupt handler code */ |
411 | ||
7d12e780 | 412 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 413 | { |
af4ea631 | 414 | struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
1da177e4 | 415 | |
af4ea631 LKA |
416 | dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
417 | ||
418 | s3c2410wdt_keepalive(&wdt->wdt_device); | |
0b445549 KK |
419 | |
420 | if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG) | |
421 | writel(0x1, wdt->reg_base + S3C2410_WTCLRINT); | |
422 | ||
1da177e4 LT |
423 | return IRQ_HANDLED; |
424 | } | |
e02f838e | 425 | |
0f1dd98d | 426 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
e02f838e BD |
427 | |
428 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
429 | unsigned long val, void *data) | |
430 | { | |
431 | int ret; | |
af4ea631 | 432 | struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
e02f838e | 433 | |
af4ea631 | 434 | if (!s3c2410wdt_is_running(wdt)) |
e02f838e BD |
435 | goto done; |
436 | ||
437 | if (val == CPUFREQ_PRECHANGE) { | |
438 | /* To ensure that over the change we don't cause the | |
439 | * watchdog to trigger, we perform an keep-alive if | |
440 | * the watchdog is running. | |
441 | */ | |
442 | ||
af4ea631 | 443 | s3c2410wdt_keepalive(&wdt->wdt_device); |
e02f838e | 444 | } else if (val == CPUFREQ_POSTCHANGE) { |
af4ea631 | 445 | s3c2410wdt_stop(&wdt->wdt_device); |
e02f838e | 446 | |
af4ea631 LKA |
447 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
448 | wdt->wdt_device.timeout); | |
e02f838e BD |
449 | |
450 | if (ret >= 0) | |
af4ea631 | 451 | s3c2410wdt_start(&wdt->wdt_device); |
e02f838e BD |
452 | else |
453 | goto err; | |
454 | } | |
455 | ||
456 | done: | |
457 | return 0; | |
458 | ||
459 | err: | |
af4ea631 LKA |
460 | dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
461 | wdt->wdt_device.timeout); | |
e02f838e BD |
462 | return ret; |
463 | } | |
464 | ||
af4ea631 | 465 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
e02f838e | 466 | { |
af4ea631 LKA |
467 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
468 | ||
469 | return cpufreq_register_notifier(&wdt->freq_transition, | |
e02f838e BD |
470 | CPUFREQ_TRANSITION_NOTIFIER); |
471 | } | |
472 | ||
af4ea631 | 473 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e | 474 | { |
af4ea631 LKA |
475 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
476 | ||
477 | cpufreq_unregister_notifier(&wdt->freq_transition, | |
e02f838e BD |
478 | CPUFREQ_TRANSITION_NOTIFIER); |
479 | } | |
480 | ||
481 | #else | |
af4ea631 LKA |
482 | |
483 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) | |
e02f838e BD |
484 | { |
485 | return 0; | |
486 | } | |
487 | ||
af4ea631 | 488 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e BD |
489 | { |
490 | } | |
491 | #endif | |
492 | ||
cffc9a60 DA |
493 | static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
494 | { | |
495 | unsigned int rst_stat; | |
496 | int ret; | |
497 | ||
498 | if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) | |
499 | return 0; | |
500 | ||
501 | ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); | |
502 | if (ret) | |
503 | dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); | |
504 | else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) | |
505 | return WDIOF_CARDRESET; | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
58415efe | 510 | static inline const struct s3c2410_wdt_variant * |
e3a60ead | 511 | s3c2410_get_wdt_drv_data(struct platform_device *pdev) |
4f1f653a LKA |
512 | { |
513 | if (pdev->dev.of_node) { | |
514 | const struct of_device_id *match; | |
515 | match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node); | |
516 | return (struct s3c2410_wdt_variant *)match->data; | |
517 | } else { | |
518 | return (struct s3c2410_wdt_variant *) | |
519 | platform_get_device_id(pdev)->driver_data; | |
520 | } | |
521 | } | |
522 | ||
2d991a16 | 523 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 524 | { |
e8ef92b8 | 525 | struct device *dev; |
af4ea631 LKA |
526 | struct s3c2410_wdt *wdt; |
527 | struct resource *wdt_mem; | |
528 | struct resource *wdt_irq; | |
46b814d6 | 529 | unsigned int wtcon; |
1da177e4 LT |
530 | int started = 0; |
531 | int ret; | |
1da177e4 | 532 | |
e8ef92b8 | 533 | dev = &pdev->dev; |
e8ef92b8 | 534 | |
af4ea631 LKA |
535 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
536 | if (!wdt) | |
537 | return -ENOMEM; | |
538 | ||
539 | wdt->dev = &pdev->dev; | |
540 | spin_lock_init(&wdt->lock); | |
541 | wdt->wdt_device = s3c2410_wdd; | |
1da177e4 | 542 | |
e3a60ead | 543 | wdt->drv_data = s3c2410_get_wdt_drv_data(pdev); |
cffc9a60 | 544 | if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
4f1f653a LKA |
545 | wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
546 | "samsung,syscon-phandle"); | |
547 | if (IS_ERR(wdt->pmureg)) { | |
548 | dev_err(dev, "syscon regmap lookup failed.\n"); | |
549 | return PTR_ERR(wdt->pmureg); | |
550 | } | |
551 | } | |
552 | ||
78d3e00b MH |
553 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
554 | if (wdt_irq == NULL) { | |
555 | dev_err(dev, "no irq resource specified\n"); | |
556 | ret = -ENOENT; | |
557 | goto err; | |
558 | } | |
559 | ||
560 | /* get the memory region for the watchdog timer */ | |
bd5cc119 | 561 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
af4ea631 LKA |
562 | wdt->reg_base = devm_ioremap_resource(dev, wdt_mem); |
563 | if (IS_ERR(wdt->reg_base)) { | |
564 | ret = PTR_ERR(wdt->reg_base); | |
04ecc7dc | 565 | goto err; |
1da177e4 LT |
566 | } |
567 | ||
af4ea631 LKA |
568 | wdt->clock = devm_clk_get(dev, "watchdog"); |
569 | if (IS_ERR(wdt->clock)) { | |
e8ef92b8 | 570 | dev_err(dev, "failed to find watchdog clock source\n"); |
af4ea631 | 571 | ret = PTR_ERR(wdt->clock); |
04ecc7dc | 572 | goto err; |
1da177e4 LT |
573 | } |
574 | ||
01b6af91 SK |
575 | ret = clk_prepare_enable(wdt->clock); |
576 | if (ret < 0) { | |
577 | dev_err(dev, "failed to enable clock\n"); | |
578 | return ret; | |
579 | } | |
1da177e4 | 580 | |
882dec1f JMC |
581 | wdt->wdt_device.min_timeout = 1; |
582 | wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock); | |
583 | ||
af4ea631 | 584 | ret = s3c2410wdt_cpufreq_register(wdt); |
78d3e00b | 585 | if (ret < 0) { |
3828924a | 586 | dev_err(dev, "failed to register cpufreq\n"); |
e02f838e BD |
587 | goto err_clk; |
588 | } | |
589 | ||
af4ea631 LKA |
590 | watchdog_set_drvdata(&wdt->wdt_device, wdt); |
591 | ||
1da177e4 LT |
592 | /* see if we can actually set the requested timer margin, and if |
593 | * not, try the default value */ | |
594 | ||
af4ea631 LKA |
595 | watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev); |
596 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
597 | wdt->wdt_device.timeout); | |
598 | if (ret) { | |
599 | started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
4f21195d | 600 | S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 601 | |
41dc8b72 AC |
602 | if (started == 0) |
603 | dev_info(dev, | |
604 | "tmr_margin value out of range, default %d used\n", | |
4f21195d | 605 | S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 606 | else |
a77dba7e WVS |
607 | dev_info(dev, "default timer value is out of range, " |
608 | "cannot start\n"); | |
1da177e4 LT |
609 | } |
610 | ||
04ecc7dc JH |
611 | ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
612 | pdev->name, pdev); | |
78d3e00b MH |
613 | if (ret != 0) { |
614 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
615 | goto err_cpufreq; | |
616 | } | |
617 | ||
af4ea631 | 618 | watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
c71f5cd2 | 619 | watchdog_set_restart_priority(&wdt->wdt_device, 128); |
ff0b3cd4 | 620 | |
cffc9a60 | 621 | wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
6551881c | 622 | wdt->wdt_device.parent = &pdev->dev; |
cffc9a60 | 623 | |
af4ea631 | 624 | ret = watchdog_register_device(&wdt->wdt_device); |
1da177e4 | 625 | if (ret) { |
25dc46e3 | 626 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
04ecc7dc | 627 | goto err_cpufreq; |
1da177e4 LT |
628 | } |
629 | ||
4f1f653a LKA |
630 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
631 | if (ret < 0) | |
632 | goto err_unregister; | |
633 | ||
1da177e4 | 634 | if (tmr_atboot && started == 0) { |
e8ef92b8 | 635 | dev_info(dev, "starting watchdog timer\n"); |
af4ea631 | 636 | s3c2410wdt_start(&wdt->wdt_device); |
655516c8 BD |
637 | } else if (!tmr_atboot) { |
638 | /* if we're not enabling the watchdog, then ensure it is | |
639 | * disabled if it has been left running from the bootloader | |
640 | * or other source */ | |
641 | ||
af4ea631 | 642 | s3c2410wdt_stop(&wdt->wdt_device); |
1da177e4 LT |
643 | } |
644 | ||
af4ea631 LKA |
645 | platform_set_drvdata(pdev, wdt); |
646 | ||
46b814d6 BD |
647 | /* print out a statement of readiness */ |
648 | ||
af4ea631 | 649 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
46b814d6 | 650 | |
e8ef92b8 | 651 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 652 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
653 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
654 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 655 | |
1da177e4 | 656 | return 0; |
0b6dd8a6 | 657 | |
4f1f653a LKA |
658 | err_unregister: |
659 | watchdog_unregister_device(&wdt->wdt_device); | |
660 | ||
e02f838e | 661 | err_cpufreq: |
af4ea631 | 662 | s3c2410wdt_cpufreq_deregister(wdt); |
e02f838e | 663 | |
0b6dd8a6 | 664 | err_clk: |
af4ea631 | 665 | clk_disable_unprepare(wdt->clock); |
0b6dd8a6 | 666 | |
78d3e00b | 667 | err: |
0b6dd8a6 | 668 | return ret; |
1da177e4 LT |
669 | } |
670 | ||
4b12b896 | 671 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 672 | { |
4f1f653a | 673 | int ret; |
af4ea631 LKA |
674 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
675 | ||
4f1f653a LKA |
676 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
677 | if (ret < 0) | |
678 | return ret; | |
679 | ||
af4ea631 | 680 | watchdog_unregister_device(&wdt->wdt_device); |
1da177e4 | 681 | |
af4ea631 | 682 | s3c2410wdt_cpufreq_deregister(wdt); |
1da177e4 | 683 | |
af4ea631 | 684 | clk_disable_unprepare(wdt->clock); |
1da177e4 | 685 | |
1da177e4 LT |
686 | return 0; |
687 | } | |
688 | ||
3ae5eaec | 689 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 690 | { |
af4ea631 LKA |
691 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
692 | ||
4f1f653a LKA |
693 | s3c2410wdt_mask_and_disable_reset(wdt, true); |
694 | ||
af4ea631 | 695 | s3c2410wdt_stop(&wdt->wdt_device); |
94f1e9f3 BD |
696 | } |
697 | ||
0183984c | 698 | #ifdef CONFIG_PM_SLEEP |
af4bb822 | 699 | |
0183984c | 700 | static int s3c2410wdt_suspend(struct device *dev) |
af4bb822 | 701 | { |
4f1f653a | 702 | int ret; |
af4ea631 LKA |
703 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
704 | ||
9480e307 | 705 | /* Save watchdog state, and turn it off. */ |
af4ea631 LKA |
706 | wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
707 | wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); | |
af4bb822 | 708 | |
4f1f653a LKA |
709 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
710 | if (ret < 0) | |
711 | return ret; | |
712 | ||
9480e307 | 713 | /* Note that WTCNT doesn't need to be saved. */ |
af4ea631 | 714 | s3c2410wdt_stop(&wdt->wdt_device); |
af4bb822 BD |
715 | |
716 | return 0; | |
717 | } | |
718 | ||
0183984c | 719 | static int s3c2410wdt_resume(struct device *dev) |
af4bb822 | 720 | { |
4f1f653a | 721 | int ret; |
af4ea631 | 722 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
af4bb822 | 723 | |
af4ea631 LKA |
724 | /* Restore watchdog state. */ |
725 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); | |
726 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ | |
727 | writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); | |
af4bb822 | 728 | |
4f1f653a LKA |
729 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
730 | if (ret < 0) | |
731 | return ret; | |
732 | ||
0183984c | 733 | dev_info(dev, "watchdog %sabled\n", |
af4ea631 | 734 | (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
af4bb822 BD |
735 | |
736 | return 0; | |
737 | } | |
0183984c | 738 | #endif |
af4bb822 | 739 | |
0183984c JH |
740 | static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
741 | s3c2410wdt_resume); | |
af4bb822 | 742 | |
3ae5eaec | 743 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 744 | .probe = s3c2410wdt_probe, |
82268714 | 745 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 746 | .shutdown = s3c2410wdt_shutdown, |
4f1f653a | 747 | .id_table = s3c2410_wdt_ids, |
3ae5eaec | 748 | .driver = { |
3ae5eaec | 749 | .name = "s3c2410-wdt", |
0183984c | 750 | .pm = &s3c2410wdt_pm_ops, |
3016a552 | 751 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 752 | }, |
1da177e4 LT |
753 | }; |
754 | ||
6b761b29 | 755 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 756 | |
af4bb822 BD |
757 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
758 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
759 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
760 | MODULE_LICENSE("GPL"); |