Commit | Line | Data |
---|---|---|
08497f22 | 1 | /* |
1da177e4 LT |
2 | * Copyright (c) 2004 Simtec Electronics |
3 | * Ben Dooks <ben@simtec.co.uk> | |
4 | * | |
5 | * S3C2410 Watchdog Timer Support | |
6 | * | |
7 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 8 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
08497f22 | 19 | */ |
1da177e4 LT |
20 | |
21 | #include <linux/module.h> | |
22 | #include <linux/moduleparam.h> | |
1da177e4 LT |
23 | #include <linux/types.h> |
24 | #include <linux/timer.h> | |
1da177e4 | 25 | #include <linux/watchdog.h> |
d052d1be | 26 | #include <linux/platform_device.h> |
1da177e4 | 27 | #include <linux/interrupt.h> |
f8ce2547 | 28 | #include <linux/clk.h> |
41dc8b72 AC |
29 | #include <linux/uaccess.h> |
30 | #include <linux/io.h> | |
e02f838e | 31 | #include <linux/cpufreq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
25dc46e3 | 33 | #include <linux/err.h> |
3016a552 | 34 | #include <linux/of.h> |
a9a02c46 | 35 | #include <linux/of_device.h> |
4f1f653a LKA |
36 | #include <linux/mfd/syscon.h> |
37 | #include <linux/regmap.h> | |
f286e133 | 38 | #include <linux/delay.h> |
1da177e4 | 39 | |
a8f5401a TF |
40 | #define S3C2410_WTCON 0x00 |
41 | #define S3C2410_WTDAT 0x04 | |
42 | #define S3C2410_WTCNT 0x08 | |
0b445549 | 43 | #define S3C2410_WTCLRINT 0x0c |
1da177e4 | 44 | |
882dec1f JMC |
45 | #define S3C2410_WTCNT_MAXCNT 0xffff |
46 | ||
a8f5401a TF |
47 | #define S3C2410_WTCON_RSTEN (1 << 0) |
48 | #define S3C2410_WTCON_INTEN (1 << 2) | |
49 | #define S3C2410_WTCON_ENABLE (1 << 5) | |
1da177e4 | 50 | |
a8f5401a TF |
51 | #define S3C2410_WTCON_DIV16 (0 << 3) |
52 | #define S3C2410_WTCON_DIV32 (1 << 3) | |
53 | #define S3C2410_WTCON_DIV64 (2 << 3) | |
54 | #define S3C2410_WTCON_DIV128 (3 << 3) | |
55 | ||
882dec1f JMC |
56 | #define S3C2410_WTCON_MAXDIV 0x80 |
57 | ||
a8f5401a TF |
58 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) |
59 | #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) | |
882dec1f | 60 | #define S3C2410_WTCON_PRESCALE_MAX 0xff |
1da177e4 | 61 | |
4f21195d KK |
62 | #define S3C2410_WATCHDOG_ATBOOT (0) |
63 | #define S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
1da177e4 | 64 | |
cffc9a60 | 65 | #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
4f1f653a LKA |
66 | #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
67 | #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c | |
68 | #define QUIRK_HAS_PMU_CONFIG (1 << 0) | |
cffc9a60 | 69 | #define QUIRK_HAS_RST_STAT (1 << 1) |
0b445549 | 70 | #define QUIRK_HAS_WTCLRINT_REG (1 << 2) |
cffc9a60 DA |
71 | |
72 | /* These quirks require that we have a PMU register map */ | |
73 | #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ | |
74 | QUIRK_HAS_RST_STAT) | |
4f1f653a | 75 | |
86a1e189 | 76 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 77 | static int tmr_margin; |
4f21195d | 78 | static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 | 79 | static int soft_noboot; |
1da177e4 LT |
80 | |
81 | module_param(tmr_margin, int, 0); | |
82 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 83 | module_param(nowayout, bool, 0); |
1da177e4 | 84 | module_param(soft_noboot, int, 0); |
1da177e4 | 85 | |
76550d32 | 86 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
4f21195d | 87 | __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
41dc8b72 AC |
88 | MODULE_PARM_DESC(tmr_atboot, |
89 | "Watchdog is started at boot time if set to 1, default=" | |
4f21195d | 90 | __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT)); |
41dc8b72 AC |
91 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
92 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
08497f22 | 93 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)"); |
1da177e4 | 94 | |
4f1f653a LKA |
95 | /** |
96 | * struct s3c2410_wdt_variant - Per-variant config data | |
97 | * | |
98 | * @disable_reg: Offset in pmureg for the register that disables the watchdog | |
99 | * timer reset functionality. | |
100 | * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog | |
101 | * timer reset functionality. | |
102 | * @mask_bit: Bit number for the watchdog timer in the disable register and the | |
103 | * mask reset register. | |
cffc9a60 DA |
104 | * @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
105 | * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog | |
106 | * reset. | |
4f1f653a LKA |
107 | * @quirks: A bitfield of quirks. |
108 | */ | |
109 | ||
110 | struct s3c2410_wdt_variant { | |
111 | int disable_reg; | |
112 | int mask_reset_reg; | |
113 | int mask_bit; | |
cffc9a60 DA |
114 | int rst_stat_reg; |
115 | int rst_stat_bit; | |
4f1f653a LKA |
116 | u32 quirks; |
117 | }; | |
118 | ||
af4ea631 LKA |
119 | struct s3c2410_wdt { |
120 | struct device *dev; | |
121 | struct clk *clock; | |
122 | void __iomem *reg_base; | |
123 | unsigned int count; | |
124 | spinlock_t lock; | |
125 | unsigned long wtcon_save; | |
126 | unsigned long wtdat_save; | |
127 | struct watchdog_device wdt_device; | |
128 | struct notifier_block freq_transition; | |
58415efe | 129 | const struct s3c2410_wdt_variant *drv_data; |
4f1f653a LKA |
130 | struct regmap *pmureg; |
131 | }; | |
132 | ||
133 | static const struct s3c2410_wdt_variant drv_data_s3c2410 = { | |
134 | .quirks = 0 | |
135 | }; | |
136 | ||
137 | #ifdef CONFIG_OF | |
0b445549 KK |
138 | static const struct s3c2410_wdt_variant drv_data_s3c6410 = { |
139 | .quirks = QUIRK_HAS_WTCLRINT_REG, | |
140 | }; | |
141 | ||
4f1f653a LKA |
142 | static const struct s3c2410_wdt_variant drv_data_exynos5250 = { |
143 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
144 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
145 | .mask_bit = 20, | |
cffc9a60 DA |
146 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
147 | .rst_stat_bit = 20, | |
0b445549 KK |
148 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
149 | | QUIRK_HAS_WTCLRINT_REG, | |
4f1f653a LKA |
150 | }; |
151 | ||
152 | static const struct s3c2410_wdt_variant drv_data_exynos5420 = { | |
153 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
154 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
155 | .mask_bit = 0, | |
cffc9a60 DA |
156 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
157 | .rst_stat_bit = 9, | |
0b445549 KK |
158 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
159 | | QUIRK_HAS_WTCLRINT_REG, | |
4f1f653a LKA |
160 | }; |
161 | ||
2b9366b6 NKC |
162 | static const struct s3c2410_wdt_variant drv_data_exynos7 = { |
163 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
164 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
5476b2b7 | 165 | .mask_bit = 23, |
2b9366b6 NKC |
166 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
167 | .rst_stat_bit = 23, /* A57 WDTRESET */ | |
0b445549 KK |
168 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
169 | | QUIRK_HAS_WTCLRINT_REG, | |
2b9366b6 NKC |
170 | }; |
171 | ||
4f1f653a LKA |
172 | static const struct of_device_id s3c2410_wdt_match[] = { |
173 | { .compatible = "samsung,s3c2410-wdt", | |
174 | .data = &drv_data_s3c2410 }, | |
0b445549 KK |
175 | { .compatible = "samsung,s3c6410-wdt", |
176 | .data = &drv_data_s3c6410 }, | |
4f1f653a LKA |
177 | { .compatible = "samsung,exynos5250-wdt", |
178 | .data = &drv_data_exynos5250 }, | |
179 | { .compatible = "samsung,exynos5420-wdt", | |
180 | .data = &drv_data_exynos5420 }, | |
2b9366b6 NKC |
181 | { .compatible = "samsung,exynos7-wdt", |
182 | .data = &drv_data_exynos7 }, | |
4f1f653a | 183 | {}, |
af4ea631 | 184 | }; |
4f1f653a LKA |
185 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
186 | #endif | |
187 | ||
188 | static const struct platform_device_id s3c2410_wdt_ids[] = { | |
189 | { | |
190 | .name = "s3c2410-wdt", | |
191 | .driver_data = (unsigned long)&drv_data_s3c2410, | |
192 | }, | |
193 | {} | |
194 | }; | |
195 | MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); | |
1da177e4 | 196 | |
1da177e4 LT |
197 | /* functions */ |
198 | ||
882dec1f JMC |
199 | static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock) |
200 | { | |
201 | unsigned long freq = clk_get_rate(clock); | |
202 | ||
203 | return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) | |
204 | / S3C2410_WTCON_MAXDIV); | |
205 | } | |
206 | ||
af4ea631 LKA |
207 | static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
208 | { | |
209 | return container_of(nb, struct s3c2410_wdt, freq_transition); | |
210 | } | |
211 | ||
4f1f653a LKA |
212 | static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) |
213 | { | |
214 | int ret; | |
215 | u32 mask_val = 1 << wdt->drv_data->mask_bit; | |
216 | u32 val = 0; | |
217 | ||
218 | /* No need to do anything if no PMU CONFIG needed */ | |
219 | if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) | |
220 | return 0; | |
221 | ||
222 | if (mask) | |
223 | val = mask_val; | |
224 | ||
225 | ret = regmap_update_bits(wdt->pmureg, | |
226 | wdt->drv_data->disable_reg, | |
227 | mask_val, val); | |
228 | if (ret < 0) | |
229 | goto error; | |
230 | ||
231 | ret = regmap_update_bits(wdt->pmureg, | |
232 | wdt->drv_data->mask_reset_reg, | |
233 | mask_val, val); | |
234 | error: | |
235 | if (ret < 0) | |
236 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
237 | ||
238 | return ret; | |
239 | } | |
240 | ||
25dc46e3 | 241 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 242 | { |
af4ea631 LKA |
243 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
244 | ||
245 | spin_lock(&wdt->lock); | |
246 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
247 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
248 | |
249 | return 0; | |
1da177e4 LT |
250 | } |
251 | ||
af4ea631 | 252 | static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
41dc8b72 AC |
253 | { |
254 | unsigned long wtcon; | |
255 | ||
af4ea631 | 256 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
41dc8b72 | 257 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
af4ea631 | 258 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
41dc8b72 AC |
259 | } |
260 | ||
25dc46e3 | 261 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 | 262 | { |
af4ea631 LKA |
263 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
264 | ||
265 | spin_lock(&wdt->lock); | |
266 | __s3c2410wdt_stop(wdt); | |
267 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
268 | |
269 | return 0; | |
1da177e4 LT |
270 | } |
271 | ||
25dc46e3 | 272 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
273 | { |
274 | unsigned long wtcon; | |
af4ea631 | 275 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
1da177e4 | 276 | |
af4ea631 | 277 | spin_lock(&wdt->lock); |
41dc8b72 | 278 | |
af4ea631 | 279 | __s3c2410wdt_stop(wdt); |
1da177e4 | 280 | |
af4ea631 | 281 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
282 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
283 | ||
284 | if (soft_noboot) { | |
285 | wtcon |= S3C2410_WTCON_INTEN; | |
286 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
287 | } else { | |
288 | wtcon &= ~S3C2410_WTCON_INTEN; | |
289 | wtcon |= S3C2410_WTCON_RSTEN; | |
290 | } | |
291 | ||
456f53d6 KK |
292 | dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n", |
293 | wdt->count, wtcon); | |
1da177e4 | 294 | |
af4ea631 LKA |
295 | writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
296 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
297 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
298 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
299 | |
300 | return 0; | |
1da177e4 LT |
301 | } |
302 | ||
af4ea631 | 303 | static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
e02f838e | 304 | { |
af4ea631 | 305 | return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
e02f838e BD |
306 | } |
307 | ||
08497f22 KK |
308 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, |
309 | unsigned int timeout) | |
1da177e4 | 310 | { |
af4ea631 LKA |
311 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
312 | unsigned long freq = clk_get_rate(wdt->clock); | |
1da177e4 LT |
313 | unsigned int count; |
314 | unsigned int divisor = 1; | |
315 | unsigned long wtcon; | |
316 | ||
317 | if (timeout < 1) | |
318 | return -EINVAL; | |
319 | ||
17862440 | 320 | freq = DIV_ROUND_UP(freq, 128); |
1da177e4 LT |
321 | count = timeout * freq; |
322 | ||
456f53d6 KK |
323 | dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n", |
324 | count, timeout, freq); | |
1da177e4 LT |
325 | |
326 | /* if the count is bigger than the watchdog register, | |
327 | then work out what we need to do (and if) we can | |
328 | actually make this value | |
329 | */ | |
330 | ||
331 | if (count >= 0x10000) { | |
17862440 | 332 | divisor = DIV_ROUND_UP(count, 0xffff); |
1da177e4 | 333 | |
17862440 | 334 | if (divisor > 0x100) { |
af4ea631 | 335 | dev_err(wdt->dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
336 | return -EINVAL; |
337 | } | |
338 | } | |
339 | ||
456f53d6 KK |
340 | dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n", |
341 | timeout, divisor, count, DIV_ROUND_UP(count, divisor)); | |
1da177e4 | 342 | |
17862440 | 343 | count = DIV_ROUND_UP(count, divisor); |
af4ea631 | 344 | wdt->count = count; |
1da177e4 LT |
345 | |
346 | /* update the pre-scaler */ | |
af4ea631 | 347 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
348 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
349 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
350 | ||
af4ea631 LKA |
351 | writel(count, wdt->reg_base + S3C2410_WTDAT); |
352 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
1da177e4 | 353 | |
5f2430f5 | 354 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 355 | |
1da177e4 LT |
356 | return 0; |
357 | } | |
358 | ||
4d8b229d GR |
359 | static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, |
360 | void *data) | |
c71f5cd2 DR |
361 | { |
362 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); | |
363 | void __iomem *wdt_base = wdt->reg_base; | |
364 | ||
365 | /* disable watchdog, to be safe */ | |
366 | writel(0, wdt_base + S3C2410_WTCON); | |
367 | ||
368 | /* put initial values into count and data */ | |
369 | writel(0x80, wdt_base + S3C2410_WTCNT); | |
370 | writel(0x80, wdt_base + S3C2410_WTDAT); | |
371 | ||
372 | /* set the watchdog to go and reset... */ | |
373 | writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | | |
374 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), | |
375 | wdt_base + S3C2410_WTCON); | |
376 | ||
377 | /* wait for reset to assert... */ | |
378 | mdelay(500); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
a77dba7e | 383 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 384 | |
41dc8b72 | 385 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
386 | .options = OPTIONS, |
387 | .firmware_version = 0, | |
388 | .identity = "S3C2410 Watchdog", | |
389 | }; | |
390 | ||
b893e344 | 391 | static const struct watchdog_ops s3c2410wdt_ops = { |
25dc46e3 WS |
392 | .owner = THIS_MODULE, |
393 | .start = s3c2410wdt_start, | |
394 | .stop = s3c2410wdt_stop, | |
395 | .ping = s3c2410wdt_keepalive, | |
396 | .set_timeout = s3c2410wdt_set_heartbeat, | |
c71f5cd2 | 397 | .restart = s3c2410wdt_restart, |
1da177e4 LT |
398 | }; |
399 | ||
58415efe | 400 | static const struct watchdog_device s3c2410_wdd = { |
25dc46e3 WS |
401 | .info = &s3c2410_wdt_ident, |
402 | .ops = &s3c2410wdt_ops, | |
4f21195d | 403 | .timeout = S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
404 | }; |
405 | ||
1da177e4 LT |
406 | /* interrupt handler code */ |
407 | ||
7d12e780 | 408 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 409 | { |
af4ea631 | 410 | struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
1da177e4 | 411 | |
af4ea631 LKA |
412 | dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
413 | ||
414 | s3c2410wdt_keepalive(&wdt->wdt_device); | |
0b445549 KK |
415 | |
416 | if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG) | |
417 | writel(0x1, wdt->reg_base + S3C2410_WTCLRINT); | |
418 | ||
1da177e4 LT |
419 | return IRQ_HANDLED; |
420 | } | |
e02f838e | 421 | |
0f1dd98d | 422 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
e02f838e BD |
423 | |
424 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
425 | unsigned long val, void *data) | |
426 | { | |
427 | int ret; | |
af4ea631 | 428 | struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
e02f838e | 429 | |
af4ea631 | 430 | if (!s3c2410wdt_is_running(wdt)) |
e02f838e BD |
431 | goto done; |
432 | ||
433 | if (val == CPUFREQ_PRECHANGE) { | |
434 | /* To ensure that over the change we don't cause the | |
435 | * watchdog to trigger, we perform an keep-alive if | |
436 | * the watchdog is running. | |
437 | */ | |
438 | ||
af4ea631 | 439 | s3c2410wdt_keepalive(&wdt->wdt_device); |
e02f838e | 440 | } else if (val == CPUFREQ_POSTCHANGE) { |
af4ea631 | 441 | s3c2410wdt_stop(&wdt->wdt_device); |
e02f838e | 442 | |
af4ea631 LKA |
443 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
444 | wdt->wdt_device.timeout); | |
e02f838e BD |
445 | |
446 | if (ret >= 0) | |
af4ea631 | 447 | s3c2410wdt_start(&wdt->wdt_device); |
e02f838e BD |
448 | else |
449 | goto err; | |
450 | } | |
451 | ||
452 | done: | |
453 | return 0; | |
454 | ||
455 | err: | |
af4ea631 LKA |
456 | dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
457 | wdt->wdt_device.timeout); | |
e02f838e BD |
458 | return ret; |
459 | } | |
460 | ||
af4ea631 | 461 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
e02f838e | 462 | { |
af4ea631 LKA |
463 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
464 | ||
465 | return cpufreq_register_notifier(&wdt->freq_transition, | |
e02f838e BD |
466 | CPUFREQ_TRANSITION_NOTIFIER); |
467 | } | |
468 | ||
af4ea631 | 469 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e | 470 | { |
af4ea631 LKA |
471 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
472 | ||
473 | cpufreq_unregister_notifier(&wdt->freq_transition, | |
e02f838e BD |
474 | CPUFREQ_TRANSITION_NOTIFIER); |
475 | } | |
476 | ||
477 | #else | |
af4ea631 LKA |
478 | |
479 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) | |
e02f838e BD |
480 | { |
481 | return 0; | |
482 | } | |
483 | ||
af4ea631 | 484 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e BD |
485 | { |
486 | } | |
487 | #endif | |
488 | ||
cffc9a60 DA |
489 | static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
490 | { | |
491 | unsigned int rst_stat; | |
492 | int ret; | |
493 | ||
494 | if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) | |
495 | return 0; | |
496 | ||
497 | ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); | |
498 | if (ret) | |
499 | dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); | |
500 | else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) | |
501 | return WDIOF_CARDRESET; | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
58415efe | 506 | static inline const struct s3c2410_wdt_variant * |
e3a60ead | 507 | s3c2410_get_wdt_drv_data(struct platform_device *pdev) |
4f1f653a | 508 | { |
a9a02c46 KK |
509 | const struct s3c2410_wdt_variant *variant; |
510 | ||
511 | variant = of_device_get_match_data(&pdev->dev); | |
512 | if (!variant) { | |
513 | /* Device matched by platform_device_id */ | |
514 | variant = (struct s3c2410_wdt_variant *) | |
515 | platform_get_device_id(pdev)->driver_data; | |
4f1f653a | 516 | } |
a9a02c46 KK |
517 | |
518 | return variant; | |
4f1f653a LKA |
519 | } |
520 | ||
2d991a16 | 521 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 522 | { |
08497f22 | 523 | struct device *dev = &pdev->dev; |
af4ea631 LKA |
524 | struct s3c2410_wdt *wdt; |
525 | struct resource *wdt_mem; | |
526 | struct resource *wdt_irq; | |
46b814d6 | 527 | unsigned int wtcon; |
1da177e4 LT |
528 | int started = 0; |
529 | int ret; | |
1da177e4 | 530 | |
af4ea631 LKA |
531 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
532 | if (!wdt) | |
533 | return -ENOMEM; | |
534 | ||
08497f22 | 535 | wdt->dev = dev; |
af4ea631 LKA |
536 | spin_lock_init(&wdt->lock); |
537 | wdt->wdt_device = s3c2410_wdd; | |
1da177e4 | 538 | |
e3a60ead | 539 | wdt->drv_data = s3c2410_get_wdt_drv_data(pdev); |
cffc9a60 | 540 | if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
4f1f653a LKA |
541 | wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
542 | "samsung,syscon-phandle"); | |
543 | if (IS_ERR(wdt->pmureg)) { | |
544 | dev_err(dev, "syscon regmap lookup failed.\n"); | |
545 | return PTR_ERR(wdt->pmureg); | |
546 | } | |
547 | } | |
548 | ||
78d3e00b MH |
549 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
550 | if (wdt_irq == NULL) { | |
551 | dev_err(dev, "no irq resource specified\n"); | |
552 | ret = -ENOENT; | |
553 | goto err; | |
554 | } | |
555 | ||
556 | /* get the memory region for the watchdog timer */ | |
bd5cc119 | 557 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
af4ea631 LKA |
558 | wdt->reg_base = devm_ioremap_resource(dev, wdt_mem); |
559 | if (IS_ERR(wdt->reg_base)) { | |
560 | ret = PTR_ERR(wdt->reg_base); | |
04ecc7dc | 561 | goto err; |
1da177e4 LT |
562 | } |
563 | ||
af4ea631 LKA |
564 | wdt->clock = devm_clk_get(dev, "watchdog"); |
565 | if (IS_ERR(wdt->clock)) { | |
e8ef92b8 | 566 | dev_err(dev, "failed to find watchdog clock source\n"); |
af4ea631 | 567 | ret = PTR_ERR(wdt->clock); |
04ecc7dc | 568 | goto err; |
1da177e4 LT |
569 | } |
570 | ||
01b6af91 SK |
571 | ret = clk_prepare_enable(wdt->clock); |
572 | if (ret < 0) { | |
573 | dev_err(dev, "failed to enable clock\n"); | |
574 | return ret; | |
575 | } | |
1da177e4 | 576 | |
882dec1f JMC |
577 | wdt->wdt_device.min_timeout = 1; |
578 | wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock); | |
579 | ||
af4ea631 | 580 | ret = s3c2410wdt_cpufreq_register(wdt); |
78d3e00b | 581 | if (ret < 0) { |
3828924a | 582 | dev_err(dev, "failed to register cpufreq\n"); |
e02f838e BD |
583 | goto err_clk; |
584 | } | |
585 | ||
af4ea631 LKA |
586 | watchdog_set_drvdata(&wdt->wdt_device, wdt); |
587 | ||
1da177e4 LT |
588 | /* see if we can actually set the requested timer margin, and if |
589 | * not, try the default value */ | |
590 | ||
08497f22 | 591 | watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev); |
af4ea631 LKA |
592 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
593 | wdt->wdt_device.timeout); | |
594 | if (ret) { | |
595 | started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
4f21195d | 596 | S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 597 | |
41dc8b72 AC |
598 | if (started == 0) |
599 | dev_info(dev, | |
08497f22 KK |
600 | "tmr_margin value out of range, default %d used\n", |
601 | S3C2410_WATCHDOG_DEFAULT_TIME); | |
41dc8b72 | 602 | else |
08497f22 | 603 | dev_info(dev, "default timer value is out of range, cannot start\n"); |
1da177e4 LT |
604 | } |
605 | ||
04ecc7dc JH |
606 | ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
607 | pdev->name, pdev); | |
78d3e00b MH |
608 | if (ret != 0) { |
609 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
610 | goto err_cpufreq; | |
611 | } | |
612 | ||
af4ea631 | 613 | watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
c71f5cd2 | 614 | watchdog_set_restart_priority(&wdt->wdt_device, 128); |
ff0b3cd4 | 615 | |
cffc9a60 | 616 | wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
08497f22 | 617 | wdt->wdt_device.parent = dev; |
cffc9a60 | 618 | |
af4ea631 | 619 | ret = watchdog_register_device(&wdt->wdt_device); |
1da177e4 | 620 | if (ret) { |
25dc46e3 | 621 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
04ecc7dc | 622 | goto err_cpufreq; |
1da177e4 LT |
623 | } |
624 | ||
4f1f653a LKA |
625 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
626 | if (ret < 0) | |
627 | goto err_unregister; | |
628 | ||
1da177e4 | 629 | if (tmr_atboot && started == 0) { |
e8ef92b8 | 630 | dev_info(dev, "starting watchdog timer\n"); |
af4ea631 | 631 | s3c2410wdt_start(&wdt->wdt_device); |
655516c8 BD |
632 | } else if (!tmr_atboot) { |
633 | /* if we're not enabling the watchdog, then ensure it is | |
634 | * disabled if it has been left running from the bootloader | |
635 | * or other source */ | |
636 | ||
af4ea631 | 637 | s3c2410wdt_stop(&wdt->wdt_device); |
1da177e4 LT |
638 | } |
639 | ||
af4ea631 LKA |
640 | platform_set_drvdata(pdev, wdt); |
641 | ||
46b814d6 BD |
642 | /* print out a statement of readiness */ |
643 | ||
af4ea631 | 644 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
46b814d6 | 645 | |
e8ef92b8 | 646 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 647 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
648 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
649 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 650 | |
1da177e4 | 651 | return 0; |
0b6dd8a6 | 652 | |
4f1f653a LKA |
653 | err_unregister: |
654 | watchdog_unregister_device(&wdt->wdt_device); | |
655 | ||
e02f838e | 656 | err_cpufreq: |
af4ea631 | 657 | s3c2410wdt_cpufreq_deregister(wdt); |
e02f838e | 658 | |
0b6dd8a6 | 659 | err_clk: |
af4ea631 | 660 | clk_disable_unprepare(wdt->clock); |
0b6dd8a6 | 661 | |
78d3e00b | 662 | err: |
0b6dd8a6 | 663 | return ret; |
1da177e4 LT |
664 | } |
665 | ||
4b12b896 | 666 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 667 | { |
4f1f653a | 668 | int ret; |
af4ea631 LKA |
669 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
670 | ||
4f1f653a LKA |
671 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
672 | if (ret < 0) | |
673 | return ret; | |
674 | ||
af4ea631 | 675 | watchdog_unregister_device(&wdt->wdt_device); |
1da177e4 | 676 | |
af4ea631 | 677 | s3c2410wdt_cpufreq_deregister(wdt); |
1da177e4 | 678 | |
af4ea631 | 679 | clk_disable_unprepare(wdt->clock); |
1da177e4 | 680 | |
1da177e4 LT |
681 | return 0; |
682 | } | |
683 | ||
3ae5eaec | 684 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 685 | { |
af4ea631 LKA |
686 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
687 | ||
4f1f653a LKA |
688 | s3c2410wdt_mask_and_disable_reset(wdt, true); |
689 | ||
af4ea631 | 690 | s3c2410wdt_stop(&wdt->wdt_device); |
94f1e9f3 BD |
691 | } |
692 | ||
0183984c | 693 | #ifdef CONFIG_PM_SLEEP |
af4bb822 | 694 | |
0183984c | 695 | static int s3c2410wdt_suspend(struct device *dev) |
af4bb822 | 696 | { |
4f1f653a | 697 | int ret; |
af4ea631 LKA |
698 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
699 | ||
9480e307 | 700 | /* Save watchdog state, and turn it off. */ |
af4ea631 LKA |
701 | wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
702 | wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); | |
af4bb822 | 703 | |
4f1f653a LKA |
704 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
705 | if (ret < 0) | |
706 | return ret; | |
707 | ||
9480e307 | 708 | /* Note that WTCNT doesn't need to be saved. */ |
af4ea631 | 709 | s3c2410wdt_stop(&wdt->wdt_device); |
af4bb822 BD |
710 | |
711 | return 0; | |
712 | } | |
713 | ||
0183984c | 714 | static int s3c2410wdt_resume(struct device *dev) |
af4bb822 | 715 | { |
4f1f653a | 716 | int ret; |
af4ea631 | 717 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
af4bb822 | 718 | |
af4ea631 LKA |
719 | /* Restore watchdog state. */ |
720 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); | |
721 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ | |
722 | writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); | |
af4bb822 | 723 | |
4f1f653a LKA |
724 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
725 | if (ret < 0) | |
726 | return ret; | |
727 | ||
0183984c | 728 | dev_info(dev, "watchdog %sabled\n", |
af4ea631 | 729 | (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
af4bb822 BD |
730 | |
731 | return 0; | |
732 | } | |
0183984c | 733 | #endif |
af4bb822 | 734 | |
0183984c JH |
735 | static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
736 | s3c2410wdt_resume); | |
af4bb822 | 737 | |
3ae5eaec | 738 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 739 | .probe = s3c2410wdt_probe, |
82268714 | 740 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 741 | .shutdown = s3c2410wdt_shutdown, |
4f1f653a | 742 | .id_table = s3c2410_wdt_ids, |
3ae5eaec | 743 | .driver = { |
3ae5eaec | 744 | .name = "s3c2410-wdt", |
0183984c | 745 | .pm = &s3c2410wdt_pm_ops, |
3016a552 | 746 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 747 | }, |
1da177e4 LT |
748 | }; |
749 | ||
6b761b29 | 750 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 751 | |
08497f22 | 752 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>"); |
1da177e4 LT |
753 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
754 | MODULE_LICENSE("GPL"); |