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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
08497f22 | 2 | /* |
1da177e4 LT |
3 | * Copyright (c) 2004 Simtec Electronics |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
08497f22 | 10 | */ |
1da177e4 LT |
11 | |
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/timer.h> | |
1da177e4 | 16 | #include <linux/watchdog.h> |
d052d1be | 17 | #include <linux/platform_device.h> |
1da177e4 | 18 | #include <linux/interrupt.h> |
f8ce2547 | 19 | #include <linux/clk.h> |
41dc8b72 AC |
20 | #include <linux/uaccess.h> |
21 | #include <linux/io.h> | |
e02f838e | 22 | #include <linux/cpufreq.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
25dc46e3 | 24 | #include <linux/err.h> |
3016a552 | 25 | #include <linux/of.h> |
a9a02c46 | 26 | #include <linux/of_device.h> |
4f1f653a LKA |
27 | #include <linux/mfd/syscon.h> |
28 | #include <linux/regmap.h> | |
f286e133 | 29 | #include <linux/delay.h> |
1da177e4 | 30 | |
a8f5401a TF |
31 | #define S3C2410_WTCON 0x00 |
32 | #define S3C2410_WTDAT 0x04 | |
33 | #define S3C2410_WTCNT 0x08 | |
0b445549 | 34 | #define S3C2410_WTCLRINT 0x0c |
1da177e4 | 35 | |
882dec1f JMC |
36 | #define S3C2410_WTCNT_MAXCNT 0xffff |
37 | ||
a8f5401a TF |
38 | #define S3C2410_WTCON_RSTEN (1 << 0) |
39 | #define S3C2410_WTCON_INTEN (1 << 2) | |
40 | #define S3C2410_WTCON_ENABLE (1 << 5) | |
1da177e4 | 41 | |
a8f5401a TF |
42 | #define S3C2410_WTCON_DIV16 (0 << 3) |
43 | #define S3C2410_WTCON_DIV32 (1 << 3) | |
44 | #define S3C2410_WTCON_DIV64 (2 << 3) | |
45 | #define S3C2410_WTCON_DIV128 (3 << 3) | |
46 | ||
882dec1f JMC |
47 | #define S3C2410_WTCON_MAXDIV 0x80 |
48 | ||
a8f5401a TF |
49 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) |
50 | #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) | |
882dec1f | 51 | #define S3C2410_WTCON_PRESCALE_MAX 0xff |
1da177e4 | 52 | |
4f21195d KK |
53 | #define S3C2410_WATCHDOG_ATBOOT (0) |
54 | #define S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
1da177e4 | 55 | |
cffc9a60 | 56 | #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
4f1f653a LKA |
57 | #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
58 | #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c | |
cd4eadf2 SP |
59 | #define EXYNOS850_CLUSTER0_NONCPU_OUT 0x1220 |
60 | #define EXYNOS850_CLUSTER0_NONCPU_INT_EN 0x1244 | |
61 | #define EXYNOS850_CLUSTER1_NONCPU_OUT 0x1620 | |
62 | #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644 | |
63 | ||
64 | #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24 | |
65 | #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23 | |
cf3fad4e SP |
66 | |
67 | /** | |
68 | * DOC: Quirk flags for different Samsung watchdog IP-cores | |
69 | * | |
70 | * This driver supports multiple Samsung SoCs, each of which might have | |
71 | * different set of registers and features supported. As watchdog block | |
72 | * sometimes requires modifying PMU registers for proper functioning, register | |
73 | * differences in both watchdog and PMU IP-cores should be accounted for. Quirk | |
74 | * flags described below serve the purpose of telling the driver about mentioned | |
75 | * SoC traits, and can be specified in driver data for each particular supported | |
76 | * device. | |
77 | * | |
78 | * %QUIRK_HAS_WTCLRINT_REG: Watchdog block has WTCLRINT register. It's used to | |
79 | * clear the interrupt once the interrupt service routine is complete. It's | |
80 | * write-only, writing any values to this register clears the interrupt, but | |
81 | * reading is not permitted. | |
82 | * | |
83 | * %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling | |
84 | * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST, | |
85 | * new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value is | |
86 | * inverted compared to the former one. | |
87 | * | |
88 | * %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register, | |
89 | * which contains bits indicating the reason for most recent CPU reset. If | |
90 | * present, driver will use this register to check if previous reboot was due to | |
91 | * watchdog timer reset. | |
92 | * | |
93 | * %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE | |
94 | * register. If 'mask_bit' bit is set, PMU will disable WDT reset when | |
95 | * corresponding processor is in reset state. | |
96 | * | |
97 | * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) | |
98 | * with "watchdog counter enable" bit. That bit should be set to make watchdog | |
99 | * counter running. | |
100 | */ | |
101 | #define QUIRK_HAS_WTCLRINT_REG (1 << 0) | |
102 | #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) | |
103 | #define QUIRK_HAS_PMU_RST_STAT (1 << 2) | |
8d9fdf60 | 104 | #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) |
aa220bc6 | 105 | #define QUIRK_HAS_PMU_CNT_EN (1 << 4) |
cffc9a60 DA |
106 | |
107 | /* These quirks require that we have a PMU register map */ | |
cf3fad4e SP |
108 | #define QUIRKS_HAVE_PMUREG \ |
109 | (QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | \ | |
110 | QUIRK_HAS_PMU_AUTO_DISABLE | QUIRK_HAS_PMU_CNT_EN) | |
4f1f653a | 111 | |
86a1e189 | 112 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 113 | static int tmr_margin; |
4f21195d | 114 | static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 | 115 | static int soft_noboot; |
1da177e4 LT |
116 | |
117 | module_param(tmr_margin, int, 0); | |
118 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 119 | module_param(nowayout, bool, 0); |
1da177e4 | 120 | module_param(soft_noboot, int, 0); |
1da177e4 | 121 | |
76550d32 | 122 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
4f21195d | 123 | __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
41dc8b72 AC |
124 | MODULE_PARM_DESC(tmr_atboot, |
125 | "Watchdog is started at boot time if set to 1, default=" | |
4f21195d | 126 | __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT)); |
41dc8b72 AC |
127 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
128 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
08497f22 | 129 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)"); |
1da177e4 | 130 | |
4f1f653a LKA |
131 | /** |
132 | * struct s3c2410_wdt_variant - Per-variant config data | |
133 | * | |
134 | * @disable_reg: Offset in pmureg for the register that disables the watchdog | |
135 | * timer reset functionality. | |
136 | * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog | |
137 | * timer reset functionality. | |
370bc7f5 | 138 | * @mask_reset_inv: If set, mask_reset_reg value will have inverted meaning. |
4f1f653a LKA |
139 | * @mask_bit: Bit number for the watchdog timer in the disable register and the |
140 | * mask reset register. | |
cffc9a60 DA |
141 | * @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
142 | * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog | |
143 | * reset. | |
aa220bc6 SP |
144 | * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. |
145 | * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. | |
4f1f653a LKA |
146 | * @quirks: A bitfield of quirks. |
147 | */ | |
148 | ||
149 | struct s3c2410_wdt_variant { | |
150 | int disable_reg; | |
151 | int mask_reset_reg; | |
370bc7f5 | 152 | bool mask_reset_inv; |
4f1f653a | 153 | int mask_bit; |
cffc9a60 DA |
154 | int rst_stat_reg; |
155 | int rst_stat_bit; | |
aa220bc6 SP |
156 | int cnt_en_reg; |
157 | int cnt_en_bit; | |
4f1f653a LKA |
158 | u32 quirks; |
159 | }; | |
160 | ||
af4ea631 LKA |
161 | struct s3c2410_wdt { |
162 | struct device *dev; | |
e249d01b SP |
163 | struct clk *bus_clk; /* for register interface (PCLK) */ |
164 | struct clk *src_clk; /* for WDT counter */ | |
af4ea631 LKA |
165 | void __iomem *reg_base; |
166 | unsigned int count; | |
167 | spinlock_t lock; | |
168 | unsigned long wtcon_save; | |
169 | unsigned long wtdat_save; | |
170 | struct watchdog_device wdt_device; | |
171 | struct notifier_block freq_transition; | |
58415efe | 172 | const struct s3c2410_wdt_variant *drv_data; |
4f1f653a LKA |
173 | struct regmap *pmureg; |
174 | }; | |
175 | ||
176 | static const struct s3c2410_wdt_variant drv_data_s3c2410 = { | |
177 | .quirks = 0 | |
178 | }; | |
179 | ||
180 | #ifdef CONFIG_OF | |
0b445549 KK |
181 | static const struct s3c2410_wdt_variant drv_data_s3c6410 = { |
182 | .quirks = QUIRK_HAS_WTCLRINT_REG, | |
183 | }; | |
184 | ||
4f1f653a LKA |
185 | static const struct s3c2410_wdt_variant drv_data_exynos5250 = { |
186 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
187 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
188 | .mask_bit = 20, | |
cffc9a60 DA |
189 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
190 | .rst_stat_bit = 20, | |
cf3fad4e SP |
191 | .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ |
192 | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, | |
4f1f653a LKA |
193 | }; |
194 | ||
195 | static const struct s3c2410_wdt_variant drv_data_exynos5420 = { | |
196 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
197 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
198 | .mask_bit = 0, | |
cffc9a60 DA |
199 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
200 | .rst_stat_bit = 9, | |
cf3fad4e SP |
201 | .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ |
202 | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, | |
4f1f653a LKA |
203 | }; |
204 | ||
2b9366b6 NKC |
205 | static const struct s3c2410_wdt_variant drv_data_exynos7 = { |
206 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
207 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
5476b2b7 | 208 | .mask_bit = 23, |
2b9366b6 NKC |
209 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
210 | .rst_stat_bit = 23, /* A57 WDTRESET */ | |
cf3fad4e SP |
211 | .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ |
212 | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, | |
2b9366b6 NKC |
213 | }; |
214 | ||
cd4eadf2 SP |
215 | static const struct s3c2410_wdt_variant drv_data_exynos850_cl0 = { |
216 | .mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN, | |
217 | .mask_bit = 2, | |
218 | .mask_reset_inv = true, | |
219 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, | |
220 | .rst_stat_bit = EXYNOS850_CLUSTER0_WDTRESET_BIT, | |
221 | .cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT, | |
222 | .cnt_en_bit = 7, | |
223 | .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ | |
224 | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, | |
225 | }; | |
226 | ||
227 | static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = { | |
228 | .mask_reset_reg = EXYNOS850_CLUSTER1_NONCPU_INT_EN, | |
229 | .mask_bit = 2, | |
230 | .mask_reset_inv = true, | |
231 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, | |
232 | .rst_stat_bit = EXYNOS850_CLUSTER1_WDTRESET_BIT, | |
233 | .cnt_en_reg = EXYNOS850_CLUSTER1_NONCPU_OUT, | |
234 | .cnt_en_bit = 7, | |
235 | .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ | |
236 | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, | |
237 | }; | |
238 | ||
4f1f653a LKA |
239 | static const struct of_device_id s3c2410_wdt_match[] = { |
240 | { .compatible = "samsung,s3c2410-wdt", | |
241 | .data = &drv_data_s3c2410 }, | |
0b445549 KK |
242 | { .compatible = "samsung,s3c6410-wdt", |
243 | .data = &drv_data_s3c6410 }, | |
4f1f653a LKA |
244 | { .compatible = "samsung,exynos5250-wdt", |
245 | .data = &drv_data_exynos5250 }, | |
246 | { .compatible = "samsung,exynos5420-wdt", | |
247 | .data = &drv_data_exynos5420 }, | |
2b9366b6 NKC |
248 | { .compatible = "samsung,exynos7-wdt", |
249 | .data = &drv_data_exynos7 }, | |
cd4eadf2 SP |
250 | { .compatible = "samsung,exynos850-wdt", |
251 | .data = &drv_data_exynos850_cl0 }, | |
4f1f653a | 252 | {}, |
af4ea631 | 253 | }; |
4f1f653a LKA |
254 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
255 | #endif | |
256 | ||
257 | static const struct platform_device_id s3c2410_wdt_ids[] = { | |
258 | { | |
259 | .name = "s3c2410-wdt", | |
260 | .driver_data = (unsigned long)&drv_data_s3c2410, | |
261 | }, | |
262 | {} | |
263 | }; | |
264 | MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); | |
1da177e4 | 265 | |
1da177e4 LT |
266 | /* functions */ |
267 | ||
e249d01b | 268 | static inline unsigned long s3c2410wdt_get_freq(struct s3c2410_wdt *wdt) |
882dec1f | 269 | { |
e249d01b SP |
270 | return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk); |
271 | } | |
272 | ||
273 | static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt) | |
274 | { | |
275 | const unsigned long freq = s3c2410wdt_get_freq(wdt); | |
882dec1f JMC |
276 | |
277 | return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) | |
278 | / S3C2410_WTCON_MAXDIV); | |
279 | } | |
280 | ||
af4ea631 LKA |
281 | static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
282 | { | |
283 | return container_of(nb, struct s3c2410_wdt, freq_transition); | |
284 | } | |
285 | ||
2bd33bb4 | 286 | static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask) |
4f1f653a | 287 | { |
2bd33bb4 SP |
288 | const u32 mask_val = BIT(wdt->drv_data->mask_bit); |
289 | const u32 val = mask ? mask_val : 0; | |
4f1f653a | 290 | int ret; |
4f1f653a | 291 | |
2bd33bb4 SP |
292 | ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg, |
293 | mask_val, val); | |
294 | if (ret < 0) | |
295 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
4f1f653a | 296 | |
2bd33bb4 SP |
297 | return ret; |
298 | } | |
4f1f653a | 299 | |
2bd33bb4 SP |
300 | static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) |
301 | { | |
302 | const u32 mask_val = BIT(wdt->drv_data->mask_bit); | |
370bc7f5 SP |
303 | const bool val_inv = wdt->drv_data->mask_reset_inv; |
304 | const u32 val = (mask ^ val_inv) ? mask_val : 0; | |
2bd33bb4 | 305 | int ret; |
4f1f653a | 306 | |
2bd33bb4 SP |
307 | ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg, |
308 | mask_val, val); | |
4f1f653a LKA |
309 | if (ret < 0) |
310 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
311 | ||
312 | return ret; | |
313 | } | |
314 | ||
aa220bc6 SP |
315 | static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) |
316 | { | |
317 | const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit); | |
318 | const u32 val = en ? mask_val : 0; | |
319 | int ret; | |
320 | ||
321 | ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg, | |
322 | mask_val, val); | |
323 | if (ret < 0) | |
324 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
325 | ||
326 | return ret; | |
327 | } | |
328 | ||
cf3fad4e | 329 | static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) |
2bd33bb4 SP |
330 | { |
331 | int ret; | |
332 | ||
333 | if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) { | |
cf3fad4e | 334 | ret = s3c2410wdt_disable_wdt_reset(wdt, !en); |
2bd33bb4 SP |
335 | if (ret < 0) |
336 | return ret; | |
337 | } | |
338 | ||
cf3fad4e SP |
339 | if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) { |
340 | ret = s3c2410wdt_mask_wdt_reset(wdt, !en); | |
2bd33bb4 SP |
341 | if (ret < 0) |
342 | return ret; | |
343 | } | |
344 | ||
aa220bc6 | 345 | if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) { |
cf3fad4e | 346 | ret = s3c2410wdt_enable_counter(wdt, en); |
aa220bc6 SP |
347 | if (ret < 0) |
348 | return ret; | |
349 | } | |
350 | ||
2bd33bb4 SP |
351 | return 0; |
352 | } | |
353 | ||
25dc46e3 | 354 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 355 | { |
af4ea631 LKA |
356 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
357 | ||
358 | spin_lock(&wdt->lock); | |
359 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
360 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
361 | |
362 | return 0; | |
1da177e4 LT |
363 | } |
364 | ||
af4ea631 | 365 | static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
41dc8b72 AC |
366 | { |
367 | unsigned long wtcon; | |
368 | ||
af4ea631 | 369 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
41dc8b72 | 370 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
af4ea631 | 371 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
41dc8b72 AC |
372 | } |
373 | ||
25dc46e3 | 374 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 | 375 | { |
af4ea631 LKA |
376 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
377 | ||
378 | spin_lock(&wdt->lock); | |
379 | __s3c2410wdt_stop(wdt); | |
380 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
381 | |
382 | return 0; | |
1da177e4 LT |
383 | } |
384 | ||
25dc46e3 | 385 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
386 | { |
387 | unsigned long wtcon; | |
af4ea631 | 388 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
1da177e4 | 389 | |
af4ea631 | 390 | spin_lock(&wdt->lock); |
41dc8b72 | 391 | |
af4ea631 | 392 | __s3c2410wdt_stop(wdt); |
1da177e4 | 393 | |
af4ea631 | 394 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
395 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
396 | ||
397 | if (soft_noboot) { | |
398 | wtcon |= S3C2410_WTCON_INTEN; | |
399 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
400 | } else { | |
401 | wtcon &= ~S3C2410_WTCON_INTEN; | |
402 | wtcon |= S3C2410_WTCON_RSTEN; | |
403 | } | |
404 | ||
456f53d6 KK |
405 | dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n", |
406 | wdt->count, wtcon); | |
1da177e4 | 407 | |
af4ea631 LKA |
408 | writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
409 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
410 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
411 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
412 | |
413 | return 0; | |
1da177e4 LT |
414 | } |
415 | ||
af4ea631 | 416 | static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
e02f838e | 417 | { |
af4ea631 | 418 | return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
e02f838e BD |
419 | } |
420 | ||
08497f22 KK |
421 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, |
422 | unsigned int timeout) | |
1da177e4 | 423 | { |
af4ea631 | 424 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
e249d01b | 425 | unsigned long freq = s3c2410wdt_get_freq(wdt); |
1da177e4 LT |
426 | unsigned int count; |
427 | unsigned int divisor = 1; | |
428 | unsigned long wtcon; | |
429 | ||
430 | if (timeout < 1) | |
431 | return -EINVAL; | |
432 | ||
17862440 | 433 | freq = DIV_ROUND_UP(freq, 128); |
1da177e4 LT |
434 | count = timeout * freq; |
435 | ||
456f53d6 KK |
436 | dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n", |
437 | count, timeout, freq); | |
1da177e4 LT |
438 | |
439 | /* if the count is bigger than the watchdog register, | |
440 | then work out what we need to do (and if) we can | |
441 | actually make this value | |
442 | */ | |
443 | ||
444 | if (count >= 0x10000) { | |
17862440 | 445 | divisor = DIV_ROUND_UP(count, 0xffff); |
1da177e4 | 446 | |
17862440 | 447 | if (divisor > 0x100) { |
af4ea631 | 448 | dev_err(wdt->dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
449 | return -EINVAL; |
450 | } | |
451 | } | |
452 | ||
456f53d6 KK |
453 | dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n", |
454 | timeout, divisor, count, DIV_ROUND_UP(count, divisor)); | |
1da177e4 | 455 | |
17862440 | 456 | count = DIV_ROUND_UP(count, divisor); |
af4ea631 | 457 | wdt->count = count; |
1da177e4 LT |
458 | |
459 | /* update the pre-scaler */ | |
af4ea631 | 460 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
461 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
462 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
463 | ||
af4ea631 LKA |
464 | writel(count, wdt->reg_base + S3C2410_WTDAT); |
465 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
1da177e4 | 466 | |
5f2430f5 | 467 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 468 | |
1da177e4 LT |
469 | return 0; |
470 | } | |
471 | ||
4d8b229d GR |
472 | static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, |
473 | void *data) | |
c71f5cd2 DR |
474 | { |
475 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); | |
476 | void __iomem *wdt_base = wdt->reg_base; | |
477 | ||
478 | /* disable watchdog, to be safe */ | |
479 | writel(0, wdt_base + S3C2410_WTCON); | |
480 | ||
481 | /* put initial values into count and data */ | |
482 | writel(0x80, wdt_base + S3C2410_WTCNT); | |
483 | writel(0x80, wdt_base + S3C2410_WTDAT); | |
484 | ||
485 | /* set the watchdog to go and reset... */ | |
486 | writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | | |
487 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), | |
488 | wdt_base + S3C2410_WTCON); | |
489 | ||
490 | /* wait for reset to assert... */ | |
491 | mdelay(500); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
a77dba7e | 496 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 497 | |
41dc8b72 | 498 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
499 | .options = OPTIONS, |
500 | .firmware_version = 0, | |
501 | .identity = "S3C2410 Watchdog", | |
502 | }; | |
503 | ||
b893e344 | 504 | static const struct watchdog_ops s3c2410wdt_ops = { |
25dc46e3 WS |
505 | .owner = THIS_MODULE, |
506 | .start = s3c2410wdt_start, | |
507 | .stop = s3c2410wdt_stop, | |
508 | .ping = s3c2410wdt_keepalive, | |
509 | .set_timeout = s3c2410wdt_set_heartbeat, | |
c71f5cd2 | 510 | .restart = s3c2410wdt_restart, |
1da177e4 LT |
511 | }; |
512 | ||
58415efe | 513 | static const struct watchdog_device s3c2410_wdd = { |
25dc46e3 WS |
514 | .info = &s3c2410_wdt_ident, |
515 | .ops = &s3c2410wdt_ops, | |
4f21195d | 516 | .timeout = S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
517 | }; |
518 | ||
1da177e4 LT |
519 | /* interrupt handler code */ |
520 | ||
7d12e780 | 521 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 522 | { |
af4ea631 | 523 | struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
1da177e4 | 524 | |
af4ea631 LKA |
525 | dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
526 | ||
527 | s3c2410wdt_keepalive(&wdt->wdt_device); | |
0b445549 KK |
528 | |
529 | if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG) | |
530 | writel(0x1, wdt->reg_base + S3C2410_WTCLRINT); | |
531 | ||
1da177e4 LT |
532 | return IRQ_HANDLED; |
533 | } | |
e02f838e | 534 | |
0f1dd98d | 535 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
e02f838e BD |
536 | |
537 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
538 | unsigned long val, void *data) | |
539 | { | |
540 | int ret; | |
af4ea631 | 541 | struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
e02f838e | 542 | |
af4ea631 | 543 | if (!s3c2410wdt_is_running(wdt)) |
e02f838e BD |
544 | goto done; |
545 | ||
546 | if (val == CPUFREQ_PRECHANGE) { | |
547 | /* To ensure that over the change we don't cause the | |
548 | * watchdog to trigger, we perform an keep-alive if | |
549 | * the watchdog is running. | |
550 | */ | |
551 | ||
af4ea631 | 552 | s3c2410wdt_keepalive(&wdt->wdt_device); |
e02f838e | 553 | } else if (val == CPUFREQ_POSTCHANGE) { |
af4ea631 | 554 | s3c2410wdt_stop(&wdt->wdt_device); |
e02f838e | 555 | |
af4ea631 LKA |
556 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
557 | wdt->wdt_device.timeout); | |
e02f838e BD |
558 | |
559 | if (ret >= 0) | |
af4ea631 | 560 | s3c2410wdt_start(&wdt->wdt_device); |
e02f838e BD |
561 | else |
562 | goto err; | |
563 | } | |
564 | ||
565 | done: | |
566 | return 0; | |
567 | ||
568 | err: | |
af4ea631 LKA |
569 | dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
570 | wdt->wdt_device.timeout); | |
e02f838e BD |
571 | return ret; |
572 | } | |
573 | ||
af4ea631 | 574 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
e02f838e | 575 | { |
af4ea631 LKA |
576 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
577 | ||
578 | return cpufreq_register_notifier(&wdt->freq_transition, | |
e02f838e BD |
579 | CPUFREQ_TRANSITION_NOTIFIER); |
580 | } | |
581 | ||
af4ea631 | 582 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e | 583 | { |
af4ea631 LKA |
584 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
585 | ||
586 | cpufreq_unregister_notifier(&wdt->freq_transition, | |
e02f838e BD |
587 | CPUFREQ_TRANSITION_NOTIFIER); |
588 | } | |
589 | ||
590 | #else | |
af4ea631 LKA |
591 | |
592 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) | |
e02f838e BD |
593 | { |
594 | return 0; | |
595 | } | |
596 | ||
af4ea631 | 597 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e BD |
598 | { |
599 | } | |
600 | #endif | |
601 | ||
cffc9a60 DA |
602 | static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
603 | { | |
604 | unsigned int rst_stat; | |
605 | int ret; | |
606 | ||
cf3fad4e | 607 | if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT)) |
cffc9a60 DA |
608 | return 0; |
609 | ||
610 | ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); | |
611 | if (ret) | |
612 | dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); | |
613 | else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) | |
614 | return WDIOF_CARDRESET; | |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
58415efe | 619 | static inline const struct s3c2410_wdt_variant * |
e3a60ead | 620 | s3c2410_get_wdt_drv_data(struct platform_device *pdev) |
4f1f653a | 621 | { |
a9a02c46 | 622 | const struct s3c2410_wdt_variant *variant; |
cd4eadf2 | 623 | struct device *dev = &pdev->dev; |
a9a02c46 | 624 | |
cd4eadf2 | 625 | variant = of_device_get_match_data(dev); |
a9a02c46 KK |
626 | if (!variant) { |
627 | /* Device matched by platform_device_id */ | |
628 | variant = (struct s3c2410_wdt_variant *) | |
629 | platform_get_device_id(pdev)->driver_data; | |
4f1f653a | 630 | } |
a9a02c46 | 631 | |
cd4eadf2 SP |
632 | #ifdef CONFIG_OF |
633 | /* Choose Exynos850 driver data w.r.t. cluster index */ | |
634 | if (variant == &drv_data_exynos850_cl0) { | |
635 | u32 index; | |
636 | int err; | |
637 | ||
638 | err = of_property_read_u32(dev->of_node, | |
639 | "samsung,cluster-index", &index); | |
640 | if (err) { | |
641 | dev_err(dev, "failed to get cluster index\n"); | |
642 | return NULL; | |
643 | } | |
644 | ||
645 | switch (index) { | |
646 | case 0: | |
647 | return &drv_data_exynos850_cl0; | |
648 | case 1: | |
649 | return &drv_data_exynos850_cl1; | |
650 | default: | |
651 | dev_err(dev, "wrong cluster index: %u\n", index); | |
652 | return NULL; | |
653 | } | |
654 | } | |
655 | #endif | |
656 | ||
a9a02c46 | 657 | return variant; |
4f1f653a LKA |
658 | } |
659 | ||
2d991a16 | 660 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 661 | { |
08497f22 | 662 | struct device *dev = &pdev->dev; |
af4ea631 | 663 | struct s3c2410_wdt *wdt; |
46b814d6 | 664 | unsigned int wtcon; |
a51f5896 | 665 | int wdt_irq; |
1da177e4 | 666 | int ret; |
1da177e4 | 667 | |
af4ea631 LKA |
668 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
669 | if (!wdt) | |
670 | return -ENOMEM; | |
671 | ||
08497f22 | 672 | wdt->dev = dev; |
af4ea631 LKA |
673 | spin_lock_init(&wdt->lock); |
674 | wdt->wdt_device = s3c2410_wdd; | |
1da177e4 | 675 | |
e3a60ead | 676 | wdt->drv_data = s3c2410_get_wdt_drv_data(pdev); |
cd4eadf2 SP |
677 | if (!wdt->drv_data) |
678 | return -EINVAL; | |
679 | ||
cffc9a60 | 680 | if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
4f1f653a LKA |
681 | wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
682 | "samsung,syscon-phandle"); | |
683 | if (IS_ERR(wdt->pmureg)) { | |
684 | dev_err(dev, "syscon regmap lookup failed.\n"); | |
685 | return PTR_ERR(wdt->pmureg); | |
686 | } | |
687 | } | |
688 | ||
a51f5896 LP |
689 | wdt_irq = platform_get_irq(pdev, 0); |
690 | if (wdt_irq < 0) | |
691 | return wdt_irq; | |
78d3e00b MH |
692 | |
693 | /* get the memory region for the watchdog timer */ | |
0f0a6a28 | 694 | wdt->reg_base = devm_platform_ioremap_resource(pdev, 0); |
1a47cda0 SP |
695 | if (IS_ERR(wdt->reg_base)) |
696 | return PTR_ERR(wdt->reg_base); | |
1da177e4 | 697 | |
e249d01b SP |
698 | wdt->bus_clk = devm_clk_get(dev, "watchdog"); |
699 | if (IS_ERR(wdt->bus_clk)) { | |
700 | dev_err(dev, "failed to find bus clock\n"); | |
1a47cda0 | 701 | return PTR_ERR(wdt->bus_clk); |
1da177e4 LT |
702 | } |
703 | ||
e249d01b | 704 | ret = clk_prepare_enable(wdt->bus_clk); |
01b6af91 | 705 | if (ret < 0) { |
e249d01b | 706 | dev_err(dev, "failed to enable bus clock\n"); |
01b6af91 SK |
707 | return ret; |
708 | } | |
1da177e4 | 709 | |
e249d01b SP |
710 | /* |
711 | * "watchdog_src" clock is optional; if it's not present -- just skip it | |
712 | * and use "watchdog" clock as both bus and source clock. | |
713 | */ | |
f7bcb023 SP |
714 | wdt->src_clk = devm_clk_get_optional(dev, "watchdog_src"); |
715 | if (IS_ERR(wdt->src_clk)) { | |
716 | dev_err_probe(dev, PTR_ERR(wdt->src_clk), | |
717 | "failed to get source clock\n"); | |
718 | ret = PTR_ERR(wdt->src_clk); | |
719 | goto err_bus_clk; | |
720 | } | |
721 | ||
722 | ret = clk_prepare_enable(wdt->src_clk); | |
723 | if (ret) { | |
724 | dev_err(dev, "failed to enable source clock\n"); | |
725 | goto err_bus_clk; | |
e249d01b SP |
726 | } |
727 | ||
882dec1f | 728 | wdt->wdt_device.min_timeout = 1; |
e249d01b | 729 | wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt); |
882dec1f | 730 | |
af4ea631 | 731 | ret = s3c2410wdt_cpufreq_register(wdt); |
78d3e00b | 732 | if (ret < 0) { |
3828924a | 733 | dev_err(dev, "failed to register cpufreq\n"); |
e249d01b | 734 | goto err_src_clk; |
e02f838e BD |
735 | } |
736 | ||
af4ea631 LKA |
737 | watchdog_set_drvdata(&wdt->wdt_device, wdt); |
738 | ||
1da177e4 LT |
739 | /* see if we can actually set the requested timer margin, and if |
740 | * not, try the default value */ | |
741 | ||
08497f22 | 742 | watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev); |
af4ea631 LKA |
743 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
744 | wdt->wdt_device.timeout); | |
745 | if (ret) { | |
f197d475 SP |
746 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
747 | S3C2410_WATCHDOG_DEFAULT_TIME); | |
748 | if (ret == 0) { | |
749 | dev_warn(dev, "tmr_margin value out of range, default %d used\n", | |
08497f22 | 750 | S3C2410_WATCHDOG_DEFAULT_TIME); |
f197d475 SP |
751 | } else { |
752 | dev_err(dev, "failed to use default timeout\n"); | |
753 | goto err_cpufreq; | |
754 | } | |
1da177e4 LT |
755 | } |
756 | ||
a51f5896 LP |
757 | ret = devm_request_irq(dev, wdt_irq, s3c2410wdt_irq, 0, |
758 | pdev->name, pdev); | |
78d3e00b MH |
759 | if (ret != 0) { |
760 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
761 | goto err_cpufreq; | |
762 | } | |
763 | ||
af4ea631 | 764 | watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
c71f5cd2 | 765 | watchdog_set_restart_priority(&wdt->wdt_device, 128); |
ff0b3cd4 | 766 | |
cffc9a60 | 767 | wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
08497f22 | 768 | wdt->wdt_device.parent = dev; |
cffc9a60 | 769 | |
a90102e3 SP |
770 | /* |
771 | * If "tmr_atboot" param is non-zero, start the watchdog right now. Also | |
772 | * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. | |
773 | * | |
774 | * If we're not enabling the watchdog, then ensure it is disabled if it | |
775 | * has been left running from the bootloader or other source. | |
776 | */ | |
777 | if (tmr_atboot) { | |
778 | dev_info(dev, "starting watchdog timer\n"); | |
779 | s3c2410wdt_start(&wdt->wdt_device); | |
780 | set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status); | |
781 | } else { | |
782 | s3c2410wdt_stop(&wdt->wdt_device); | |
783 | } | |
784 | ||
af4ea631 | 785 | ret = watchdog_register_device(&wdt->wdt_device); |
386f465a | 786 | if (ret) |
04ecc7dc | 787 | goto err_cpufreq; |
1da177e4 | 788 | |
cf3fad4e | 789 | ret = s3c2410wdt_enable(wdt, true); |
4f1f653a LKA |
790 | if (ret < 0) |
791 | goto err_unregister; | |
792 | ||
af4ea631 LKA |
793 | platform_set_drvdata(pdev, wdt); |
794 | ||
46b814d6 BD |
795 | /* print out a statement of readiness */ |
796 | ||
af4ea631 | 797 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
46b814d6 | 798 | |
e8ef92b8 | 799 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 800 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
801 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
802 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 803 | |
1da177e4 | 804 | return 0; |
0b6dd8a6 | 805 | |
4f1f653a LKA |
806 | err_unregister: |
807 | watchdog_unregister_device(&wdt->wdt_device); | |
808 | ||
e02f838e | 809 | err_cpufreq: |
af4ea631 | 810 | s3c2410wdt_cpufreq_deregister(wdt); |
e02f838e | 811 | |
e249d01b SP |
812 | err_src_clk: |
813 | clk_disable_unprepare(wdt->src_clk); | |
814 | ||
815 | err_bus_clk: | |
816 | clk_disable_unprepare(wdt->bus_clk); | |
0b6dd8a6 | 817 | |
0b6dd8a6 | 818 | return ret; |
1da177e4 LT |
819 | } |
820 | ||
4b12b896 | 821 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 822 | { |
4f1f653a | 823 | int ret; |
af4ea631 LKA |
824 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
825 | ||
cf3fad4e | 826 | ret = s3c2410wdt_enable(wdt, false); |
4f1f653a LKA |
827 | if (ret < 0) |
828 | return ret; | |
829 | ||
af4ea631 | 830 | watchdog_unregister_device(&wdt->wdt_device); |
1da177e4 | 831 | |
af4ea631 | 832 | s3c2410wdt_cpufreq_deregister(wdt); |
1da177e4 | 833 | |
e249d01b SP |
834 | clk_disable_unprepare(wdt->src_clk); |
835 | clk_disable_unprepare(wdt->bus_clk); | |
1da177e4 | 836 | |
1da177e4 LT |
837 | return 0; |
838 | } | |
839 | ||
3ae5eaec | 840 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 841 | { |
af4ea631 LKA |
842 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
843 | ||
cf3fad4e | 844 | s3c2410wdt_enable(wdt, false); |
af4ea631 | 845 | s3c2410wdt_stop(&wdt->wdt_device); |
94f1e9f3 BD |
846 | } |
847 | ||
0183984c | 848 | #ifdef CONFIG_PM_SLEEP |
af4bb822 | 849 | |
0183984c | 850 | static int s3c2410wdt_suspend(struct device *dev) |
af4bb822 | 851 | { |
4f1f653a | 852 | int ret; |
af4ea631 LKA |
853 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
854 | ||
9480e307 | 855 | /* Save watchdog state, and turn it off. */ |
af4ea631 LKA |
856 | wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
857 | wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); | |
af4bb822 | 858 | |
cf3fad4e | 859 | ret = s3c2410wdt_enable(wdt, false); |
4f1f653a LKA |
860 | if (ret < 0) |
861 | return ret; | |
862 | ||
9480e307 | 863 | /* Note that WTCNT doesn't need to be saved. */ |
af4ea631 | 864 | s3c2410wdt_stop(&wdt->wdt_device); |
af4bb822 BD |
865 | |
866 | return 0; | |
867 | } | |
868 | ||
0183984c | 869 | static int s3c2410wdt_resume(struct device *dev) |
af4bb822 | 870 | { |
4f1f653a | 871 | int ret; |
af4ea631 | 872 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
af4bb822 | 873 | |
af4ea631 LKA |
874 | /* Restore watchdog state. */ |
875 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); | |
876 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ | |
877 | writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); | |
af4bb822 | 878 | |
cf3fad4e | 879 | ret = s3c2410wdt_enable(wdt, true); |
4f1f653a LKA |
880 | if (ret < 0) |
881 | return ret; | |
882 | ||
0183984c | 883 | dev_info(dev, "watchdog %sabled\n", |
af4ea631 | 884 | (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
af4bb822 BD |
885 | |
886 | return 0; | |
887 | } | |
0183984c | 888 | #endif |
af4bb822 | 889 | |
0183984c JH |
890 | static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
891 | s3c2410wdt_resume); | |
af4bb822 | 892 | |
3ae5eaec | 893 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 894 | .probe = s3c2410wdt_probe, |
82268714 | 895 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 896 | .shutdown = s3c2410wdt_shutdown, |
4f1f653a | 897 | .id_table = s3c2410_wdt_ids, |
3ae5eaec | 898 | .driver = { |
3ae5eaec | 899 | .name = "s3c2410-wdt", |
0183984c | 900 | .pm = &s3c2410wdt_pm_ops, |
3016a552 | 901 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 902 | }, |
1da177e4 LT |
903 | }; |
904 | ||
6b761b29 | 905 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 906 | |
08497f22 | 907 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>"); |
1da177e4 LT |
908 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
909 | MODULE_LICENSE("GPL"); |