Merge branch 'x86-fpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / watchdog / s3c2410_wdt.c
CommitLineData
1da177e4
LT
1/* linux/drivers/char/watchdog/s3c2410_wdt.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Watchdog Timer Support
7 *
8 * Based on, softdog.c by Alan Cox,
29fa0586 9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4
LT
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1da177e4
LT
24*/
25
26#include <linux/module.h>
27#include <linux/moduleparam.h>
1da177e4
LT
28#include <linux/types.h>
29#include <linux/timer.h>
25dc46e3 30#include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */
1da177e4 31#include <linux/watchdog.h>
1da177e4 32#include <linux/init.h>
d052d1be 33#include <linux/platform_device.h>
1da177e4 34#include <linux/interrupt.h>
f8ce2547 35#include <linux/clk.h>
41dc8b72
AC
36#include <linux/uaccess.h>
37#include <linux/io.h>
e02f838e 38#include <linux/cpufreq.h>
5a0e3ad6 39#include <linux/slab.h>
25dc46e3 40#include <linux/err.h>
1da177e4 41
a09e64fb 42#include <mach/map.h>
1da177e4 43
b430708a
BD
44#undef S3C_VA_WATCHDOG
45#define S3C_VA_WATCHDOG (0)
1da177e4 46
180ee700 47#include <plat/regs-watchdog.h>
1da177e4
LT
48
49#define PFX "s3c2410-wdt: "
50
51#define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
52#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
53
25ff3780 54static int nowayout = WATCHDOG_NOWAYOUT;
1da177e4
LT
55static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
56static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
41dc8b72
AC
57static int soft_noboot;
58static int debug;
1da177e4
LT
59
60module_param(tmr_margin, int, 0);
61module_param(tmr_atboot, int, 0);
62module_param(nowayout, int, 0);
63module_param(soft_noboot, int, 0);
64module_param(debug, int, 0);
65
76550d32 66MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
41dc8b72
AC
67 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
68MODULE_PARM_DESC(tmr_atboot,
69 "Watchdog is started at boot time if set to 1, default="
70 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
71MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
72 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
a77dba7e 73MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
76550d32
RD
74 "0 to reboot (default 0)");
75MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
1da177e4 76
e8ef92b8 77static struct device *wdt_dev; /* platform device attached to */
1da177e4
LT
78static struct resource *wdt_mem;
79static struct resource *wdt_irq;
80static struct clk *wdt_clock;
81static void __iomem *wdt_base;
82static unsigned int wdt_count;
41dc8b72 83static DEFINE_SPINLOCK(wdt_lock);
1da177e4
LT
84
85/* watchdog control routines */
86
87#define DBG(msg...) do { \
88 if (debug) \
89 printk(KERN_INFO msg); \
41dc8b72 90 } while (0)
1da177e4
LT
91
92/* functions */
93
25dc46e3 94static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
1da177e4 95{
41dc8b72 96 spin_lock(&wdt_lock);
1da177e4 97 writel(wdt_count, wdt_base + S3C2410_WTCNT);
41dc8b72 98 spin_unlock(&wdt_lock);
25dc46e3
WS
99
100 return 0;
1da177e4
LT
101}
102
41dc8b72
AC
103static void __s3c2410wdt_stop(void)
104{
105 unsigned long wtcon;
106
107 wtcon = readl(wdt_base + S3C2410_WTCON);
108 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
109 writel(wtcon, wdt_base + S3C2410_WTCON);
110}
111
25dc46e3 112static int s3c2410wdt_stop(struct watchdog_device *wdd)
41dc8b72
AC
113{
114 spin_lock(&wdt_lock);
115 __s3c2410wdt_stop();
116 spin_unlock(&wdt_lock);
25dc46e3
WS
117
118 return 0;
1da177e4
LT
119}
120
25dc46e3 121static int s3c2410wdt_start(struct watchdog_device *wdd)
1da177e4
LT
122{
123 unsigned long wtcon;
124
41dc8b72
AC
125 spin_lock(&wdt_lock);
126
127 __s3c2410wdt_stop();
1da177e4
LT
128
129 wtcon = readl(wdt_base + S3C2410_WTCON);
130 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
131
132 if (soft_noboot) {
133 wtcon |= S3C2410_WTCON_INTEN;
134 wtcon &= ~S3C2410_WTCON_RSTEN;
135 } else {
136 wtcon &= ~S3C2410_WTCON_INTEN;
137 wtcon |= S3C2410_WTCON_RSTEN;
138 }
139
140 DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
fa9363c5 141 __func__, wdt_count, wtcon);
1da177e4
LT
142
143 writel(wdt_count, wdt_base + S3C2410_WTDAT);
144 writel(wdt_count, wdt_base + S3C2410_WTCNT);
145 writel(wtcon, wdt_base + S3C2410_WTCON);
41dc8b72 146 spin_unlock(&wdt_lock);
25dc46e3
WS
147
148 return 0;
1da177e4
LT
149}
150
e02f838e
BD
151static inline int s3c2410wdt_is_running(void)
152{
153 return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
154}
155
25dc46e3 156static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
1da177e4 157{
e02f838e 158 unsigned long freq = clk_get_rate(wdt_clock);
1da177e4
LT
159 unsigned int count;
160 unsigned int divisor = 1;
161 unsigned long wtcon;
162
163 if (timeout < 1)
164 return -EINVAL;
165
166 freq /= 128;
167 count = timeout * freq;
168
e02f838e 169 DBG("%s: count=%d, timeout=%d, freq=%lu\n",
fa9363c5 170 __func__, count, timeout, freq);
1da177e4
LT
171
172 /* if the count is bigger than the watchdog register,
173 then work out what we need to do (and if) we can
174 actually make this value
175 */
176
177 if (count >= 0x10000) {
178 for (divisor = 1; divisor <= 0x100; divisor++) {
179 if ((count / divisor) < 0x10000)
180 break;
181 }
182
183 if ((count / divisor) >= 0x10000) {
e8ef92b8 184 dev_err(wdt_dev, "timeout %d too big\n", timeout);
1da177e4
LT
185 return -EINVAL;
186 }
187 }
188
1da177e4 189 DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
fa9363c5 190 __func__, timeout, divisor, count, count/divisor);
1da177e4
LT
191
192 count /= divisor;
193 wdt_count = count;
194
195 /* update the pre-scaler */
196 wtcon = readl(wdt_base + S3C2410_WTCON);
197 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
198 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
199
200 writel(count, wdt_base + S3C2410_WTDAT);
201 writel(wtcon, wdt_base + S3C2410_WTCON);
202
203 return 0;
204}
205
a77dba7e 206#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
1da177e4 207
41dc8b72 208static const struct watchdog_info s3c2410_wdt_ident = {
1da177e4
LT
209 .options = OPTIONS,
210 .firmware_version = 0,
211 .identity = "S3C2410 Watchdog",
212};
213
25dc46e3
WS
214static struct watchdog_ops s3c2410wdt_ops = {
215 .owner = THIS_MODULE,
216 .start = s3c2410wdt_start,
217 .stop = s3c2410wdt_stop,
218 .ping = s3c2410wdt_keepalive,
219 .set_timeout = s3c2410wdt_set_heartbeat,
1da177e4
LT
220};
221
25dc46e3
WS
222static struct watchdog_device s3c2410_wdd = {
223 .info = &s3c2410_wdt_ident,
224 .ops = &s3c2410wdt_ops,
1da177e4
LT
225};
226
1da177e4
LT
227/* interrupt handler code */
228
7d12e780 229static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
1da177e4 230{
e8ef92b8 231 dev_info(wdt_dev, "watchdog timer expired (irq)\n");
1da177e4 232
25dc46e3 233 s3c2410wdt_keepalive(&s3c2410_wdd);
1da177e4
LT
234 return IRQ_HANDLED;
235}
e02f838e
BD
236
237
238#ifdef CONFIG_CPU_FREQ
239
240static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
241 unsigned long val, void *data)
242{
243 int ret;
244
245 if (!s3c2410wdt_is_running())
246 goto done;
247
248 if (val == CPUFREQ_PRECHANGE) {
249 /* To ensure that over the change we don't cause the
250 * watchdog to trigger, we perform an keep-alive if
251 * the watchdog is running.
252 */
253
25dc46e3 254 s3c2410wdt_keepalive(&s3c2410_wdd);
e02f838e 255 } else if (val == CPUFREQ_POSTCHANGE) {
25dc46e3 256 s3c2410wdt_stop(&s3c2410_wdd);
e02f838e 257
25dc46e3 258 ret = s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout);
e02f838e
BD
259
260 if (ret >= 0)
25dc46e3 261 s3c2410wdt_start(&s3c2410_wdd);
e02f838e
BD
262 else
263 goto err;
264 }
265
266done:
267 return 0;
268
269 err:
25dc46e3
WS
270 dev_err(wdt_dev, "cannot set new value for timeout %d\n",
271 s3c2410_wdd.timeout);
e02f838e
BD
272 return ret;
273}
274
275static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
276 .notifier_call = s3c2410wdt_cpufreq_transition,
277};
278
279static inline int s3c2410wdt_cpufreq_register(void)
280{
281 return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
282 CPUFREQ_TRANSITION_NOTIFIER);
283}
284
285static inline void s3c2410wdt_cpufreq_deregister(void)
286{
287 cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
288 CPUFREQ_TRANSITION_NOTIFIER);
289}
290
291#else
292static inline int s3c2410wdt_cpufreq_register(void)
293{
294 return 0;
295}
296
297static inline void s3c2410wdt_cpufreq_deregister(void)
298{
299}
300#endif
301
a77dba7e 302static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
1da177e4 303{
e8ef92b8 304 struct device *dev;
46b814d6 305 unsigned int wtcon;
1da177e4
LT
306 int started = 0;
307 int ret;
308 int size;
309
fa9363c5 310 DBG("%s: probe=%p\n", __func__, pdev);
1da177e4 311
e8ef92b8
BD
312 dev = &pdev->dev;
313 wdt_dev = &pdev->dev;
314
f72401e9
JL
315 wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
316 if (wdt_mem == NULL) {
e8ef92b8 317 dev_err(dev, "no memory resource specified\n");
1da177e4
LT
318 return -ENOENT;
319 }
320
78d3e00b
MH
321 wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
322 if (wdt_irq == NULL) {
323 dev_err(dev, "no irq resource specified\n");
324 ret = -ENOENT;
325 goto err;
326 }
327
328 /* get the memory region for the watchdog timer */
329
f72401e9
JL
330 size = resource_size(wdt_mem);
331 if (!request_mem_region(wdt_mem->start, size, pdev->name)) {
e8ef92b8 332 dev_err(dev, "failed to get memory region\n");
78d3e00b
MH
333 ret = -EBUSY;
334 goto err;
1da177e4
LT
335 }
336
f72401e9 337 wdt_base = ioremap(wdt_mem->start, size);
b4253f8f 338 if (wdt_base == NULL) {
e8ef92b8 339 dev_err(dev, "failed to ioremap() region\n");
0b6dd8a6
BD
340 ret = -EINVAL;
341 goto err_req;
1da177e4
LT
342 }
343
344 DBG("probe: mapped wdt_base=%p\n", wdt_base);
345
3ae5eaec 346 wdt_clock = clk_get(&pdev->dev, "watchdog");
9cd44619 347 if (IS_ERR(wdt_clock)) {
e8ef92b8 348 dev_err(dev, "failed to find watchdog clock source\n");
9cd44619 349 ret = PTR_ERR(wdt_clock);
78d3e00b 350 goto err_map;
1da177e4
LT
351 }
352
1da177e4
LT
353 clk_enable(wdt_clock);
354
78d3e00b
MH
355 ret = s3c2410wdt_cpufreq_register();
356 if (ret < 0) {
e02f838e
BD
357 printk(KERN_ERR PFX "failed to register cpufreq\n");
358 goto err_clk;
359 }
360
1da177e4
LT
361 /* see if we can actually set the requested timer margin, and if
362 * not, try the default value */
363
25dc46e3
WS
364 if (s3c2410wdt_set_heartbeat(&s3c2410_wdd, tmr_margin)) {
365 started = s3c2410wdt_set_heartbeat(&s3c2410_wdd,
41dc8b72 366 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
1da177e4 367
41dc8b72
AC
368 if (started == 0)
369 dev_info(dev,
370 "tmr_margin value out of range, default %d used\n",
1da177e4 371 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
41dc8b72 372 else
a77dba7e
WVS
373 dev_info(dev, "default timer value is out of range, "
374 "cannot start\n");
1da177e4
LT
375 }
376
78d3e00b
MH
377 ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
378 if (ret != 0) {
379 dev_err(dev, "failed to install irq (%d)\n", ret);
380 goto err_cpufreq;
381 }
382
ff0b3cd4
WVS
383 watchdog_set_nowayout(&s3c2410_wdd, nowayout);
384
25dc46e3 385 ret = watchdog_register_device(&s3c2410_wdd);
1da177e4 386 if (ret) {
25dc46e3 387 dev_err(dev, "cannot register watchdog (%d)\n", ret);
78d3e00b 388 goto err_irq;
1da177e4
LT
389 }
390
391 if (tmr_atboot && started == 0) {
e8ef92b8 392 dev_info(dev, "starting watchdog timer\n");
25dc46e3 393 s3c2410wdt_start(&s3c2410_wdd);
655516c8
BD
394 } else if (!tmr_atboot) {
395 /* if we're not enabling the watchdog, then ensure it is
396 * disabled if it has been left running from the bootloader
397 * or other source */
398
25dc46e3 399 s3c2410wdt_stop(&s3c2410_wdd);
1da177e4
LT
400 }
401
46b814d6
BD
402 /* print out a statement of readiness */
403
404 wtcon = readl(wdt_base + S3C2410_WTCON);
405
e8ef92b8 406 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
46b814d6 407 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
20403e84
DA
408 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
409 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
41dc8b72 410
1da177e4 411 return 0;
0b6dd8a6 412
78d3e00b
MH
413 err_irq:
414 free_irq(wdt_irq->start, pdev);
415
e02f838e
BD
416 err_cpufreq:
417 s3c2410wdt_cpufreq_deregister();
418
0b6dd8a6
BD
419 err_clk:
420 clk_disable(wdt_clock);
421 clk_put(wdt_clock);
78d3e00b 422 wdt_clock = NULL;
0b6dd8a6
BD
423
424 err_map:
425 iounmap(wdt_base);
426
427 err_req:
f72401e9 428 release_mem_region(wdt_mem->start, size);
0b6dd8a6 429
78d3e00b
MH
430 err:
431 wdt_irq = NULL;
432 wdt_mem = NULL;
0b6dd8a6 433 return ret;
1da177e4
LT
434}
435
a77dba7e 436static int __devexit s3c2410wdt_remove(struct platform_device *dev)
1da177e4 437{
25dc46e3 438 watchdog_unregister_device(&s3c2410_wdd);
1da177e4 439
78d3e00b
MH
440 free_irq(wdt_irq->start, dev);
441
9a372563 442 s3c2410wdt_cpufreq_deregister();
1da177e4 443
0b6dd8a6
BD
444 clk_disable(wdt_clock);
445 clk_put(wdt_clock);
446 wdt_clock = NULL;
1da177e4 447
e34477e9 448 iounmap(wdt_base);
9a372563 449
f72401e9 450 release_mem_region(wdt_mem->start, resource_size(wdt_mem));
78d3e00b 451 wdt_irq = NULL;
9a372563 452 wdt_mem = NULL;
1da177e4
LT
453 return 0;
454}
455
3ae5eaec 456static void s3c2410wdt_shutdown(struct platform_device *dev)
94f1e9f3 457{
25dc46e3 458 s3c2410wdt_stop(&s3c2410_wdd);
94f1e9f3
BD
459}
460
af4bb822
BD
461#ifdef CONFIG_PM
462
463static unsigned long wtcon_save;
464static unsigned long wtdat_save;
465
3ae5eaec 466static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
af4bb822 467{
9480e307
RK
468 /* Save watchdog state, and turn it off. */
469 wtcon_save = readl(wdt_base + S3C2410_WTCON);
470 wtdat_save = readl(wdt_base + S3C2410_WTDAT);
af4bb822 471
9480e307 472 /* Note that WTCNT doesn't need to be saved. */
25dc46e3 473 s3c2410wdt_stop(&s3c2410_wdd);
af4bb822
BD
474
475 return 0;
476}
477
3ae5eaec 478static int s3c2410wdt_resume(struct platform_device *dev)
af4bb822 479{
9480e307 480 /* Restore watchdog state. */
af4bb822 481
9480e307
RK
482 writel(wtdat_save, wdt_base + S3C2410_WTDAT);
483 writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
484 writel(wtcon_save, wdt_base + S3C2410_WTCON);
af4bb822 485
9480e307
RK
486 printk(KERN_INFO PFX "watchdog %sabled\n",
487 (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
af4bb822
BD
488
489 return 0;
490}
491
492#else
493#define s3c2410wdt_suspend NULL
494#define s3c2410wdt_resume NULL
495#endif /* CONFIG_PM */
496
9487a9cc
TA
497#ifdef CONFIG_OF
498static const struct of_device_id s3c2410_wdt_match[] = {
499 { .compatible = "samsung,s3c2410-wdt" },
500 {},
501};
502MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
503#else
504#define s3c2410_wdt_match NULL
505#endif
af4bb822 506
3ae5eaec 507static struct platform_driver s3c2410wdt_driver = {
1da177e4 508 .probe = s3c2410wdt_probe,
a77dba7e 509 .remove = __devexit_p(s3c2410wdt_remove),
94f1e9f3 510 .shutdown = s3c2410wdt_shutdown,
af4bb822
BD
511 .suspend = s3c2410wdt_suspend,
512 .resume = s3c2410wdt_resume,
3ae5eaec
RK
513 .driver = {
514 .owner = THIS_MODULE,
515 .name = "s3c2410-wdt",
9487a9cc 516 .of_match_table = s3c2410_wdt_match,
3ae5eaec 517 },
1da177e4
LT
518};
519
520
41dc8b72
AC
521static char banner[] __initdata =
522 KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
1da177e4
LT
523
524static int __init watchdog_init(void)
525{
526 printk(banner);
3ae5eaec 527 return platform_driver_register(&s3c2410wdt_driver);
1da177e4
LT
528}
529
530static void __exit watchdog_exit(void)
531{
3ae5eaec 532 platform_driver_unregister(&s3c2410wdt_driver);
1da177e4
LT
533}
534
535module_init(watchdog_init);
536module_exit(watchdog_exit);
537
af4bb822
BD
538MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
539 "Dimitry Andric <dimitry.andric@tomtom.com>");
1da177e4
LT
540MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
541MODULE_LICENSE("GPL");
542MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c 543MODULE_ALIAS("platform:s3c2410-wdt");