[linux-2.6-block.git] / drivers / watchdog / rt2880_wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
 *
 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2013 John Crispin <john@phrozen.org>
 *
 * This driver was based on: drivers/watchdog/softdog.c
 */

#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>

#include <asm/mach-ralink/ralink_regs.h>

#define SYSC_RSTSTAT			0x38
#define WDT_RST_CAUSE			BIT(1)

#define RALINK_WDT_TIMEOUT		30
#define RALINK_WDT_PRESCALE		65536

#define TIMER_REG_TMR1LOAD		0x00
#define TIMER_REG_TMR1CTL		0x08

#define TMRSTAT_TMR1RST			BIT(5)

#define TMR1CTL_ENABLE			BIT(7)
#define TMR1CTL_MODE_SHIFT		4
#define TMR1CTL_MODE_MASK		0x3
#define TMR1CTL_MODE_FREE_RUNNING	0x0
#define TMR1CTL_MODE_PERIODIC		0x1
#define TMR1CTL_MODE_TIMEOUT		0x2
#define TMR1CTL_MODE_WDT		0x3
#define TMR1CTL_PRESCALE_MASK		0xf
#define TMR1CTL_PRESCALE_65536		0xf

struct rt2880_wdt_data {
	void __iomem *base;
	unsigned long freq;
	struct clk *clk;
	struct reset_control *rst;
	struct watchdog_device wdt;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
		"Watchdog cannot be stopped once started (default="
		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
{
	iowrite32(val, base + reg);
}

static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
{
	return ioread32(base + reg);
}

static int rt288x_wdt_ping(struct watchdog_device *w)
{
	struct rt2880_wdt_data *drvdata = watchdog_get_drvdata(w);

	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, w->timeout * drvdata->freq);

	return 0;
}

static int rt288x_wdt_start(struct watchdog_device *w)
{
	struct rt2880_wdt_data *drvdata = watchdog_get_drvdata(w);
	u32 t;

	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
	t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT |
		TMR1CTL_PRESCALE_MASK);
	t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT |
		TMR1CTL_PRESCALE_65536);
	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);

	rt288x_wdt_ping(w);

	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
	t |= TMR1CTL_ENABLE;
	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);

	return 0;
}

static int rt288x_wdt_stop(struct watchdog_device *w)
{
	struct rt2880_wdt_data *drvdata = watchdog_get_drvdata(w);
	u32 t;

	rt288x_wdt_ping(w);

	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
	t &= ~TMR1CTL_ENABLE;
	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);

	return 0;
}

static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
{
	w->timeout = t;
	rt288x_wdt_ping(w);

	return 0;
}

static int rt288x_wdt_bootcause(void)
{
	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
		return WDIOF_CARDRESET;

	return 0;
}

static const struct watchdog_info rt288x_wdt_info = {
	.identity = "Ralink Watchdog",
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops rt288x_wdt_ops = {
	.owner = THIS_MODULE,
	.start = rt288x_wdt_start,
	.stop = rt288x_wdt_stop,
	.ping = rt288x_wdt_ping,
	.set_timeout = rt288x_wdt_set_timeout,
};

static int rt288x_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdt;
	struct rt2880_wdt_data *drvdata;
	int ret;

	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;

	drvdata->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(drvdata->base))
		return PTR_ERR(drvdata->base);

	drvdata->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(drvdata->clk))
		return PTR_ERR(drvdata->clk);

	drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
	if (!IS_ERR(drvdata->rst))
		reset_control_deassert(drvdata->rst);

	drvdata->freq = clk_get_rate(drvdata->clk) / RALINK_WDT_PRESCALE;

	wdt = &drvdata->wdt;
	wdt->info = &rt288x_wdt_info;
	wdt->ops = &rt288x_wdt_ops;
	wdt->min_timeout = 1;
	wdt->max_timeout = (0xfffful / drvdata->freq);
	wdt->parent = dev;
	wdt->bootstatus = rt288x_wdt_bootcause();

	watchdog_init_timeout(wdt, wdt->max_timeout, dev);
	watchdog_set_nowayout(wdt, nowayout);
	watchdog_set_drvdata(wdt, drvdata);

	watchdog_stop_on_reboot(wdt);
	ret = devm_watchdog_register_device(dev, &drvdata->wdt);
	if (!ret)
		dev_info(dev, "Initialized\n");

	return 0;
}

static const struct of_device_id rt288x_wdt_match[] = {
	{ .compatible = "ralink,rt2880-wdt" },
	{},
};
MODULE_DEVICE_TABLE(of, rt288x_wdt_match);

static struct platform_driver rt288x_wdt_driver = {
	.probe		= rt288x_wdt_probe,
	.driver		= {
		.name		= KBUILD_MODNAME,
		.of_match_table	= rt288x_wdt_match,
	},
};

module_platform_driver(rt288x_wdt_driver);

MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
473cf939 JC	2	/*
	3	* Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
	4	*
	5	* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
f3519a66	6	* Copyright (C) 2013 John Crispin <john@phrozen.org>
473cf939 JC	7	*
473cf939 JC	8	* This driver was based on: drivers/watchdog/softdog.c
473cf939 JC	9	*/
	10
	11	#include <linux/clk.h>
	12	#include <linux/reset.h>
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/watchdog.h>
473cf939 JC	16	#include <linux/moduleparam.h>
473cf939 JC	17	#include <linux/platform_device.h>
3aa8b8bb	18	#include <linux/mod_devicetable.h>
473cf939 JC	19
	20	#include <asm/mach-ralink/ralink_regs.h>
	21
	22	#define SYSC_RSTSTAT 0x38
	23	#define WDT_RST_CAUSE BIT(1)
	24
	25	#define RALINK_WDT_TIMEOUT 30
	26	#define RALINK_WDT_PRESCALE 65536
	27
	28	#define TIMER_REG_TMR1LOAD 0x00
	29	#define TIMER_REG_TMR1CTL 0x08
	30
	31	#define TMRSTAT_TMR1RST BIT(5)
	32
	33	#define TMR1CTL_ENABLE BIT(7)
	34	#define TMR1CTL_MODE_SHIFT 4
	35	#define TMR1CTL_MODE_MASK 0x3
	36	#define TMR1CTL_MODE_FREE_RUNNING 0x0
	37	#define TMR1CTL_MODE_PERIODIC 0x1
	38	#define TMR1CTL_MODE_TIMEOUT 0x2
	39	#define TMR1CTL_MODE_WDT 0x3
	40	#define TMR1CTL_PRESCALE_MASK 0xf
	41	#define TMR1CTL_PRESCALE_65536 0xf
	42
76ad36bf SP	43	struct rt2880_wdt_data {
	44	void __iomem *base;
	45	unsigned long freq;
	46	struct clk *clk;
	47	struct reset_control *rst;
	48	struct watchdog_device wdt;
	49	};
473cf939 JC	50
	51	static bool nowayout = WATCHDOG_NOWAYOUT;
	52	module_param(nowayout, bool, 0);
	53	MODULE_PARM_DESC(nowayout,
	54	"Watchdog cannot be stopped once started (default="
	55	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	56
af3ac8e4	57	static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
473cf939	58	{
76ad36bf	59	iowrite32(val, base + reg);
473cf939 JC	60	}
473cf939 JC	61
af3ac8e4	62	static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
473cf939	63	{
76ad36bf	64	return ioread32(base + reg);
473cf939 JC	65	}
	66
	67	static int rt288x_wdt_ping(struct watchdog_device *w)
	68	{
76ad36bf SP	69	struct rt2880_wdt_data *drvdata = watchdog_get_drvdata(w);
	70
	71	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, w->timeout * drvdata->freq);
473cf939 JC	72
	73	return 0;
	74	}
	75
	76	static int rt288x_wdt_start(struct watchdog_device *w)
	77	{
76ad36bf	78	struct rt2880_wdt_data *drvdata = watchdog_get_drvdata(w);
473cf939 JC	79	u32 t;
473cf939 JC	80
76ad36bf	81	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
473cf939 JC	82	t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT \|
	83	TMR1CTL_PRESCALE_MASK);
	84	t \|= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT \|
	85	TMR1CTL_PRESCALE_65536);
76ad36bf	86	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
473cf939 JC	87
	88	rt288x_wdt_ping(w);
	89
76ad36bf	90	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
473cf939	91	t \|= TMR1CTL_ENABLE;
76ad36bf	92	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
473cf939 JC	93
	94	return 0;
	95	}
	96
	97	static int rt288x_wdt_stop(struct watchdog_device *w)
	98	{
76ad36bf	99	struct rt2880_wdt_data *drvdata = watchdog_get_drvdata(w);
473cf939 JC	100	u32 t;
	101
	102	rt288x_wdt_ping(w);
	103
76ad36bf	104	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
473cf939	105	t &= ~TMR1CTL_ENABLE;
76ad36bf	106	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
473cf939 JC	107
	108	return 0;
	109	}
	110
	111	static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
	112	{
	113	w->timeout = t;
	114	rt288x_wdt_ping(w);
	115
	116	return 0;
	117	}
	118
	119	static int rt288x_wdt_bootcause(void)
	120	{
	121	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
	122	return WDIOF_CARDRESET;
	123
	124	return 0;
	125	}
	126
323edb2e	127	static const struct watchdog_info rt288x_wdt_info = {
473cf939 JC	128	.identity = "Ralink Watchdog",
	129	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	130	};
	131
b893e344	132	static const struct watchdog_ops rt288x_wdt_ops = {
473cf939 JC	133	.owner = THIS_MODULE,
	134	.start = rt288x_wdt_start,
	135	.stop = rt288x_wdt_stop,
	136	.ping = rt288x_wdt_ping,
	137	.set_timeout = rt288x_wdt_set_timeout,
	138	};
	139
473cf939 JC	140	static int rt288x_wdt_probe(struct platform_device *pdev)
473cf939 JC	141	{
570927df	142	struct device *dev = &pdev->dev;
76ad36bf SP	143	struct watchdog_device *wdt;
76ad36bf SP	144	struct rt2880_wdt_data *drvdata;
473cf939 JC	145	int ret;
473cf939 JC	146
76ad36bf SP	147	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
	148	if (!drvdata)
	149	return -ENOMEM;
	150
	151	drvdata->base = devm_platform_ioremap_resource(pdev, 0);
	152	if (IS_ERR(drvdata->base))
	153	return PTR_ERR(drvdata->base);
473cf939	154
76ad36bf SP	155	drvdata->clk = devm_clk_get(dev, NULL);
	156	if (IS_ERR(drvdata->clk))
	157	return PTR_ERR(drvdata->clk);
473cf939	158
76ad36bf SP	159	drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
	160	if (!IS_ERR(drvdata->rst))
	161	reset_control_deassert(drvdata->rst);
473cf939	162
76ad36bf	163	drvdata->freq = clk_get_rate(drvdata->clk) / RALINK_WDT_PRESCALE;
473cf939	164
76ad36bf SP	165	wdt = &drvdata->wdt;
	166	wdt->info = &rt288x_wdt_info;
	167	wdt->ops = &rt288x_wdt_ops;
	168	wdt->min_timeout = 1;
	169	wdt->max_timeout = (0xfffful / drvdata->freq);
	170	wdt->parent = dev;
	171	wdt->bootstatus = rt288x_wdt_bootcause();
473cf939	172
76ad36bf SP	173	watchdog_init_timeout(wdt, wdt->max_timeout, dev);
	174	watchdog_set_nowayout(wdt, nowayout);
	175	watchdog_set_drvdata(wdt, drvdata);
473cf939	176
76ad36bf SP	177	watchdog_stop_on_reboot(wdt);
76ad36bf SP	178	ret = devm_watchdog_register_device(dev, &drvdata->wdt);
473cf939	179	if (!ret)
570927df	180	dev_info(dev, "Initialized\n");
473cf939 JC	181
	182	return 0;
	183	}
	184
473cf939 JC	185	static const struct of_device_id rt288x_wdt_match[] = {
	186	{ .compatible = "ralink,rt2880-wdt" },
	187	{},
	188	};
	189	MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
	190
	191	static struct platform_driver rt288x_wdt_driver = {
	192	.probe = rt288x_wdt_probe,
473cf939 JC	193	.driver = {
473cf939 JC	194	.name = KBUILD_MODNAME,
473cf939 JC	195	.of_match_table = rt288x_wdt_match,
	196	},
	197	};
	198
	199	module_platform_driver(rt288x_wdt_driver);
	200
	201	MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
	202	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
	203	MODULE_LICENSE("GPL v2");