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bd99b68e WS |
1 | /* |
2 | * Watchdog driver for Renesas WDT watchdog | |
3 | * | |
1f185596 WS |
4 | * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> |
5 | * Copyright (C) 2015-17 Renesas Electronics Corporation | |
bd99b68e WS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/bitops.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/pm_runtime.h> | |
3fe95e6c FC |
19 | #include <linux/smp.h> |
20 | #include <linux/sys_soc.h> | |
bd99b68e WS |
21 | #include <linux/watchdog.h> |
22 | ||
23 | #define RWTCNT 0 | |
24 | #define RWTCSRA 4 | |
25 | #define RWTCSRA_WOVF BIT(4) | |
26 | #define RWTCSRA_WRFLG BIT(5) | |
27 | #define RWTCSRA_TME BIT(7) | |
03a196f2 | 28 | #define RWTCSRB 8 |
bd99b68e WS |
29 | |
30 | #define RWDT_DEFAULT_TIMEOUT 60U | |
31 | ||
82f64cd2 WS |
32 | /* |
33 | * In probe, clk_rate is checked to be not more than 16 bit * biggest clock | |
03a196f2 | 34 | * divider (12 bits). d is only a factor to fully utilize the WDT counter and |
82f64cd2 WS |
35 | * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits. |
36 | */ | |
37 | #define MUL_BY_CLKS_PER_SEC(p, d) \ | |
38 | DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks]) | |
39 | ||
03a196f2 | 40 | /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */ |
82f64cd2 WS |
41 | #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate) |
42 | ||
03a196f2 | 43 | static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 }; |
bd99b68e WS |
44 | |
45 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
46 | module_param(nowayout, bool, 0); | |
47 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
48 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
49 | ||
50 | struct rwdt_priv { | |
51 | void __iomem *base; | |
52 | struct watchdog_device wdev; | |
82f64cd2 | 53 | unsigned long clk_rate; |
07278ca1 | 54 | u16 time_left; |
bd99b68e WS |
55 | u8 cks; |
56 | }; | |
57 | ||
58 | static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg) | |
59 | { | |
60 | if (reg == RWTCNT) | |
61 | val |= 0x5a5a0000; | |
62 | else | |
63 | val |= 0xa5a5a500; | |
64 | ||
65 | writel_relaxed(val, priv->base + reg); | |
66 | } | |
67 | ||
68 | static int rwdt_init_timeout(struct watchdog_device *wdev) | |
69 | { | |
70 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
71 | ||
82f64cd2 | 72 | rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); |
bd99b68e WS |
73 | |
74 | return 0; | |
75 | } | |
76 | ||
77 | static int rwdt_start(struct watchdog_device *wdev) | |
78 | { | |
79 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
80 | ||
3be42941 | 81 | pm_runtime_get_sync(wdev->parent); |
bd99b68e | 82 | |
03a196f2 | 83 | rwdt_write(priv, 0, RWTCSRB); |
bd99b68e WS |
84 | rwdt_write(priv, priv->cks, RWTCSRA); |
85 | rwdt_init_timeout(wdev); | |
86 | ||
87 | while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG) | |
88 | cpu_relax(); | |
89 | ||
90 | rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA); | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
95 | static int rwdt_stop(struct watchdog_device *wdev) | |
96 | { | |
97 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
98 | ||
99 | rwdt_write(priv, priv->cks, RWTCSRA); | |
3be42941 | 100 | pm_runtime_put(wdev->parent); |
bd99b68e WS |
101 | |
102 | return 0; | |
103 | } | |
104 | ||
105 | static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev) | |
106 | { | |
107 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
108 | u16 val = readw_relaxed(priv->base + RWTCNT); | |
109 | ||
82f64cd2 | 110 | return DIV_BY_CLKS_PER_SEC(priv, 65536 - val); |
bd99b68e WS |
111 | } |
112 | ||
089bcaa8 FC |
113 | static int rwdt_restart(struct watchdog_device *wdev, unsigned long action, |
114 | void *data) | |
115 | { | |
116 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
117 | ||
118 | rwdt_start(wdev); | |
119 | rwdt_write(priv, 0xffff, RWTCNT); | |
120 | return 0; | |
121 | } | |
122 | ||
bd99b68e | 123 | static const struct watchdog_info rwdt_ident = { |
fdac6a90 VC |
124 | .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
125 | WDIOF_CARDRESET, | |
bd99b68e WS |
126 | .identity = "Renesas WDT Watchdog", |
127 | }; | |
128 | ||
129 | static const struct watchdog_ops rwdt_ops = { | |
130 | .owner = THIS_MODULE, | |
131 | .start = rwdt_start, | |
132 | .stop = rwdt_stop, | |
133 | .ping = rwdt_init_timeout, | |
134 | .get_timeleft = rwdt_get_timeleft, | |
089bcaa8 | 135 | .restart = rwdt_restart, |
bd99b68e WS |
136 | }; |
137 | ||
3fe95e6c FC |
138 | #if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP) |
139 | /* | |
140 | * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs | |
141 | */ | |
142 | static const struct soc_device_attribute rwdt_quirks_match[] = { | |
143 | { | |
144 | .soc_id = "r8a7790", | |
145 | .revision = "ES1.*", | |
146 | .data = (void *)1, /* needs single CPU */ | |
147 | }, { | |
148 | .soc_id = "r8a7791", | |
665f9442 | 149 | .revision = "ES1.*", |
3fe95e6c FC |
150 | .data = (void *)1, /* needs single CPU */ |
151 | }, { | |
152 | .soc_id = "r8a7792", | |
153 | .revision = "*", | |
154 | .data = (void *)0, /* needs SMP disabled */ | |
155 | }, | |
156 | { /* sentinel */ } | |
157 | }; | |
158 | ||
159 | static bool rwdt_blacklisted(struct device *dev) | |
160 | { | |
161 | const struct soc_device_attribute *attr; | |
162 | ||
163 | attr = soc_device_match(rwdt_quirks_match); | |
164 | if (attr && setup_max_cpus > (uintptr_t)attr->data) { | |
165 | dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id, | |
166 | attr->revision); | |
167 | return true; | |
168 | } | |
169 | ||
170 | return false; | |
171 | } | |
172 | #else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */ | |
173 | static inline bool rwdt_blacklisted(struct device *dev) { return false; } | |
174 | #endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */ | |
175 | ||
bd99b68e WS |
176 | static int rwdt_probe(struct platform_device *pdev) |
177 | { | |
178 | struct rwdt_priv *priv; | |
179 | struct resource *res; | |
9c22b6d3 | 180 | struct clk *clk; |
82f64cd2 | 181 | unsigned long clks_per_sec; |
bd99b68e WS |
182 | int ret, i; |
183 | ||
3fe95e6c FC |
184 | if (rwdt_blacklisted(&pdev->dev)) |
185 | return -ENODEV; | |
186 | ||
bd99b68e WS |
187 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
188 | if (!priv) | |
189 | return -ENOMEM; | |
190 | ||
191 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
192 | priv->base = devm_ioremap_resource(&pdev->dev, res); | |
193 | if (IS_ERR(priv->base)) | |
194 | return PTR_ERR(priv->base); | |
195 | ||
9c22b6d3 WS |
196 | clk = devm_clk_get(&pdev->dev, NULL); |
197 | if (IS_ERR(clk)) | |
198 | return PTR_ERR(clk); | |
bd99b68e | 199 | |
3be42941 | 200 | pm_runtime_enable(&pdev->dev); |
3be42941 | 201 | pm_runtime_get_sync(&pdev->dev); |
9c22b6d3 | 202 | priv->clk_rate = clk_get_rate(clk); |
fdac6a90 VC |
203 | priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) & |
204 | RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0; | |
3be42941 WS |
205 | pm_runtime_put(&pdev->dev); |
206 | ||
207 | if (!priv->clk_rate) { | |
208 | ret = -ENOENT; | |
209 | goto out_pm_disable; | |
210 | } | |
bd99b68e WS |
211 | |
212 | for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) { | |
82f64cd2 | 213 | clks_per_sec = priv->clk_rate / clk_divs[i]; |
b51247c8 | 214 | if (clks_per_sec && clks_per_sec < 65536) { |
bd99b68e WS |
215 | priv->cks = i; |
216 | break; | |
217 | } | |
218 | } | |
219 | ||
b51247c8 | 220 | if (i < 0) { |
bd99b68e | 221 | dev_err(&pdev->dev, "Can't find suitable clock divider\n"); |
3be42941 WS |
222 | ret = -ERANGE; |
223 | goto out_pm_disable; | |
bd99b68e WS |
224 | } |
225 | ||
bd99b68e WS |
226 | priv->wdev.info = &rwdt_ident, |
227 | priv->wdev.ops = &rwdt_ops, | |
228 | priv->wdev.parent = &pdev->dev; | |
229 | priv->wdev.min_timeout = 1; | |
82f64cd2 | 230 | priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536); |
bd99b68e WS |
231 | priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT); |
232 | ||
233 | platform_set_drvdata(pdev, priv); | |
234 | watchdog_set_drvdata(&priv->wdev, priv); | |
235 | watchdog_set_nowayout(&priv->wdev, nowayout); | |
089bcaa8 | 236 | watchdog_set_restart_priority(&priv->wdev, 0); |
bd99b68e WS |
237 | |
238 | /* This overrides the default timeout only if DT configuration was found */ | |
239 | ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev); | |
240 | if (ret) | |
241 | dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n"); | |
242 | ||
243 | ret = watchdog_register_device(&priv->wdev); | |
3be42941 WS |
244 | if (ret < 0) |
245 | goto out_pm_disable; | |
bd99b68e WS |
246 | |
247 | return 0; | |
3be42941 WS |
248 | |
249 | out_pm_disable: | |
250 | pm_runtime_disable(&pdev->dev); | |
251 | return ret; | |
bd99b68e WS |
252 | } |
253 | ||
254 | static int rwdt_remove(struct platform_device *pdev) | |
255 | { | |
256 | struct rwdt_priv *priv = platform_get_drvdata(pdev); | |
257 | ||
258 | watchdog_unregister_device(&priv->wdev); | |
bd99b68e WS |
259 | pm_runtime_disable(&pdev->dev); |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
07278ca1 FC |
264 | static int __maybe_unused rwdt_suspend(struct device *dev) |
265 | { | |
266 | struct rwdt_priv *priv = dev_get_drvdata(dev); | |
267 | ||
268 | if (watchdog_active(&priv->wdev)) { | |
269 | priv->time_left = readw(priv->base + RWTCNT); | |
270 | rwdt_stop(&priv->wdev); | |
271 | } | |
272 | return 0; | |
273 | } | |
274 | ||
275 | static int __maybe_unused rwdt_resume(struct device *dev) | |
276 | { | |
277 | struct rwdt_priv *priv = dev_get_drvdata(dev); | |
278 | ||
279 | if (watchdog_active(&priv->wdev)) { | |
280 | rwdt_start(&priv->wdev); | |
281 | rwdt_write(priv, priv->time_left, RWTCNT); | |
282 | } | |
283 | return 0; | |
284 | } | |
285 | ||
286 | static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume); | |
287 | ||
bd99b68e | 288 | static const struct of_device_id rwdt_ids[] = { |
3fe95e6c | 289 | { .compatible = "renesas,rcar-gen2-wdt", }, |
bd99b68e WS |
290 | { .compatible = "renesas,rcar-gen3-wdt", }, |
291 | { /* sentinel */ } | |
292 | }; | |
293 | MODULE_DEVICE_TABLE(of, rwdt_ids); | |
294 | ||
295 | static struct platform_driver rwdt_driver = { | |
296 | .driver = { | |
297 | .name = "renesas_wdt", | |
298 | .of_match_table = rwdt_ids, | |
07278ca1 | 299 | .pm = &rwdt_pm_ops, |
bd99b68e WS |
300 | }, |
301 | .probe = rwdt_probe, | |
302 | .remove = rwdt_remove, | |
303 | }; | |
304 | module_platform_driver(rwdt_driver); | |
305 | ||
306 | MODULE_DESCRIPTION("Renesas WDT Watchdog Driver"); | |
307 | MODULE_LICENSE("GPL v2"); | |
308 | MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>"); |