[linux-2.6-block.git] / drivers / watchdog / renesas_wdt.c

/*
 * Watchdog driver for Renesas WDT watchdog
 *
 * Copyright (C) 2015-16 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 * Copyright (C) 2015-16 Renesas Electronics Corporation
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/watchdog.h>

#define RWTCNT		0
#define RWTCSRA		4
#define RWTCSRA_WOVF	BIT(4)
#define RWTCSRA_WRFLG	BIT(5)
#define RWTCSRA_TME	BIT(7)
#define RWTCSRB		8

#define RWDT_DEFAULT_TIMEOUT 60U

/*
 * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
 * divider (12 bits). d is only a factor to fully utilize the WDT counter and
 * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
 */
#define MUL_BY_CLKS_PER_SEC(p, d) \
	DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])

/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)

static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

struct rwdt_priv {
	void __iomem *base;
	struct watchdog_device wdev;
	struct clk *clk;
	unsigned long clk_rate;
	u8 cks;
};

static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
{
	if (reg == RWTCNT)
		val |= 0x5a5a0000;
	else
		val |= 0xa5a5a500;

	writel_relaxed(val, priv->base + reg);
}

static int rwdt_init_timeout(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

	rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);

	return 0;
}

static int rwdt_start(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

	clk_prepare_enable(priv->clk);

	rwdt_write(priv, 0, RWTCSRB);
	rwdt_write(priv, priv->cks, RWTCSRA);
	rwdt_init_timeout(wdev);

	while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
		cpu_relax();

	rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);

	return 0;
}

static int rwdt_stop(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);

	rwdt_write(priv, priv->cks, RWTCSRA);
	clk_disable_unprepare(priv->clk);

	return 0;
}

static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
{
	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	u16 val = readw_relaxed(priv->base + RWTCNT);

	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
}

static const struct watchdog_info rwdt_ident = {
	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
	.identity = "Renesas WDT Watchdog",
};

static const struct watchdog_ops rwdt_ops = {
	.owner = THIS_MODULE,
	.start = rwdt_start,
	.stop = rwdt_stop,
	.ping = rwdt_init_timeout,
	.get_timeleft = rwdt_get_timeleft,
};

static int rwdt_probe(struct platform_device *pdev)
{
	struct rwdt_priv *priv;
	struct resource *res;
	unsigned long clks_per_sec;
	int ret, i;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	priv->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(priv->clk))
		return PTR_ERR(priv->clk);

	priv->clk_rate = clk_get_rate(priv->clk);
	if (!priv->clk_rate)
		return -ENOENT;

	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
		clks_per_sec = priv->clk_rate / clk_divs[i];
		if (clks_per_sec && clks_per_sec < 65536) {
			priv->cks = i;
			break;
		}
	}

	if (i < 0) {
		dev_err(&pdev->dev, "Can't find suitable clock divider\n");
		return -ERANGE;
	}

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	priv->wdev.info = &rwdt_ident,
	priv->wdev.ops = &rwdt_ops,
	priv->wdev.parent = &pdev->dev;
	priv->wdev.min_timeout = 1;
	priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
	priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);

	platform_set_drvdata(pdev, priv);
	watchdog_set_drvdata(&priv->wdev, priv);
	watchdog_set_nowayout(&priv->wdev, nowayout);

	/* This overrides the default timeout only if DT configuration was found */
	ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
	if (ret)
		dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");

	ret = watchdog_register_device(&priv->wdev);
	if (ret < 0) {
		pm_runtime_put(&pdev->dev);
		pm_runtime_disable(&pdev->dev);
		return ret;
	}

	return 0;
}

static int rwdt_remove(struct platform_device *pdev)
{
	struct rwdt_priv *priv = platform_get_drvdata(pdev);

	watchdog_unregister_device(&priv->wdev);
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

/*
 * This driver does also fit for R-Car Gen2 (r8a779[0-4]) WDT. However, for SMP
 * to work there, one also needs a RESET (RST) driver which does not exist yet
 * due to HW issues. This needs to be solved before adding compatibles here.
 */
static const struct of_device_id rwdt_ids[] = {
	{ .compatible = "renesas,rcar-gen3-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rwdt_ids);

static struct platform_driver rwdt_driver = {
	.driver = {
		.name = "renesas_wdt",
		.of_match_table = rwdt_ids,
	},
	.probe = rwdt_probe,
	.remove = rwdt_remove,
};
module_platform_driver(rwdt_driver);

MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
Commit	Line	Data
bd99b68e WS	1	/*
	2	* Watchdog driver for Renesas WDT watchdog
	3	*
	4	* Copyright (C) 2015-16 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
	5	* Copyright (C) 2015-16 Renesas Electronics Corporation
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*/
	11	#include <linux/bitops.h>
	12	#include <linux/clk.h>
	13	#include <linux/io.h>
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pm_runtime.h>
	19	#include <linux/watchdog.h>
	20
	21	#define RWTCNT 0
	22	#define RWTCSRA 4
	23	#define RWTCSRA_WOVF BIT(4)
	24	#define RWTCSRA_WRFLG BIT(5)
	25	#define RWTCSRA_TME BIT(7)
03a196f2	26	#define RWTCSRB 8
bd99b68e WS	27
	28	#define RWDT_DEFAULT_TIMEOUT 60U
	29
82f64cd2 WS	30	/*
82f64cd2 WS	31	* In probe, clk_rate is checked to be not more than 16 bit * biggest clock
03a196f2	32	* divider (12 bits). d is only a factor to fully utilize the WDT counter and
82f64cd2 WS	33	* will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
	34	*/
	35	#define MUL_BY_CLKS_PER_SEC(p, d) \
	36	DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
	37
03a196f2	38	/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
82f64cd2 WS	39	#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
82f64cd2 WS	40
03a196f2	41	static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
bd99b68e WS	42
	43	static bool nowayout = WATCHDOG_NOWAYOUT;
	44	module_param(nowayout, bool, 0);
	45	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	46	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	47
	48	struct rwdt_priv {
	49	void __iomem *base;
	50	struct watchdog_device wdev;
	51	struct clk *clk;
82f64cd2	52	unsigned long clk_rate;
bd99b68e WS	53	u8 cks;
	54	};
	55
	56	static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
	57	{
	58	if (reg == RWTCNT)
	59	val \|= 0x5a5a0000;
	60	else
	61	val \|= 0xa5a5a500;
	62
	63	writel_relaxed(val, priv->base + reg);
	64	}
	65
	66	static int rwdt_init_timeout(struct watchdog_device *wdev)
	67	{
	68	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	69
82f64cd2	70	rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
bd99b68e WS	71
	72	return 0;
	73	}
	74
	75	static int rwdt_start(struct watchdog_device *wdev)
	76	{
	77	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	78
	79	clk_prepare_enable(priv->clk);
	80
03a196f2	81	rwdt_write(priv, 0, RWTCSRB);
bd99b68e WS	82	rwdt_write(priv, priv->cks, RWTCSRA);
	83	rwdt_init_timeout(wdev);
	84
	85	while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
	86	cpu_relax();
	87
	88	rwdt_write(priv, priv->cks \| RWTCSRA_TME, RWTCSRA);
	89
	90	return 0;
	91	}
	92
	93	static int rwdt_stop(struct watchdog_device *wdev)
	94	{
	95	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	96
	97	rwdt_write(priv, priv->cks, RWTCSRA);
	98	clk_disable_unprepare(priv->clk);
	99
	100	return 0;
	101	}
	102
	103	static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
	104	{
	105	struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
	106	u16 val = readw_relaxed(priv->base + RWTCNT);
	107
82f64cd2	108	return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
bd99b68e WS	109	}
	110
	111	static const struct watchdog_info rwdt_ident = {
	112	.options = WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT,
	113	.identity = "Renesas WDT Watchdog",
	114	};
	115
	116	static const struct watchdog_ops rwdt_ops = {
	117	.owner = THIS_MODULE,
	118	.start = rwdt_start,
	119	.stop = rwdt_stop,
	120	.ping = rwdt_init_timeout,
	121	.get_timeleft = rwdt_get_timeleft,
	122	};
	123
	124	static int rwdt_probe(struct platform_device *pdev)
	125	{
	126	struct rwdt_priv *priv;
	127	struct resource *res;
82f64cd2	128	unsigned long clks_per_sec;
bd99b68e WS	129	int ret, i;
	130
	131	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	132	if (!priv)
	133	return -ENOMEM;
	134
	135	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	136	priv->base = devm_ioremap_resource(&pdev->dev, res);
	137	if (IS_ERR(priv->base))
	138	return PTR_ERR(priv->base);
	139
	140	priv->clk = devm_clk_get(&pdev->dev, NULL);
	141	if (IS_ERR(priv->clk))
	142	return PTR_ERR(priv->clk);
	143
82f64cd2 WS	144	priv->clk_rate = clk_get_rate(priv->clk);
82f64cd2 WS	145	if (!priv->clk_rate)
bd99b68e WS	146	return -ENOENT;
	147
	148	for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
82f64cd2	149	clks_per_sec = priv->clk_rate / clk_divs[i];
b51247c8	150	if (clks_per_sec && clks_per_sec < 65536) {
bd99b68e WS	151	priv->cks = i;
	152	break;
	153	}
	154	}
	155
b51247c8	156	if (i < 0) {
bd99b68e WS	157	dev_err(&pdev->dev, "Can't find suitable clock divider\n");
	158	return -ERANGE;
	159	}
	160
	161	pm_runtime_enable(&pdev->dev);
	162	pm_runtime_get_sync(&pdev->dev);
	163
	164	priv->wdev.info = &rwdt_ident,
	165	priv->wdev.ops = &rwdt_ops,
	166	priv->wdev.parent = &pdev->dev;
	167	priv->wdev.min_timeout = 1;
82f64cd2	168	priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
bd99b68e WS	169	priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
	170
	171	platform_set_drvdata(pdev, priv);
	172	watchdog_set_drvdata(&priv->wdev, priv);
	173	watchdog_set_nowayout(&priv->wdev, nowayout);
	174
	175	/* This overrides the default timeout only if DT configuration was found */
	176	ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
	177	if (ret)
	178	dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");
	179
	180	ret = watchdog_register_device(&priv->wdev);
	181	if (ret < 0) {
	182	pm_runtime_put(&pdev->dev);
	183	pm_runtime_disable(&pdev->dev);
	184	return ret;
	185	}
	186
	187	return 0;
	188	}
	189
	190	static int rwdt_remove(struct platform_device *pdev)
	191	{
	192	struct rwdt_priv *priv = platform_get_drvdata(pdev);
	193
	194	watchdog_unregister_device(&priv->wdev);
	195	pm_runtime_put(&pdev->dev);
	196	pm_runtime_disable(&pdev->dev);
	197
	198	return 0;
	199	}
	200
	201	/*
	202	* This driver does also fit for R-Car Gen2 (r8a779[0-4]) WDT. However, for SMP
	203	* to work there, one also needs a RESET (RST) driver which does not exist yet
	204	* due to HW issues. This needs to be solved before adding compatibles here.
	205	*/
	206	static const struct of_device_id rwdt_ids[] = {
	207	{ .compatible = "renesas,rcar-gen3-wdt", },
	208	{ /* sentinel */ }
	209	};
	210	MODULE_DEVICE_TABLE(of, rwdt_ids);
	211
	212	static struct platform_driver rwdt_driver = {
	213	.driver = {
	214	.name = "renesas_wdt",
	215	.of_match_table = rwdt_ids,
	216	},
	217	.probe = rwdt_probe,
	218	.remove = rwdt_remove,
	219	};
	220	module_platform_driver(rwdt_driver);
	221
	222	MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
	223	MODULE_LICENSE("GPL v2");
	224	MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");