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3bed02a2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
bd99b68e WS |
2 | /* |
3 | * Watchdog driver for Renesas WDT watchdog | |
4 | * | |
1f185596 WS |
5 | * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> |
6 | * Copyright (C) 2015-17 Renesas Electronics Corporation | |
bd99b68e WS |
7 | */ |
8 | #include <linux/bitops.h> | |
9 | #include <linux/clk.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/pm_runtime.h> | |
3fe95e6c FC |
16 | #include <linux/smp.h> |
17 | #include <linux/sys_soc.h> | |
bd99b68e WS |
18 | #include <linux/watchdog.h> |
19 | ||
20 | #define RWTCNT 0 | |
21 | #define RWTCSRA 4 | |
22 | #define RWTCSRA_WOVF BIT(4) | |
23 | #define RWTCSRA_WRFLG BIT(5) | |
24 | #define RWTCSRA_TME BIT(7) | |
03a196f2 | 25 | #define RWTCSRB 8 |
bd99b68e WS |
26 | |
27 | #define RWDT_DEFAULT_TIMEOUT 60U | |
28 | ||
82f64cd2 WS |
29 | /* |
30 | * In probe, clk_rate is checked to be not more than 16 bit * biggest clock | |
03a196f2 | 31 | * divider (12 bits). d is only a factor to fully utilize the WDT counter and |
82f64cd2 WS |
32 | * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits. |
33 | */ | |
34 | #define MUL_BY_CLKS_PER_SEC(p, d) \ | |
35 | DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks]) | |
36 | ||
03a196f2 | 37 | /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */ |
82f64cd2 WS |
38 | #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate) |
39 | ||
03a196f2 | 40 | static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 }; |
bd99b68e WS |
41 | |
42 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
43 | module_param(nowayout, bool, 0); | |
44 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
45 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
46 | ||
47 | struct rwdt_priv { | |
48 | void __iomem *base; | |
49 | struct watchdog_device wdev; | |
82f64cd2 | 50 | unsigned long clk_rate; |
bd99b68e WS |
51 | u8 cks; |
52 | }; | |
53 | ||
54 | static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg) | |
55 | { | |
56 | if (reg == RWTCNT) | |
57 | val |= 0x5a5a0000; | |
58 | else | |
59 | val |= 0xa5a5a500; | |
60 | ||
61 | writel_relaxed(val, priv->base + reg); | |
62 | } | |
63 | ||
64 | static int rwdt_init_timeout(struct watchdog_device *wdev) | |
65 | { | |
66 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
67 | ||
82f64cd2 | 68 | rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); |
bd99b68e WS |
69 | |
70 | return 0; | |
71 | } | |
72 | ||
73 | static int rwdt_start(struct watchdog_device *wdev) | |
74 | { | |
75 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
e990e127 | 76 | u8 val; |
bd99b68e | 77 | |
3be42941 | 78 | pm_runtime_get_sync(wdev->parent); |
bd99b68e | 79 | |
e990e127 WS |
80 | /* Stop the timer before we modify any register */ |
81 | val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME; | |
82 | rwdt_write(priv, val, RWTCSRA); | |
83 | ||
bd99b68e | 84 | rwdt_init_timeout(wdev); |
e990e127 WS |
85 | rwdt_write(priv, priv->cks, RWTCSRA); |
86 | rwdt_write(priv, 0, RWTCSRB); | |
bd99b68e WS |
87 | |
88 | while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG) | |
89 | cpu_relax(); | |
90 | ||
91 | rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA); | |
92 | ||
93 | return 0; | |
94 | } | |
95 | ||
96 | static int rwdt_stop(struct watchdog_device *wdev) | |
97 | { | |
98 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
99 | ||
100 | rwdt_write(priv, priv->cks, RWTCSRA); | |
3be42941 | 101 | pm_runtime_put(wdev->parent); |
bd99b68e WS |
102 | |
103 | return 0; | |
104 | } | |
105 | ||
106 | static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev) | |
107 | { | |
108 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
109 | u16 val = readw_relaxed(priv->base + RWTCNT); | |
110 | ||
82f64cd2 | 111 | return DIV_BY_CLKS_PER_SEC(priv, 65536 - val); |
bd99b68e WS |
112 | } |
113 | ||
089bcaa8 FC |
114 | static int rwdt_restart(struct watchdog_device *wdev, unsigned long action, |
115 | void *data) | |
116 | { | |
117 | struct rwdt_priv *priv = watchdog_get_drvdata(wdev); | |
118 | ||
119 | rwdt_start(wdev); | |
120 | rwdt_write(priv, 0xffff, RWTCNT); | |
121 | return 0; | |
122 | } | |
123 | ||
bd99b68e | 124 | static const struct watchdog_info rwdt_ident = { |
fdac6a90 VC |
125 | .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
126 | WDIOF_CARDRESET, | |
bd99b68e WS |
127 | .identity = "Renesas WDT Watchdog", |
128 | }; | |
129 | ||
130 | static const struct watchdog_ops rwdt_ops = { | |
131 | .owner = THIS_MODULE, | |
132 | .start = rwdt_start, | |
133 | .stop = rwdt_stop, | |
134 | .ping = rwdt_init_timeout, | |
135 | .get_timeleft = rwdt_get_timeleft, | |
089bcaa8 | 136 | .restart = rwdt_restart, |
bd99b68e WS |
137 | }; |
138 | ||
3fe95e6c FC |
139 | #if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP) |
140 | /* | |
141 | * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs | |
142 | */ | |
143 | static const struct soc_device_attribute rwdt_quirks_match[] = { | |
144 | { | |
145 | .soc_id = "r8a7790", | |
146 | .revision = "ES1.*", | |
147 | .data = (void *)1, /* needs single CPU */ | |
148 | }, { | |
149 | .soc_id = "r8a7791", | |
665f9442 | 150 | .revision = "ES1.*", |
3fe95e6c FC |
151 | .data = (void *)1, /* needs single CPU */ |
152 | }, { | |
153 | .soc_id = "r8a7792", | |
3fe95e6c FC |
154 | .data = (void *)0, /* needs SMP disabled */ |
155 | }, | |
156 | { /* sentinel */ } | |
157 | }; | |
158 | ||
159 | static bool rwdt_blacklisted(struct device *dev) | |
160 | { | |
161 | const struct soc_device_attribute *attr; | |
162 | ||
163 | attr = soc_device_match(rwdt_quirks_match); | |
164 | if (attr && setup_max_cpus > (uintptr_t)attr->data) { | |
165 | dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id, | |
166 | attr->revision); | |
167 | return true; | |
168 | } | |
169 | ||
170 | return false; | |
171 | } | |
172 | #else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */ | |
173 | static inline bool rwdt_blacklisted(struct device *dev) { return false; } | |
174 | #endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */ | |
175 | ||
bd99b68e WS |
176 | static int rwdt_probe(struct platform_device *pdev) |
177 | { | |
178 | struct rwdt_priv *priv; | |
9c22b6d3 | 179 | struct clk *clk; |
82f64cd2 | 180 | unsigned long clks_per_sec; |
bd99b68e WS |
181 | int ret, i; |
182 | ||
3fe95e6c FC |
183 | if (rwdt_blacklisted(&pdev->dev)) |
184 | return -ENODEV; | |
185 | ||
bd99b68e WS |
186 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
187 | if (!priv) | |
188 | return -ENOMEM; | |
189 | ||
0f0a6a28 | 190 | priv->base = devm_platform_ioremap_resource(pdev, 0); |
bd99b68e WS |
191 | if (IS_ERR(priv->base)) |
192 | return PTR_ERR(priv->base); | |
193 | ||
9c22b6d3 WS |
194 | clk = devm_clk_get(&pdev->dev, NULL); |
195 | if (IS_ERR(clk)) | |
196 | return PTR_ERR(clk); | |
bd99b68e | 197 | |
3be42941 | 198 | pm_runtime_enable(&pdev->dev); |
3be42941 | 199 | pm_runtime_get_sync(&pdev->dev); |
9c22b6d3 | 200 | priv->clk_rate = clk_get_rate(clk); |
fdac6a90 VC |
201 | priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) & |
202 | RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0; | |
3be42941 WS |
203 | pm_runtime_put(&pdev->dev); |
204 | ||
205 | if (!priv->clk_rate) { | |
206 | ret = -ENOENT; | |
207 | goto out_pm_disable; | |
208 | } | |
bd99b68e WS |
209 | |
210 | for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) { | |
82f64cd2 | 211 | clks_per_sec = priv->clk_rate / clk_divs[i]; |
b51247c8 | 212 | if (clks_per_sec && clks_per_sec < 65536) { |
bd99b68e WS |
213 | priv->cks = i; |
214 | break; | |
215 | } | |
216 | } | |
217 | ||
b51247c8 | 218 | if (i < 0) { |
bd99b68e | 219 | dev_err(&pdev->dev, "Can't find suitable clock divider\n"); |
3be42941 WS |
220 | ret = -ERANGE; |
221 | goto out_pm_disable; | |
bd99b68e WS |
222 | } |
223 | ||
f8cde726 FC |
224 | priv->wdev.info = &rwdt_ident; |
225 | priv->wdev.ops = &rwdt_ops; | |
bd99b68e WS |
226 | priv->wdev.parent = &pdev->dev; |
227 | priv->wdev.min_timeout = 1; | |
82f64cd2 | 228 | priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536); |
bd99b68e WS |
229 | priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT); |
230 | ||
231 | platform_set_drvdata(pdev, priv); | |
232 | watchdog_set_drvdata(&priv->wdev, priv); | |
233 | watchdog_set_nowayout(&priv->wdev, nowayout); | |
089bcaa8 | 234 | watchdog_set_restart_priority(&priv->wdev, 0); |
14de99b4 | 235 | watchdog_stop_on_unregister(&priv->wdev); |
bd99b68e WS |
236 | |
237 | /* This overrides the default timeout only if DT configuration was found */ | |
cd6457a9 | 238 | watchdog_init_timeout(&priv->wdev, 0, &pdev->dev); |
bd99b68e WS |
239 | |
240 | ret = watchdog_register_device(&priv->wdev); | |
3be42941 WS |
241 | if (ret < 0) |
242 | goto out_pm_disable; | |
bd99b68e WS |
243 | |
244 | return 0; | |
3be42941 WS |
245 | |
246 | out_pm_disable: | |
247 | pm_runtime_disable(&pdev->dev); | |
248 | return ret; | |
bd99b68e WS |
249 | } |
250 | ||
251 | static int rwdt_remove(struct platform_device *pdev) | |
252 | { | |
253 | struct rwdt_priv *priv = platform_get_drvdata(pdev); | |
254 | ||
255 | watchdog_unregister_device(&priv->wdev); | |
bd99b68e WS |
256 | pm_runtime_disable(&pdev->dev); |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
07278ca1 FC |
261 | static int __maybe_unused rwdt_suspend(struct device *dev) |
262 | { | |
263 | struct rwdt_priv *priv = dev_get_drvdata(dev); | |
264 | ||
9077123c | 265 | if (watchdog_active(&priv->wdev)) |
07278ca1 | 266 | rwdt_stop(&priv->wdev); |
9077123c | 267 | |
07278ca1 FC |
268 | return 0; |
269 | } | |
270 | ||
271 | static int __maybe_unused rwdt_resume(struct device *dev) | |
272 | { | |
273 | struct rwdt_priv *priv = dev_get_drvdata(dev); | |
274 | ||
9077123c | 275 | if (watchdog_active(&priv->wdev)) |
07278ca1 | 276 | rwdt_start(&priv->wdev); |
9077123c | 277 | |
07278ca1 FC |
278 | return 0; |
279 | } | |
280 | ||
281 | static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume); | |
282 | ||
bd99b68e | 283 | static const struct of_device_id rwdt_ids[] = { |
3fe95e6c | 284 | { .compatible = "renesas,rcar-gen2-wdt", }, |
bd99b68e WS |
285 | { .compatible = "renesas,rcar-gen3-wdt", }, |
286 | { /* sentinel */ } | |
287 | }; | |
288 | MODULE_DEVICE_TABLE(of, rwdt_ids); | |
289 | ||
290 | static struct platform_driver rwdt_driver = { | |
291 | .driver = { | |
292 | .name = "renesas_wdt", | |
293 | .of_match_table = rwdt_ids, | |
07278ca1 | 294 | .pm = &rwdt_pm_ops, |
bd99b68e WS |
295 | }, |
296 | .probe = rwdt_probe, | |
297 | .remove = rwdt_remove, | |
298 | }; | |
299 | module_platform_driver(rwdt_driver); | |
300 | ||
301 | MODULE_DESCRIPTION("Renesas WDT Watchdog Driver"); | |
302 | MODULE_LICENSE("GPL v2"); | |
303 | MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>"); |