[linux-2.6-block.git] / drivers / watchdog / qcom-wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 */
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/of_device.h>

enum wdt_reg {
	WDT_RST,
	WDT_EN,
	WDT_STS,
	WDT_BARK_TIME,
	WDT_BITE_TIME,
};

#define QCOM_WDT_ENABLE		BIT(0)
#define QCOM_WDT_ENABLE_IRQ	BIT(1)

static const u32 reg_offset_data_apcs_tmr[] = {
	[WDT_RST] = 0x38,
	[WDT_EN] = 0x40,
	[WDT_STS] = 0x44,
	[WDT_BARK_TIME] = 0x4C,
	[WDT_BITE_TIME] = 0x5C,
};

static const u32 reg_offset_data_kpss[] = {
	[WDT_RST] = 0x4,
	[WDT_EN] = 0x8,
	[WDT_STS] = 0xC,
	[WDT_BARK_TIME] = 0x10,
	[WDT_BITE_TIME] = 0x14,
};

struct qcom_wdt {
	struct watchdog_device	wdd;
	unsigned long		rate;
	void __iomem		*base;
	const u32		*layout;
};

static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
{
	return wdt->base + wdt->layout[reg];
}

static inline
struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
{
	return container_of(wdd, struct qcom_wdt, wdd);
}

static inline int qcom_get_enable(struct watchdog_device *wdd)
{
	int enable = QCOM_WDT_ENABLE;

	if (wdd->pretimeout)
		enable |= QCOM_WDT_ENABLE_IRQ;

	return enable;
}

static irqreturn_t qcom_wdt_isr(int irq, void *arg)
{
	struct watchdog_device *wdd = arg;

	watchdog_notify_pretimeout(wdd);

	return IRQ_HANDLED;
}

static int qcom_wdt_start(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	unsigned int bark = wdd->timeout - wdd->pretimeout;

	writel(0, wdt_addr(wdt, WDT_EN));
	writel(1, wdt_addr(wdt, WDT_RST));
	writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
	writel(qcom_get_enable(wdd), wdt_addr(wdt, WDT_EN));
	return 0;
}

static int qcom_wdt_stop(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(0, wdt_addr(wdt, WDT_EN));
	return 0;
}

static int qcom_wdt_ping(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(1, wdt_addr(wdt, WDT_RST));
	return 0;
}

static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
				unsigned int timeout)
{
	wdd->timeout = timeout;
	return qcom_wdt_start(wdd);
}

static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
				   unsigned int timeout)
{
	wdd->pretimeout = timeout;
	return qcom_wdt_start(wdd);
}

static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
			    void *data)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	u32 timeout;

	/*
	 * Trigger watchdog bite:
	 *    Setup BITE_TIME to be 128ms, and enable WDT.
	 */
	timeout = 128 * wdt->rate / 1000;

	writel(0, wdt_addr(wdt, WDT_EN));
	writel(1, wdt_addr(wdt, WDT_RST));
	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));

	/*
	 * Actually make sure the above sequence hits hardware before sleeping.
	 */
	wmb();

	msleep(150);
	return 0;
}

static const struct watchdog_ops qcom_wdt_ops = {
	.start		= qcom_wdt_start,
	.stop		= qcom_wdt_stop,
	.ping		= qcom_wdt_ping,
	.set_timeout	= qcom_wdt_set_timeout,
	.set_pretimeout	= qcom_wdt_set_pretimeout,
	.restart        = qcom_wdt_restart,
	.owner		= THIS_MODULE,
};

static const struct watchdog_info qcom_wdt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT
			| WDIOF_CARDRESET,
	.identity	= KBUILD_MODNAME,
};

static const struct watchdog_info qcom_wdt_pt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT
			| WDIOF_PRETIMEOUT
			| WDIOF_CARDRESET,
	.identity	= KBUILD_MODNAME,
};

static void qcom_clk_disable_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static int qcom_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct qcom_wdt *wdt;
	struct resource *res;
	struct device_node *np = dev->of_node;
	const u32 *regs;
	u32 percpu_offset;
	int irq, ret;
	struct clk *clk;

	regs = of_device_get_match_data(dev);
	if (!regs) {
		dev_err(dev, "Unsupported QCOM WDT module\n");
		return -ENODEV;
	}

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOMEM;

	/* We use CPU0's DGT for the watchdog */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	res->start += percpu_offset;
	res->end += percpu_offset;

	wdt->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	clk = devm_clk_get(dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get input clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		dev_err(dev, "failed to setup clock\n");
		return ret;
	}
	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
	if (ret)
		return ret;

	/*
	 * We use the clock rate to calculate the max timeout, so ensure it's
	 * not zero to avoid a divide-by-zero exception.
	 *
	 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
	 * that it would bite before a second elapses it's usefulness is
	 * limited.  Bail if this is the case.
	 */
	wdt->rate = clk_get_rate(clk);
	if (wdt->rate == 0 ||
	    wdt->rate > 0x10000000U) {
		dev_err(dev, "invalid clock rate\n");
		return -EINVAL;
	}

	/* check if there is pretimeout support */
	irq = platform_get_irq_optional(pdev, 0);
	if (irq > 0) {
		ret = devm_request_irq(dev, irq, qcom_wdt_isr,
				       IRQF_TRIGGER_RISING,
				       "wdt_bark", &wdt->wdd);
		if (ret)
			return ret;

		wdt->wdd.info = &qcom_wdt_pt_info;
		wdt->wdd.pretimeout = 1;
	} else {
		if (irq == -EPROBE_DEFER)
			return -EPROBE_DEFER;

		wdt->wdd.info = &qcom_wdt_info;
	}

	wdt->wdd.ops = &qcom_wdt_ops;
	wdt->wdd.min_timeout = 1;
	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
	wdt->wdd.parent = dev;
	wdt->layout = regs;

	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
		wdt->wdd.bootstatus = WDIOF_CARDRESET;

	/*
	 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
	 * default, unless the max timeout is less than 30 seconds, then use
	 * the max instead.
	 */
	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
	watchdog_init_timeout(&wdt->wdd, 0, dev);

	ret = devm_watchdog_register_device(dev, &wdt->wdd);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, wdt);
	return 0;
}

static int __maybe_unused qcom_wdt_suspend(struct device *dev)
{
	struct qcom_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		qcom_wdt_stop(&wdt->wdd);

	return 0;
}

static int __maybe_unused qcom_wdt_resume(struct device *dev)
{
	struct qcom_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		qcom_wdt_start(&wdt->wdd);

	return 0;
}

static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);

static const struct of_device_id qcom_wdt_of_table[] = {
	{ .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
	{ .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
	{ .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
	{ },
};
MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);

static struct platform_driver qcom_watchdog_driver = {
	.probe	= qcom_wdt_probe,
	.driver	= {
		.name		= KBUILD_MODNAME,
		.of_match_table	= qcom_wdt_of_table,
		.pm		= &qcom_wdt_pm_ops,
	},
};
module_platform_driver(qcom_watchdog_driver);

MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
1094ebe9	2	/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
1094ebe9	3	*/
36375491	4	#include <linux/bits.h>
1094ebe9	5	#include <linux/clk.h>
05e487d9	6	#include <linux/delay.h>
36375491	7	#include <linux/interrupt.h>
1094ebe9 JC	8	#include <linux/io.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/watchdog.h>
f0d9d0f4	14	#include <linux/of_device.h>
1094ebe9	15
f0d9d0f4 MM	16	enum wdt_reg {
	17	WDT_RST,
	18	WDT_EN,
	19	WDT_STS,
10073a20	20	WDT_BARK_TIME,
f0d9d0f4 MM	21	WDT_BITE_TIME,
	22	};
	23
36375491 JRO	24	#define QCOM_WDT_ENABLE BIT(0)
	25	#define QCOM_WDT_ENABLE_IRQ BIT(1)
	26
f0d9d0f4 MM	27	static const u32 reg_offset_data_apcs_tmr[] = {
	28	[WDT_RST] = 0x38,
	29	[WDT_EN] = 0x40,
	30	[WDT_STS] = 0x44,
10073a20	31	[WDT_BARK_TIME] = 0x4C,
f0d9d0f4 MM	32	[WDT_BITE_TIME] = 0x5C,
	33	};
	34
	35	static const u32 reg_offset_data_kpss[] = {
	36	[WDT_RST] = 0x4,
	37	[WDT_EN] = 0x8,
	38	[WDT_STS] = 0xC,
10073a20	39	[WDT_BARK_TIME] = 0x10,
f0d9d0f4 MM	40	[WDT_BITE_TIME] = 0x14,
f0d9d0f4 MM	41	};
1094ebe9 JC	42
	43	struct qcom_wdt {
	44	struct watchdog_device wdd;
1094ebe9 JC	45	unsigned long rate;
1094ebe9 JC	46	void __iomem *base;
f0d9d0f4	47	const u32 *layout;
1094ebe9 JC	48	};
1094ebe9 JC	49
f0d9d0f4 MM	50	static void __iomem wdt_addr(struct qcom_wdt wdt, enum wdt_reg reg)
	51	{
	52	return wdt->base + wdt->layout[reg];
	53	}
	54
1094ebe9 JC	55	static inline
	56	struct qcom_wdt to_qcom_wdt(struct watchdog_device wdd)
	57	{
	58	return container_of(wdd, struct qcom_wdt, wdd);
	59	}
	60
36375491 JRO	61	static inline int qcom_get_enable(struct watchdog_device *wdd)
	62	{
	63	int enable = QCOM_WDT_ENABLE;
	64
	65	if (wdd->pretimeout)
	66	enable \|= QCOM_WDT_ENABLE_IRQ;
	67
	68	return enable;
	69	}
	70
	71	static irqreturn_t qcom_wdt_isr(int irq, void *arg)
	72	{
	73	struct watchdog_device *wdd = arg;
	74
	75	watchdog_notify_pretimeout(wdd);
	76
	77	return IRQ_HANDLED;
	78	}
	79
1094ebe9 JC	80	static int qcom_wdt_start(struct watchdog_device *wdd)
	81	{
	82	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
36375491	83	unsigned int bark = wdd->timeout - wdd->pretimeout;
1094ebe9	84
f0d9d0f4 MM	85	writel(0, wdt_addr(wdt, WDT_EN));
f0d9d0f4 MM	86	writel(1, wdt_addr(wdt, WDT_RST));
36375491	87	writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
f0d9d0f4	88	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
36375491	89	writel(qcom_get_enable(wdd), wdt_addr(wdt, WDT_EN));
1094ebe9 JC	90	return 0;
	91	}
	92
	93	static int qcom_wdt_stop(struct watchdog_device *wdd)
	94	{
	95	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	96
f0d9d0f4	97	writel(0, wdt_addr(wdt, WDT_EN));
1094ebe9 JC	98	return 0;
	99	}
	100
	101	static int qcom_wdt_ping(struct watchdog_device *wdd)
	102	{
	103	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	104
f0d9d0f4	105	writel(1, wdt_addr(wdt, WDT_RST));
1094ebe9 JC	106	return 0;
	107	}
	108
	109	static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
	110	unsigned int timeout)
	111	{
	112	wdd->timeout = timeout;
	113	return qcom_wdt_start(wdd);
	114	}
	115
36375491 JRO	116	static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
	117	unsigned int timeout)
	118	{
	119	wdd->pretimeout = timeout;
	120	return qcom_wdt_start(wdd);
	121	}
	122
4d8b229d GR	123	static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
4d8b229d GR	124	void *data)
05e487d9	125	{
80969a68	126	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
05e487d9 JC	127	u32 timeout;
	128
	129	/*
	130	* Trigger watchdog bite:
	131	* Setup BITE_TIME to be 128ms, and enable WDT.
	132	*/
	133	timeout = 128 * wdt->rate / 1000;
	134
f0d9d0f4 MM	135	writel(0, wdt_addr(wdt, WDT_EN));
f0d9d0f4 MM	136	writel(1, wdt_addr(wdt, WDT_RST));
10073a20	137	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
f0d9d0f4	138	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
36375491	139	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
05e487d9 JC	140
	141	/*
	142	* Actually make sure the above sequence hits hardware before sleeping.
	143	*/
	144	wmb();
	145
	146	msleep(150);
80969a68	147	return 0;
05e487d9 JC	148	}
05e487d9 JC	149
80969a68 DR	150	static const struct watchdog_ops qcom_wdt_ops = {
	151	.start = qcom_wdt_start,
	152	.stop = qcom_wdt_stop,
	153	.ping = qcom_wdt_ping,
	154	.set_timeout = qcom_wdt_set_timeout,
36375491	155	.set_pretimeout = qcom_wdt_set_pretimeout,
80969a68 DR	156	.restart = qcom_wdt_restart,
	157	.owner = THIS_MODULE,
	158	};
	159
	160	static const struct watchdog_info qcom_wdt_info = {
	161	.options = WDIOF_KEEPALIVEPING
	162	\| WDIOF_MAGICCLOSE
b6ef36d2 GR	163	\| WDIOF_SETTIMEOUT
b6ef36d2 GR	164	\| WDIOF_CARDRESET,
80969a68 DR	165	.identity = KBUILD_MODNAME,
	166	};
	167
36375491 JRO	168	static const struct watchdog_info qcom_wdt_pt_info = {
	169	.options = WDIOF_KEEPALIVEPING
	170	\| WDIOF_MAGICCLOSE
	171	\| WDIOF_SETTIMEOUT
	172	\| WDIOF_PRETIMEOUT
	173	\| WDIOF_CARDRESET,
	174	.identity = KBUILD_MODNAME,
	175	};
	176
bba07e6e GR	177	static void qcom_clk_disable_unprepare(void *data)
	178	{
	179	clk_disable_unprepare(data);
	180	}
	181
1094ebe9 JC	182	static int qcom_wdt_probe(struct platform_device *pdev)
1094ebe9 JC	183	{
bba07e6e	184	struct device *dev = &pdev->dev;
1094ebe9 JC	185	struct qcom_wdt *wdt;
1094ebe9 JC	186	struct resource *res;
bba07e6e	187	struct device_node *np = dev->of_node;
f0d9d0f4	188	const u32 *regs;
0dfd582e	189	u32 percpu_offset;
36375491	190	int irq, ret;
52a14214	191	struct clk *clk;
1094ebe9	192
bba07e6e	193	regs = of_device_get_match_data(dev);
f0d9d0f4	194	if (!regs) {
bba07e6e	195	dev_err(dev, "Unsupported QCOM WDT module\n");
f0d9d0f4 MM	196	return -ENODEV;
	197	}
	198
bba07e6e	199	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
1094ebe9 JC	200	if (!wdt)
	201	return -ENOMEM;
	202
	203	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15210ad1 FE	204	if (!res)
15210ad1 FE	205	return -ENOMEM;
0dfd582e MO	206
	207	/* We use CPU0's DGT for the watchdog */
	208	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	209	percpu_offset = 0;
	210
	211	res->start += percpu_offset;
	212	res->end += percpu_offset;
	213
bba07e6e	214	wdt->base = devm_ioremap_resource(dev, res);
1094ebe9 JC	215	if (IS_ERR(wdt->base))
	216	return PTR_ERR(wdt->base);
	217
52a14214 JRO	218	clk = devm_clk_get(dev, NULL);
52a14214 JRO	219	if (IS_ERR(clk)) {
bba07e6e	220	dev_err(dev, "failed to get input clock\n");
52a14214	221	return PTR_ERR(clk);
1094ebe9 JC	222	}
1094ebe9 JC	223
52a14214	224	ret = clk_prepare_enable(clk);
1094ebe9	225	if (ret) {
bba07e6e	226	dev_err(dev, "failed to setup clock\n");
1094ebe9 JC	227	return ret;
1094ebe9 JC	228	}
52a14214	229	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
bba07e6e GR	230	if (ret)
bba07e6e GR	231	return ret;
1094ebe9 JC	232
	233	/*
	234	* We use the clock rate to calculate the max timeout, so ensure it's
	235	* not zero to avoid a divide-by-zero exception.
	236	*
	237	* WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
	238	* that it would bite before a second elapses it's usefulness is
	239	* limited. Bail if this is the case.
	240	*/
52a14214	241	wdt->rate = clk_get_rate(clk);
1094ebe9 JC	242	if (wdt->rate == 0 \|\|
1094ebe9 JC	243	wdt->rate > 0x10000000U) {
bba07e6e GR	244	dev_err(dev, "invalid clock rate\n");
bba07e6e GR	245	return -EINVAL;
1094ebe9 JC	246	}
1094ebe9 JC	247
36375491	248	/* check if there is pretimeout support */
e0b4f4e0	249	irq = platform_get_irq_optional(pdev, 0);
36375491 JRO	250	if (irq > 0) {
	251	ret = devm_request_irq(dev, irq, qcom_wdt_isr,
	252	IRQF_TRIGGER_RISING,
	253	"wdt_bark", &wdt->wdd);
	254	if (ret)
	255	return ret;
	256
	257	wdt->wdd.info = &qcom_wdt_pt_info;
	258	wdt->wdd.pretimeout = 1;
	259	} else {
	260	if (irq == -EPROBE_DEFER)
	261	return -EPROBE_DEFER;
	262
	263	wdt->wdd.info = &qcom_wdt_info;
	264	}
	265
1094ebe9 JC	266	wdt->wdd.ops = &qcom_wdt_ops;
	267	wdt->wdd.min_timeout = 1;
	268	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
bba07e6e	269	wdt->wdd.parent = dev;
f0d9d0f4	270	wdt->layout = regs;
1094ebe9	271
f06f35c6	272	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
b6ef36d2 GR	273	wdt->wdd.bootstatus = WDIOF_CARDRESET;
b6ef36d2 GR	274
1094ebe9 JC	275	/*
	276	* If 'timeout-sec' unspecified in devicetree, assume a 30 second
	277	* default, unless the max timeout is less than 30 seconds, then use
	278	* the max instead.
	279	*/
	280	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
bba07e6e	281	watchdog_init_timeout(&wdt->wdd, 0, dev);
1094ebe9	282
bba07e6e	283	ret = devm_watchdog_register_device(dev, &wdt->wdd);
ccbf872a	284	if (ret)
bba07e6e	285	return ret;
1094ebe9 JC	286
	287	platform_set_drvdata(pdev, wdt);
	288	return 0;
1094ebe9 JC	289	}
1094ebe9 JC	290
671cdde3 SPR	291	static int __maybe_unused qcom_wdt_suspend(struct device *dev)
	292	{
	293	struct qcom_wdt *wdt = dev_get_drvdata(dev);
	294
	295	if (watchdog_active(&wdt->wdd))
	296	qcom_wdt_stop(&wdt->wdd);
	297
	298	return 0;
	299	}
	300
	301	static int __maybe_unused qcom_wdt_resume(struct device *dev)
	302	{
	303	struct qcom_wdt *wdt = dev_get_drvdata(dev);
	304
	305	if (watchdog_active(&wdt->wdd))
	306	qcom_wdt_start(&wdt->wdd);
	307
	308	return 0;
	309	}
	310
	311	static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
	312
1094ebe9	313	static const struct of_device_id qcom_wdt_of_table[] = {
f0d9d0f4 MM	314	{ .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
	315	{ .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
	316	{ .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
1094ebe9 JC	317	{ },
	318	};
	319	MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
	320
	321	static struct platform_driver qcom_watchdog_driver = {
	322	.probe = qcom_wdt_probe,
1094ebe9 JC	323	.driver = {
	324	.name = KBUILD_MODNAME,
	325	.of_match_table = qcom_wdt_of_table,
671cdde3	326	.pm = &qcom_wdt_pm_ops,
1094ebe9 JC	327	},
	328	};
	329	module_platform_driver(qcom_watchdog_driver);
	330
	331	MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
	332	MODULE_LICENSE("GPL v2");