[linux-2.6-block.git] / drivers / watchdog / qcom-wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 */
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/of_device.h>

enum wdt_reg {
	WDT_RST,
	WDT_EN,
	WDT_STS,
	WDT_BARK_TIME,
	WDT_BITE_TIME,
};

#define QCOM_WDT_ENABLE		BIT(0)
#define QCOM_WDT_ENABLE_IRQ	BIT(1)

static const u32 reg_offset_data_apcs_tmr[] = {
	[WDT_RST] = 0x38,
	[WDT_EN] = 0x40,
	[WDT_STS] = 0x44,
	[WDT_BARK_TIME] = 0x4C,
	[WDT_BITE_TIME] = 0x5C,
};

static const u32 reg_offset_data_kpss[] = {
	[WDT_RST] = 0x4,
	[WDT_EN] = 0x8,
	[WDT_STS] = 0xC,
	[WDT_BARK_TIME] = 0x10,
	[WDT_BITE_TIME] = 0x14,
};

struct qcom_wdt_match_data {
	const u32 *offset;
	bool pretimeout;
};

struct qcom_wdt {
	struct watchdog_device	wdd;
	unsigned long		rate;
	void __iomem		*base;
	const u32		*layout;
};

static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
{
	return wdt->base + wdt->layout[reg];
}

static inline
struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
{
	return container_of(wdd, struct qcom_wdt, wdd);
}

static inline int qcom_get_enable(struct watchdog_device *wdd)
{
	int enable = QCOM_WDT_ENABLE;

	if (wdd->pretimeout)
		enable |= QCOM_WDT_ENABLE_IRQ;

	return enable;
}

static irqreturn_t qcom_wdt_isr(int irq, void *arg)
{
	struct watchdog_device *wdd = arg;

	watchdog_notify_pretimeout(wdd);

	return IRQ_HANDLED;
}

static int qcom_wdt_start(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	unsigned int bark = wdd->timeout - wdd->pretimeout;

	writel(0, wdt_addr(wdt, WDT_EN));
	writel(1, wdt_addr(wdt, WDT_RST));
	writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
	writel(qcom_get_enable(wdd), wdt_addr(wdt, WDT_EN));
	return 0;
}

static int qcom_wdt_stop(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(0, wdt_addr(wdt, WDT_EN));
	return 0;
}

static int qcom_wdt_ping(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(1, wdt_addr(wdt, WDT_RST));
	return 0;
}

static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
				unsigned int timeout)
{
	wdd->timeout = timeout;
	return qcom_wdt_start(wdd);
}

static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
				   unsigned int timeout)
{
	wdd->pretimeout = timeout;
	return qcom_wdt_start(wdd);
}

static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
			    void *data)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	u32 timeout;

	/*
	 * Trigger watchdog bite:
	 *    Setup BITE_TIME to be 128ms, and enable WDT.
	 */
	timeout = 128 * wdt->rate / 1000;

	writel(0, wdt_addr(wdt, WDT_EN));
	writel(1, wdt_addr(wdt, WDT_RST));
	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));

	/*
	 * Actually make sure the above sequence hits hardware before sleeping.
	 */
	wmb();

	mdelay(150);
	return 0;
}

static int qcom_wdt_is_running(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
}

static const struct watchdog_ops qcom_wdt_ops = {
	.start		= qcom_wdt_start,
	.stop		= qcom_wdt_stop,
	.ping		= qcom_wdt_ping,
	.set_timeout	= qcom_wdt_set_timeout,
	.set_pretimeout	= qcom_wdt_set_pretimeout,
	.restart        = qcom_wdt_restart,
	.owner		= THIS_MODULE,
};

static const struct watchdog_info qcom_wdt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT
			| WDIOF_CARDRESET,
	.identity	= KBUILD_MODNAME,
};

static const struct watchdog_info qcom_wdt_pt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT
			| WDIOF_PRETIMEOUT
			| WDIOF_CARDRESET,
	.identity	= KBUILD_MODNAME,
};

static void qcom_clk_disable_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static const struct qcom_wdt_match_data match_data_apcs_tmr = {
	.offset = reg_offset_data_apcs_tmr,
	.pretimeout = false,
};

static const struct qcom_wdt_match_data match_data_kpss = {
	.offset = reg_offset_data_kpss,
	.pretimeout = true,
};

static int qcom_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct qcom_wdt *wdt;
	struct resource *res;
	struct device_node *np = dev->of_node;
	const struct qcom_wdt_match_data *data;
	u32 percpu_offset;
	int irq, ret;
	struct clk *clk;

	data = of_device_get_match_data(dev);
	if (!data) {
		dev_err(dev, "Unsupported QCOM WDT module\n");
		return -ENODEV;
	}

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOMEM;

	/* We use CPU0's DGT for the watchdog */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	res->start += percpu_offset;
	res->end += percpu_offset;

	wdt->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	clk = devm_clk_get(dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get input clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		dev_err(dev, "failed to setup clock\n");
		return ret;
	}
	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
	if (ret)
		return ret;

	/*
	 * We use the clock rate to calculate the max timeout, so ensure it's
	 * not zero to avoid a divide-by-zero exception.
	 *
	 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
	 * that it would bite before a second elapses it's usefulness is
	 * limited.  Bail if this is the case.
	 */
	wdt->rate = clk_get_rate(clk);
	if (wdt->rate == 0 ||
	    wdt->rate > 0x10000000U) {
		dev_err(dev, "invalid clock rate\n");
		return -EINVAL;
	}

	/* check if there is pretimeout support */
	irq = platform_get_irq_optional(pdev, 0);
	if (data->pretimeout && irq > 0) {
		ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
				       "wdt_bark", &wdt->wdd);
		if (ret)
			return ret;

		wdt->wdd.info = &qcom_wdt_pt_info;
		wdt->wdd.pretimeout = 1;
	} else {
		if (irq == -EPROBE_DEFER)
			return -EPROBE_DEFER;

		wdt->wdd.info = &qcom_wdt_info;
	}

	wdt->wdd.ops = &qcom_wdt_ops;
	wdt->wdd.min_timeout = 1;
	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
	wdt->wdd.parent = dev;
	wdt->layout = data->offset;

	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
		wdt->wdd.bootstatus = WDIOF_CARDRESET;

	/*
	 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
	 * default, unless the max timeout is less than 30 seconds, then use
	 * the max instead.
	 */
	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
	watchdog_init_timeout(&wdt->wdd, 0, dev);

	/*
	 * If WDT is already running, call WDT start which
	 * will stop the WDT, set timeouts as bootloader
	 * might use different ones and set running bit
	 * to inform the WDT subsystem to ping the WDT
	 */
	if (qcom_wdt_is_running(&wdt->wdd)) {
		qcom_wdt_start(&wdt->wdd);
		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	}

	ret = devm_watchdog_register_device(dev, &wdt->wdd);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, wdt);
	return 0;
}

static int __maybe_unused qcom_wdt_suspend(struct device *dev)
{
	struct qcom_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		qcom_wdt_stop(&wdt->wdd);

	return 0;
}

static int __maybe_unused qcom_wdt_resume(struct device *dev)
{
	struct qcom_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		qcom_wdt_start(&wdt->wdd);

	return 0;
}

static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);

static const struct of_device_id qcom_wdt_of_table[] = {
	{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
	{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
	{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
	{ },
};
MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);

static struct platform_driver qcom_watchdog_driver = {
	.probe	= qcom_wdt_probe,
	.driver	= {
		.name		= KBUILD_MODNAME,
		.of_match_table	= qcom_wdt_of_table,
		.pm		= &qcom_wdt_pm_ops,
	},
};
module_platform_driver(qcom_watchdog_driver);

MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
1094ebe9	2	/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
1094ebe9	3	*/
36375491	4	#include <linux/bits.h>
1094ebe9	5	#include <linux/clk.h>
05e487d9	6	#include <linux/delay.h>
36375491	7	#include <linux/interrupt.h>
1094ebe9 JC	8	#include <linux/io.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/watchdog.h>
f0d9d0f4	14	#include <linux/of_device.h>
1094ebe9	15
f0d9d0f4 MM	16	enum wdt_reg {
	17	WDT_RST,
	18	WDT_EN,
	19	WDT_STS,
10073a20	20	WDT_BARK_TIME,
f0d9d0f4 MM	21	WDT_BITE_TIME,
	22	};
	23
36375491 JRO	24	#define QCOM_WDT_ENABLE BIT(0)
	25	#define QCOM_WDT_ENABLE_IRQ BIT(1)
	26
f0d9d0f4 MM	27	static const u32 reg_offset_data_apcs_tmr[] = {
	28	[WDT_RST] = 0x38,
	29	[WDT_EN] = 0x40,
	30	[WDT_STS] = 0x44,
10073a20	31	[WDT_BARK_TIME] = 0x4C,
f0d9d0f4 MM	32	[WDT_BITE_TIME] = 0x5C,
	33	};
	34
	35	static const u32 reg_offset_data_kpss[] = {
	36	[WDT_RST] = 0x4,
	37	[WDT_EN] = 0x8,
	38	[WDT_STS] = 0xC,
10073a20	39	[WDT_BARK_TIME] = 0x10,
f0d9d0f4 MM	40	[WDT_BITE_TIME] = 0x14,
f0d9d0f4 MM	41	};
1094ebe9	42
000de541 AS	43	struct qcom_wdt_match_data {
	44	const u32 *offset;
	45	bool pretimeout;
	46	};
	47
1094ebe9 JC	48	struct qcom_wdt {
1094ebe9 JC	49	struct watchdog_device wdd;
1094ebe9 JC	50	unsigned long rate;
1094ebe9 JC	51	void __iomem *base;
f0d9d0f4	52	const u32 *layout;
1094ebe9 JC	53	};
1094ebe9 JC	54
f0d9d0f4 MM	55	static void __iomem wdt_addr(struct qcom_wdt wdt, enum wdt_reg reg)
	56	{
	57	return wdt->base + wdt->layout[reg];
	58	}
	59
1094ebe9 JC	60	static inline
	61	struct qcom_wdt to_qcom_wdt(struct watchdog_device wdd)
	62	{
	63	return container_of(wdd, struct qcom_wdt, wdd);
	64	}
	65
36375491 JRO	66	static inline int qcom_get_enable(struct watchdog_device *wdd)
	67	{
	68	int enable = QCOM_WDT_ENABLE;
	69
	70	if (wdd->pretimeout)
	71	enable \|= QCOM_WDT_ENABLE_IRQ;
	72
	73	return enable;
	74	}
	75
	76	static irqreturn_t qcom_wdt_isr(int irq, void *arg)
	77	{
	78	struct watchdog_device *wdd = arg;
	79
	80	watchdog_notify_pretimeout(wdd);
	81
	82	return IRQ_HANDLED;
	83	}
	84
1094ebe9 JC	85	static int qcom_wdt_start(struct watchdog_device *wdd)
	86	{
	87	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
36375491	88	unsigned int bark = wdd->timeout - wdd->pretimeout;
1094ebe9	89
f0d9d0f4 MM	90	writel(0, wdt_addr(wdt, WDT_EN));
f0d9d0f4 MM	91	writel(1, wdt_addr(wdt, WDT_RST));
36375491	92	writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
f0d9d0f4	93	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
36375491	94	writel(qcom_get_enable(wdd), wdt_addr(wdt, WDT_EN));
1094ebe9 JC	95	return 0;
	96	}
	97
	98	static int qcom_wdt_stop(struct watchdog_device *wdd)
	99	{
	100	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	101
f0d9d0f4	102	writel(0, wdt_addr(wdt, WDT_EN));
1094ebe9 JC	103	return 0;
	104	}
	105
	106	static int qcom_wdt_ping(struct watchdog_device *wdd)
	107	{
	108	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	109
f0d9d0f4	110	writel(1, wdt_addr(wdt, WDT_RST));
1094ebe9 JC	111	return 0;
	112	}
	113
	114	static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
	115	unsigned int timeout)
	116	{
	117	wdd->timeout = timeout;
	118	return qcom_wdt_start(wdd);
	119	}
	120
36375491 JRO	121	static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
	122	unsigned int timeout)
	123	{
	124	wdd->pretimeout = timeout;
	125	return qcom_wdt_start(wdd);
	126	}
	127
4d8b229d GR	128	static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
4d8b229d GR	129	void *data)
05e487d9	130	{
80969a68	131	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
05e487d9 JC	132	u32 timeout;
	133
	134	/*
	135	* Trigger watchdog bite:
	136	* Setup BITE_TIME to be 128ms, and enable WDT.
	137	*/
	138	timeout = 128 * wdt->rate / 1000;
	139
f0d9d0f4 MM	140	writel(0, wdt_addr(wdt, WDT_EN));
f0d9d0f4 MM	141	writel(1, wdt_addr(wdt, WDT_RST));
10073a20	142	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
f0d9d0f4	143	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
36375491	144	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
05e487d9 JC	145
	146	/*
	147	* Actually make sure the above sequence hits hardware before sleeping.
	148	*/
	149	wmb();
	150
7948fab2	151	mdelay(150);
80969a68	152	return 0;
05e487d9 JC	153	}
05e487d9 JC	154
8650d0f9 RM	155	static int qcom_wdt_is_running(struct watchdog_device *wdd)
	156	{
	157	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	158
	159	return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
	160	}
	161
80969a68 DR	162	static const struct watchdog_ops qcom_wdt_ops = {
	163	.start = qcom_wdt_start,
	164	.stop = qcom_wdt_stop,
	165	.ping = qcom_wdt_ping,
	166	.set_timeout = qcom_wdt_set_timeout,
36375491	167	.set_pretimeout = qcom_wdt_set_pretimeout,
80969a68 DR	168	.restart = qcom_wdt_restart,
	169	.owner = THIS_MODULE,
	170	};
	171
	172	static const struct watchdog_info qcom_wdt_info = {
	173	.options = WDIOF_KEEPALIVEPING
	174	\| WDIOF_MAGICCLOSE
b6ef36d2 GR	175	\| WDIOF_SETTIMEOUT
b6ef36d2 GR	176	\| WDIOF_CARDRESET,
80969a68 DR	177	.identity = KBUILD_MODNAME,
	178	};
	179
36375491 JRO	180	static const struct watchdog_info qcom_wdt_pt_info = {
	181	.options = WDIOF_KEEPALIVEPING
	182	\| WDIOF_MAGICCLOSE
	183	\| WDIOF_SETTIMEOUT
	184	\| WDIOF_PRETIMEOUT
	185	\| WDIOF_CARDRESET,
	186	.identity = KBUILD_MODNAME,
	187	};
	188
bba07e6e GR	189	static void qcom_clk_disable_unprepare(void *data)
	190	{
	191	clk_disable_unprepare(data);
	192	}
	193
000de541 AS	194	static const struct qcom_wdt_match_data match_data_apcs_tmr = {
	195	.offset = reg_offset_data_apcs_tmr,
	196	.pretimeout = false,
	197	};
	198
	199	static const struct qcom_wdt_match_data match_data_kpss = {
	200	.offset = reg_offset_data_kpss,
	201	.pretimeout = true,
	202	};
	203
1094ebe9 JC	204	static int qcom_wdt_probe(struct platform_device *pdev)
1094ebe9 JC	205	{
bba07e6e	206	struct device *dev = &pdev->dev;
1094ebe9 JC	207	struct qcom_wdt *wdt;
1094ebe9 JC	208	struct resource *res;
bba07e6e	209	struct device_node *np = dev->of_node;
000de541	210	const struct qcom_wdt_match_data *data;
0dfd582e	211	u32 percpu_offset;
36375491	212	int irq, ret;
52a14214	213	struct clk *clk;
1094ebe9	214
000de541 AS	215	data = of_device_get_match_data(dev);
000de541 AS	216	if (!data) {
bba07e6e	217	dev_err(dev, "Unsupported QCOM WDT module\n");
f0d9d0f4 MM	218	return -ENODEV;
	219	}
	220
bba07e6e	221	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
1094ebe9 JC	222	if (!wdt)
	223	return -ENOMEM;
	224
	225	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15210ad1 FE	226	if (!res)
15210ad1 FE	227	return -ENOMEM;
0dfd582e MO	228
	229	/* We use CPU0's DGT for the watchdog */
	230	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	231	percpu_offset = 0;
	232
	233	res->start += percpu_offset;
	234	res->end += percpu_offset;
	235
bba07e6e	236	wdt->base = devm_ioremap_resource(dev, res);
1094ebe9 JC	237	if (IS_ERR(wdt->base))
	238	return PTR_ERR(wdt->base);
	239
52a14214 JRO	240	clk = devm_clk_get(dev, NULL);
52a14214 JRO	241	if (IS_ERR(clk)) {
bba07e6e	242	dev_err(dev, "failed to get input clock\n");
52a14214	243	return PTR_ERR(clk);
1094ebe9 JC	244	}
1094ebe9 JC	245
52a14214	246	ret = clk_prepare_enable(clk);
1094ebe9	247	if (ret) {
bba07e6e	248	dev_err(dev, "failed to setup clock\n");
1094ebe9 JC	249	return ret;
1094ebe9 JC	250	}
52a14214	251	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
bba07e6e GR	252	if (ret)
bba07e6e GR	253	return ret;
1094ebe9 JC	254
	255	/*
	256	* We use the clock rate to calculate the max timeout, so ensure it's
	257	* not zero to avoid a divide-by-zero exception.
	258	*
	259	* WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
	260	* that it would bite before a second elapses it's usefulness is
	261	* limited. Bail if this is the case.
	262	*/
52a14214	263	wdt->rate = clk_get_rate(clk);
1094ebe9 JC	264	if (wdt->rate == 0 \|\|
1094ebe9 JC	265	wdt->rate > 0x10000000U) {
bba07e6e GR	266	dev_err(dev, "invalid clock rate\n");
bba07e6e GR	267	return -EINVAL;
1094ebe9 JC	268	}
1094ebe9 JC	269
36375491	270	/* check if there is pretimeout support */
e0b4f4e0	271	irq = platform_get_irq_optional(pdev, 0);
000de541	272	if (data->pretimeout && irq > 0) {
cc9cc794	273	ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
36375491 JRO	274	"wdt_bark", &wdt->wdd);
	275	if (ret)
	276	return ret;
	277
	278	wdt->wdd.info = &qcom_wdt_pt_info;
	279	wdt->wdd.pretimeout = 1;
	280	} else {
	281	if (irq == -EPROBE_DEFER)
	282	return -EPROBE_DEFER;
	283
	284	wdt->wdd.info = &qcom_wdt_info;
	285	}
	286
1094ebe9 JC	287	wdt->wdd.ops = &qcom_wdt_ops;
	288	wdt->wdd.min_timeout = 1;
	289	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
bba07e6e	290	wdt->wdd.parent = dev;
000de541	291	wdt->layout = data->offset;
1094ebe9	292
f06f35c6	293	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
b6ef36d2 GR	294	wdt->wdd.bootstatus = WDIOF_CARDRESET;
b6ef36d2 GR	295
1094ebe9 JC	296	/*
	297	* If 'timeout-sec' unspecified in devicetree, assume a 30 second
	298	* default, unless the max timeout is less than 30 seconds, then use
	299	* the max instead.
	300	*/
	301	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
bba07e6e	302	watchdog_init_timeout(&wdt->wdd, 0, dev);
1094ebe9	303
8650d0f9 RM	304	/*
	305	* If WDT is already running, call WDT start which
	306	* will stop the WDT, set timeouts as bootloader
	307	* might use different ones and set running bit
	308	* to inform the WDT subsystem to ping the WDT
	309	*/
	310	if (qcom_wdt_is_running(&wdt->wdd)) {
	311	qcom_wdt_start(&wdt->wdd);
	312	set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	313	}
	314
bba07e6e	315	ret = devm_watchdog_register_device(dev, &wdt->wdd);
ccbf872a	316	if (ret)
bba07e6e	317	return ret;
1094ebe9 JC	318
	319	platform_set_drvdata(pdev, wdt);
	320	return 0;
1094ebe9 JC	321	}
1094ebe9 JC	322
671cdde3 SPR	323	static int __maybe_unused qcom_wdt_suspend(struct device *dev)
	324	{
	325	struct qcom_wdt *wdt = dev_get_drvdata(dev);
	326
	327	if (watchdog_active(&wdt->wdd))
	328	qcom_wdt_stop(&wdt->wdd);
	329
	330	return 0;
	331	}
	332
	333	static int __maybe_unused qcom_wdt_resume(struct device *dev)
	334	{
	335	struct qcom_wdt *wdt = dev_get_drvdata(dev);
	336
	337	if (watchdog_active(&wdt->wdd))
	338	qcom_wdt_start(&wdt->wdd);
	339
	340	return 0;
	341	}
	342
	343	static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
	344
1094ebe9	345	static const struct of_device_id qcom_wdt_of_table[] = {
000de541 AS	346	{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
	347	{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
	348	{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
1094ebe9 JC	349	{ },
	350	};
	351	MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
	352
	353	static struct platform_driver qcom_watchdog_driver = {
	354	.probe = qcom_wdt_probe,
1094ebe9 JC	355	.driver = {
	356	.name = KBUILD_MODNAME,
	357	.of_match_table = qcom_wdt_of_table,
671cdde3	358	.pm = &qcom_wdt_pm_ops,
1094ebe9 JC	359	},
	360	};
	361	module_platform_driver(qcom_watchdog_driver);
	362
	363	MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
	364	MODULE_LICENSE("GPL v2");