[linux-2.6-block.git] / drivers / watchdog / qcom-wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/of_device.h>

enum wdt_reg {
	WDT_RST,
	WDT_EN,
	WDT_STS,
	WDT_BARK_TIME,
	WDT_BITE_TIME,
};

static const u32 reg_offset_data_apcs_tmr[] = {
	[WDT_RST] = 0x38,
	[WDT_EN] = 0x40,
	[WDT_STS] = 0x44,
	[WDT_BARK_TIME] = 0x4C,
	[WDT_BITE_TIME] = 0x5C,
};

static const u32 reg_offset_data_kpss[] = {
	[WDT_RST] = 0x4,
	[WDT_EN] = 0x8,
	[WDT_STS] = 0xC,
	[WDT_BARK_TIME] = 0x10,
	[WDT_BITE_TIME] = 0x14,
};

struct qcom_wdt {
	struct watchdog_device	wdd;
	struct clk		*clk;
	unsigned long		rate;
	void __iomem		*base;
	const u32		*layout;
};

static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
{
	return wdt->base + wdt->layout[reg];
}

static inline
struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
{
	return container_of(wdd, struct qcom_wdt, wdd);
}

static int qcom_wdt_start(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(0, wdt_addr(wdt, WDT_EN));
	writel(1, wdt_addr(wdt, WDT_RST));
	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
	writel(1, wdt_addr(wdt, WDT_EN));
	return 0;
}

static int qcom_wdt_stop(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(0, wdt_addr(wdt, WDT_EN));
	return 0;
}

static int qcom_wdt_ping(struct watchdog_device *wdd)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);

	writel(1, wdt_addr(wdt, WDT_RST));
	return 0;
}

static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
				unsigned int timeout)
{
	wdd->timeout = timeout;
	return qcom_wdt_start(wdd);
}

static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
			    void *data)
{
	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	u32 timeout;

	/*
	 * Trigger watchdog bite:
	 *    Setup BITE_TIME to be 128ms, and enable WDT.
	 */
	timeout = 128 * wdt->rate / 1000;

	writel(0, wdt_addr(wdt, WDT_EN));
	writel(1, wdt_addr(wdt, WDT_RST));
	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
	writel(1, wdt_addr(wdt, WDT_EN));

	/*
	 * Actually make sure the above sequence hits hardware before sleeping.
	 */
	wmb();

	msleep(150);
	return 0;
}

static const struct watchdog_ops qcom_wdt_ops = {
	.start		= qcom_wdt_start,
	.stop		= qcom_wdt_stop,
	.ping		= qcom_wdt_ping,
	.set_timeout	= qcom_wdt_set_timeout,
	.restart        = qcom_wdt_restart,
	.owner		= THIS_MODULE,
};

static const struct watchdog_info qcom_wdt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT
			| WDIOF_CARDRESET,
	.identity	= KBUILD_MODNAME,
};

static void qcom_clk_disable_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static int qcom_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct qcom_wdt *wdt;
	struct resource *res;
	struct device_node *np = dev->of_node;
	const u32 *regs;
	u32 percpu_offset;
	int ret;

	regs = of_device_get_match_data(dev);
	if (!regs) {
		dev_err(dev, "Unsupported QCOM WDT module\n");
		return -ENODEV;
	}

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOMEM;

	/* We use CPU0's DGT for the watchdog */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	res->start += percpu_offset;
	res->end += percpu_offset;

	wdt->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	wdt->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(wdt->clk)) {
		dev_err(dev, "failed to get input clock\n");
		return PTR_ERR(wdt->clk);
	}

	ret = clk_prepare_enable(wdt->clk);
	if (ret) {
		dev_err(dev, "failed to setup clock\n");
		return ret;
	}
	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare,
				       wdt->clk);
	if (ret)
		return ret;

	/*
	 * We use the clock rate to calculate the max timeout, so ensure it's
	 * not zero to avoid a divide-by-zero exception.
	 *
	 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
	 * that it would bite before a second elapses it's usefulness is
	 * limited.  Bail if this is the case.
	 */
	wdt->rate = clk_get_rate(wdt->clk);
	if (wdt->rate == 0 ||
	    wdt->rate > 0x10000000U) {
		dev_err(dev, "invalid clock rate\n");
		return -EINVAL;
	}

	wdt->wdd.info = &qcom_wdt_info;
	wdt->wdd.ops = &qcom_wdt_ops;
	wdt->wdd.min_timeout = 1;
	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
	wdt->wdd.parent = dev;
	wdt->layout = regs;

	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
		wdt->wdd.bootstatus = WDIOF_CARDRESET;

	/*
	 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
	 * default, unless the max timeout is less than 30 seconds, then use
	 * the max instead.
	 */
	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
	watchdog_init_timeout(&wdt->wdd, 0, dev);

	ret = devm_watchdog_register_device(dev, &wdt->wdd);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, wdt);
	return 0;
}

static int __maybe_unused qcom_wdt_suspend(struct device *dev)
{
	struct qcom_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		qcom_wdt_stop(&wdt->wdd);

	return 0;
}

static int __maybe_unused qcom_wdt_resume(struct device *dev)
{
	struct qcom_wdt *wdt = dev_get_drvdata(dev);

	if (watchdog_active(&wdt->wdd))
		qcom_wdt_start(&wdt->wdd);

	return 0;
}

static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);

static const struct of_device_id qcom_wdt_of_table[] = {
	{ .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
	{ .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
	{ .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
	{ },
};
MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);

static struct platform_driver qcom_watchdog_driver = {
	.probe	= qcom_wdt_probe,
	.driver	= {
		.name		= KBUILD_MODNAME,
		.of_match_table	= qcom_wdt_of_table,
		.pm		= &qcom_wdt_pm_ops,
	},
};
module_platform_driver(qcom_watchdog_driver);

MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
1094ebe9	2	/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
1094ebe9 JC	3	*/
1094ebe9 JC	4	#include <linux/clk.h>
05e487d9	5	#include <linux/delay.h>
1094ebe9 JC	6	#include <linux/io.h>
	7	#include <linux/kernel.h>
	8	#include <linux/module.h>
	9	#include <linux/of.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/watchdog.h>
f0d9d0f4	12	#include <linux/of_device.h>
1094ebe9	13
f0d9d0f4 MM	14	enum wdt_reg {
	15	WDT_RST,
	16	WDT_EN,
	17	WDT_STS,
10073a20	18	WDT_BARK_TIME,
f0d9d0f4 MM	19	WDT_BITE_TIME,
	20	};
	21
	22	static const u32 reg_offset_data_apcs_tmr[] = {
	23	[WDT_RST] = 0x38,
	24	[WDT_EN] = 0x40,
	25	[WDT_STS] = 0x44,
10073a20	26	[WDT_BARK_TIME] = 0x4C,
f0d9d0f4 MM	27	[WDT_BITE_TIME] = 0x5C,
	28	};
	29
	30	static const u32 reg_offset_data_kpss[] = {
	31	[WDT_RST] = 0x4,
	32	[WDT_EN] = 0x8,
	33	[WDT_STS] = 0xC,
10073a20	34	[WDT_BARK_TIME] = 0x10,
f0d9d0f4 MM	35	[WDT_BITE_TIME] = 0x14,
f0d9d0f4 MM	36	};
1094ebe9 JC	37
	38	struct qcom_wdt {
	39	struct watchdog_device wdd;
	40	struct clk *clk;
	41	unsigned long rate;
	42	void __iomem *base;
f0d9d0f4	43	const u32 *layout;
1094ebe9 JC	44	};
1094ebe9 JC	45
f0d9d0f4 MM	46	static void __iomem wdt_addr(struct qcom_wdt wdt, enum wdt_reg reg)
	47	{
	48	return wdt->base + wdt->layout[reg];
	49	}
	50
1094ebe9 JC	51	static inline
	52	struct qcom_wdt to_qcom_wdt(struct watchdog_device wdd)
	53	{
	54	return container_of(wdd, struct qcom_wdt, wdd);
	55	}
	56
	57	static int qcom_wdt_start(struct watchdog_device *wdd)
	58	{
	59	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	60
f0d9d0f4 MM	61	writel(0, wdt_addr(wdt, WDT_EN));
f0d9d0f4 MM	62	writel(1, wdt_addr(wdt, WDT_RST));
10073a20	63	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
f0d9d0f4 MM	64	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
f0d9d0f4 MM	65	writel(1, wdt_addr(wdt, WDT_EN));
1094ebe9 JC	66	return 0;
	67	}
	68
	69	static int qcom_wdt_stop(struct watchdog_device *wdd)
	70	{
	71	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	72
f0d9d0f4	73	writel(0, wdt_addr(wdt, WDT_EN));
1094ebe9 JC	74	return 0;
	75	}
	76
	77	static int qcom_wdt_ping(struct watchdog_device *wdd)
	78	{
	79	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
	80
f0d9d0f4	81	writel(1, wdt_addr(wdt, WDT_RST));
1094ebe9 JC	82	return 0;
	83	}
	84
	85	static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
	86	unsigned int timeout)
	87	{
	88	wdd->timeout = timeout;
	89	return qcom_wdt_start(wdd);
	90	}
	91
4d8b229d GR	92	static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
4d8b229d GR	93	void *data)
05e487d9	94	{
80969a68	95	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
05e487d9 JC	96	u32 timeout;
	97
	98	/*
	99	* Trigger watchdog bite:
	100	* Setup BITE_TIME to be 128ms, and enable WDT.
	101	*/
	102	timeout = 128 * wdt->rate / 1000;
	103
f0d9d0f4 MM	104	writel(0, wdt_addr(wdt, WDT_EN));
f0d9d0f4 MM	105	writel(1, wdt_addr(wdt, WDT_RST));
10073a20	106	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
f0d9d0f4 MM	107	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
f0d9d0f4 MM	108	writel(1, wdt_addr(wdt, WDT_EN));
05e487d9 JC	109
	110	/*
	111	* Actually make sure the above sequence hits hardware before sleeping.
	112	*/
	113	wmb();
	114
	115	msleep(150);
80969a68	116	return 0;
05e487d9 JC	117	}
05e487d9 JC	118
80969a68 DR	119	static const struct watchdog_ops qcom_wdt_ops = {
	120	.start = qcom_wdt_start,
	121	.stop = qcom_wdt_stop,
	122	.ping = qcom_wdt_ping,
	123	.set_timeout = qcom_wdt_set_timeout,
	124	.restart = qcom_wdt_restart,
	125	.owner = THIS_MODULE,
	126	};
	127
	128	static const struct watchdog_info qcom_wdt_info = {
	129	.options = WDIOF_KEEPALIVEPING
	130	\| WDIOF_MAGICCLOSE
b6ef36d2 GR	131	\| WDIOF_SETTIMEOUT
b6ef36d2 GR	132	\| WDIOF_CARDRESET,
80969a68 DR	133	.identity = KBUILD_MODNAME,
	134	};
	135
bba07e6e GR	136	static void qcom_clk_disable_unprepare(void *data)
	137	{
	138	clk_disable_unprepare(data);
	139	}
	140
1094ebe9 JC	141	static int qcom_wdt_probe(struct platform_device *pdev)
1094ebe9 JC	142	{
bba07e6e	143	struct device *dev = &pdev->dev;
1094ebe9 JC	144	struct qcom_wdt *wdt;
1094ebe9 JC	145	struct resource *res;
bba07e6e	146	struct device_node *np = dev->of_node;
f0d9d0f4	147	const u32 *regs;
0dfd582e	148	u32 percpu_offset;
1094ebe9 JC	149	int ret;
1094ebe9 JC	150
bba07e6e	151	regs = of_device_get_match_data(dev);
f0d9d0f4	152	if (!regs) {
bba07e6e	153	dev_err(dev, "Unsupported QCOM WDT module\n");
f0d9d0f4 MM	154	return -ENODEV;
	155	}
	156
bba07e6e	157	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
1094ebe9 JC	158	if (!wdt)
	159	return -ENOMEM;
	160
	161	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15210ad1 FE	162	if (!res)
15210ad1 FE	163	return -ENOMEM;
0dfd582e MO	164
	165	/* We use CPU0's DGT for the watchdog */
	166	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	167	percpu_offset = 0;
	168
	169	res->start += percpu_offset;
	170	res->end += percpu_offset;
	171
bba07e6e	172	wdt->base = devm_ioremap_resource(dev, res);
1094ebe9 JC	173	if (IS_ERR(wdt->base))
	174	return PTR_ERR(wdt->base);
	175
bba07e6e	176	wdt->clk = devm_clk_get(dev, NULL);
1094ebe9	177	if (IS_ERR(wdt->clk)) {
bba07e6e	178	dev_err(dev, "failed to get input clock\n");
1094ebe9 JC	179	return PTR_ERR(wdt->clk);
	180	}
	181
	182	ret = clk_prepare_enable(wdt->clk);
	183	if (ret) {
bba07e6e	184	dev_err(dev, "failed to setup clock\n");
1094ebe9 JC	185	return ret;
1094ebe9 JC	186	}
bba07e6e GR	187	ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare,
	188	wdt->clk);
	189	if (ret)
	190	return ret;
1094ebe9 JC	191
	192	/*
	193	* We use the clock rate to calculate the max timeout, so ensure it's
	194	* not zero to avoid a divide-by-zero exception.
	195	*
	196	* WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
	197	* that it would bite before a second elapses it's usefulness is
	198	* limited. Bail if this is the case.
	199	*/
	200	wdt->rate = clk_get_rate(wdt->clk);
	201	if (wdt->rate == 0 \|\|
	202	wdt->rate > 0x10000000U) {
bba07e6e GR	203	dev_err(dev, "invalid clock rate\n");
bba07e6e GR	204	return -EINVAL;
1094ebe9 JC	205	}
1094ebe9 JC	206
1094ebe9 JC	207	wdt->wdd.info = &qcom_wdt_info;
	208	wdt->wdd.ops = &qcom_wdt_ops;
	209	wdt->wdd.min_timeout = 1;
	210	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
bba07e6e	211	wdt->wdd.parent = dev;
f0d9d0f4	212	wdt->layout = regs;
1094ebe9	213
f06f35c6	214	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
b6ef36d2 GR	215	wdt->wdd.bootstatus = WDIOF_CARDRESET;
b6ef36d2 GR	216
1094ebe9 JC	217	/*
	218	* If 'timeout-sec' unspecified in devicetree, assume a 30 second
	219	* default, unless the max timeout is less than 30 seconds, then use
	220	* the max instead.
	221	*/
	222	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
bba07e6e	223	watchdog_init_timeout(&wdt->wdd, 0, dev);
1094ebe9	224
bba07e6e	225	ret = devm_watchdog_register_device(dev, &wdt->wdd);
ccbf872a	226	if (ret)
bba07e6e	227	return ret;
1094ebe9 JC	228
	229	platform_set_drvdata(pdev, wdt);
	230	return 0;
1094ebe9 JC	231	}
1094ebe9 JC	232
671cdde3 SPR	233	static int __maybe_unused qcom_wdt_suspend(struct device *dev)
	234	{
	235	struct qcom_wdt *wdt = dev_get_drvdata(dev);
	236
	237	if (watchdog_active(&wdt->wdd))
	238	qcom_wdt_stop(&wdt->wdd);
	239
	240	return 0;
	241	}
	242
	243	static int __maybe_unused qcom_wdt_resume(struct device *dev)
	244	{
	245	struct qcom_wdt *wdt = dev_get_drvdata(dev);
	246
	247	if (watchdog_active(&wdt->wdd))
	248	qcom_wdt_start(&wdt->wdd);
	249
	250	return 0;
	251	}
	252
	253	static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
	254
1094ebe9	255	static const struct of_device_id qcom_wdt_of_table[] = {
f0d9d0f4 MM	256	{ .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
	257	{ .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
	258	{ .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
1094ebe9 JC	259	{ },
	260	};
	261	MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
	262
	263	static struct platform_driver qcom_watchdog_driver = {
	264	.probe = qcom_wdt_probe,
1094ebe9 JC	265	.driver = {
	266	.name = KBUILD_MODNAME,
	267	.of_match_table = qcom_wdt_of_table,
671cdde3	268	.pm = &qcom_wdt_pm_ops,
1094ebe9 JC	269	},
	270	};
	271	module_platform_driver(qcom_watchdog_driver);
	272
	273	MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
	274	MODULE_LICENSE("GPL v2");