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d0173278 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9325fa36 VW |
2 | /* |
3 | * drivers/char/watchdog/pnx4008_wdt.c | |
4 | * | |
5 | * Watchdog driver for PNX4008 board | |
6 | * | |
7 | * Authors: Dmitry Chigirev <source@mvista.com>, | |
5f3b2756 | 8 | * Vitaly Wool <vitalywool@gmail.com> |
9325fa36 VW |
9 | * Based on sa1100 driver, |
10 | * Copyright (C) 2000 Oleg Drokin <green@crimea.edu> | |
11 | * | |
6b1e8386 WS |
12 | * 2005-2006 (c) MontaVista Software, Inc. |
13 | * | |
14 | * (C) 2012 Wolfram Sang, Pengutronix | |
9325fa36 VW |
15 | */ |
16 | ||
27c766aa JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
9325fa36 VW |
19 | #include <linux/module.h> |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/types.h> | |
22 | #include <linux/kernel.h> | |
9325fa36 | 23 | #include <linux/watchdog.h> |
9325fa36 VW |
24 | #include <linux/platform_device.h> |
25 | #include <linux/clk.h> | |
99d2853a | 26 | #include <linux/spinlock.h> |
84ca995c | 27 | #include <linux/io.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
6b1e8386 | 29 | #include <linux/err.h> |
3ba3774b | 30 | #include <linux/of.h> |
4ed5443d SL |
31 | #include <linux/delay.h> |
32 | #include <linux/reboot.h> | |
9325fa36 | 33 | |
9325fa36 VW |
34 | /* WatchDog Timer - Chapter 23 Page 207 */ |
35 | ||
36 | #define DEFAULT_HEARTBEAT 19 | |
37 | #define MAX_HEARTBEAT 60 | |
38 | ||
39 | /* Watchdog timer register set definition */ | |
40 | #define WDTIM_INT(p) ((p) + 0x0) | |
41 | #define WDTIM_CTRL(p) ((p) + 0x4) | |
42 | #define WDTIM_COUNTER(p) ((p) + 0x8) | |
43 | #define WDTIM_MCTRL(p) ((p) + 0xC) | |
44 | #define WDTIM_MATCH0(p) ((p) + 0x10) | |
45 | #define WDTIM_EMR(p) ((p) + 0x14) | |
46 | #define WDTIM_PULSE(p) ((p) + 0x18) | |
47 | #define WDTIM_RES(p) ((p) + 0x1C) | |
48 | ||
49 | /* WDTIM_INT bit definitions */ | |
50 | #define MATCH_INT 1 | |
51 | ||
52 | /* WDTIM_CTRL bit definitions */ | |
53 | #define COUNT_ENAB 1 | |
143a2e54 WVS |
54 | #define RESET_COUNT (1 << 1) |
55 | #define DEBUG_EN (1 << 2) | |
9325fa36 VW |
56 | |
57 | /* WDTIM_MCTRL bit definitions */ | |
58 | #define MR0_INT 1 | |
59 | #undef RESET_COUNT0 | |
143a2e54 WVS |
60 | #define RESET_COUNT0 (1 << 2) |
61 | #define STOP_COUNT0 (1 << 2) | |
62 | #define M_RES1 (1 << 3) | |
63 | #define M_RES2 (1 << 4) | |
64 | #define RESFRC1 (1 << 5) | |
65 | #define RESFRC2 (1 << 6) | |
9325fa36 VW |
66 | |
67 | /* WDTIM_EMR bit definitions */ | |
68 | #define EXT_MATCH0 1 | |
143a2e54 | 69 | #define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */ |
9325fa36 VW |
70 | |
71 | /* WDTIM_RES bit definitions */ | |
72 | #define WDOG_RESET 1 /* read only */ | |
73 | ||
74 | #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */ | |
75 | ||
86a1e189 | 76 | static bool nowayout = WATCHDOG_NOWAYOUT; |
d956aa78 | 77 | static unsigned int heartbeat; |
9325fa36 | 78 | |
c7dfd0cc | 79 | static DEFINE_SPINLOCK(io_lock); |
9325fa36 | 80 | static void __iomem *wdt_base; |
4c30737c | 81 | static struct clk *wdt_clk; |
9325fa36 | 82 | |
6b1e8386 | 83 | static int pnx4008_wdt_start(struct watchdog_device *wdd) |
9325fa36 | 84 | { |
99d2853a WVS |
85 | spin_lock(&io_lock); |
86 | ||
9325fa36 | 87 | /* stop counter, initiate counter reset */ |
7cbc3535 | 88 | writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); |
9325fa36 | 89 | /*wait for reset to complete. 100% guarantee event */ |
7cbc3535 | 90 | while (readl(WDTIM_COUNTER(wdt_base))) |
65a64ec3 | 91 | cpu_relax(); |
9325fa36 | 92 | /* internal and external reset, stop after that */ |
7cbc3535 | 93 | writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); |
9325fa36 | 94 | /* configure match output */ |
7cbc3535 | 95 | writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); |
9325fa36 | 96 | /* clear interrupt, just in case */ |
7cbc3535 | 97 | writel(MATCH_INT, WDTIM_INT(wdt_base)); |
9325fa36 | 98 | /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ |
7cbc3535 | 99 | writel(0xFFFF, WDTIM_PULSE(wdt_base)); |
6b1e8386 | 100 | writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); |
9325fa36 | 101 | /*enable counter, stop when debugger active */ |
7cbc3535 | 102 | writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); |
99d2853a WVS |
103 | |
104 | spin_unlock(&io_lock); | |
6b1e8386 | 105 | return 0; |
9325fa36 VW |
106 | } |
107 | ||
6b1e8386 | 108 | static int pnx4008_wdt_stop(struct watchdog_device *wdd) |
9325fa36 | 109 | { |
99d2853a WVS |
110 | spin_lock(&io_lock); |
111 | ||
7cbc3535 | 112 | writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ |
99d2853a WVS |
113 | |
114 | spin_unlock(&io_lock); | |
6b1e8386 | 115 | return 0; |
9325fa36 VW |
116 | } |
117 | ||
6b1e8386 WS |
118 | static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd, |
119 | unsigned int new_timeout) | |
9325fa36 | 120 | { |
0197c1c4 | 121 | wdd->timeout = new_timeout; |
6b1e8386 | 122 | return 0; |
9325fa36 VW |
123 | } |
124 | ||
4ed5443d SL |
125 | static int pnx4008_restart_handler(struct watchdog_device *wdd, |
126 | unsigned long mode, void *cmd) | |
127 | { | |
247dcad5 SL |
128 | const char *boot_cmd = cmd; |
129 | ||
130 | /* | |
131 | * Verify if a "cmd" passed from the userspace program rebooting | |
132 | * the system; if available, handle it. | |
133 | * - For details, see the 'reboot' syscall in kernel/reboot.c | |
134 | * - If the received "cmd" is not supported, use the default mode. | |
135 | */ | |
136 | if (boot_cmd) { | |
137 | if (boot_cmd[0] == 'h') | |
138 | mode = REBOOT_HARD; | |
139 | else if (boot_cmd[0] == 's') | |
140 | mode = REBOOT_SOFT; | |
141 | } | |
142 | ||
25b286c0 SL |
143 | if (mode == REBOOT_SOFT) { |
144 | /* Force match output active */ | |
145 | writel(EXT_MATCH0, WDTIM_EMR(wdt_base)); | |
146 | /* Internal reset on match output (RESOUT_N not asserted) */ | |
147 | writel(M_RES1, WDTIM_MCTRL(wdt_base)); | |
148 | } else { | |
149 | /* Instant assert of RESETOUT_N with pulse length 1mS */ | |
150 | writel(13000, WDTIM_PULSE(wdt_base)); | |
151 | writel(M_RES2 | RESFRC1 | RESFRC2, WDTIM_MCTRL(wdt_base)); | |
152 | } | |
4ed5443d SL |
153 | |
154 | /* Wait for watchdog to reset system */ | |
155 | mdelay(1000); | |
156 | ||
157 | return NOTIFY_DONE; | |
158 | } | |
159 | ||
6b1e8386 | 160 | static const struct watchdog_info pnx4008_wdt_ident = { |
9325fa36 VW |
161 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | |
162 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
163 | .identity = "PNX4008 Watchdog", | |
164 | }; | |
165 | ||
6b1e8386 | 166 | static const struct watchdog_ops pnx4008_wdt_ops = { |
9325fa36 | 167 | .owner = THIS_MODULE, |
6b1e8386 WS |
168 | .start = pnx4008_wdt_start, |
169 | .stop = pnx4008_wdt_stop, | |
170 | .set_timeout = pnx4008_wdt_set_timeout, | |
4ed5443d | 171 | .restart = pnx4008_restart_handler, |
9325fa36 VW |
172 | }; |
173 | ||
6b1e8386 WS |
174 | static struct watchdog_device pnx4008_wdd = { |
175 | .info = &pnx4008_wdt_ident, | |
176 | .ops = &pnx4008_wdt_ops, | |
c1fd5f64 | 177 | .timeout = DEFAULT_HEARTBEAT, |
6b1e8386 WS |
178 | .min_timeout = 1, |
179 | .max_timeout = MAX_HEARTBEAT, | |
9325fa36 VW |
180 | }; |
181 | ||
2d991a16 | 182 | static int pnx4008_wdt_probe(struct platform_device *pdev) |
9325fa36 | 183 | { |
8862c1f2 | 184 | struct device *dev = &pdev->dev; |
19f505f0 | 185 | int ret = 0; |
9325fa36 | 186 | |
8862c1f2 | 187 | watchdog_init_timeout(&pnx4008_wdd, heartbeat, dev); |
9325fa36 | 188 | |
0f0a6a28 | 189 | wdt_base = devm_platform_ioremap_resource(pdev, 0); |
4c271bb6 TR |
190 | if (IS_ERR(wdt_base)) |
191 | return PTR_ERR(wdt_base); | |
9325fa36 | 192 | |
a8a9b980 | 193 | wdt_clk = devm_clk_get_enabled(dev, NULL); |
19f505f0 WS |
194 | if (IS_ERR(wdt_clk)) |
195 | return PTR_ERR(wdt_clk); | |
24fd1eda | 196 | |
6b1e8386 | 197 | pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? |
7cbc3535 | 198 | WDIOF_CARDRESET : 0; |
8862c1f2 | 199 | pnx4008_wdd.parent = dev; |
6b1e8386 | 200 | watchdog_set_nowayout(&pnx4008_wdd, nowayout); |
4ed5443d | 201 | watchdog_set_restart_priority(&pnx4008_wdd, 128); |
6b1e8386 | 202 | |
9d7c0923 AB |
203 | if (readl(WDTIM_CTRL(wdt_base)) & COUNT_ENAB) |
204 | set_bit(WDOG_HW_RUNNING, &pnx4008_wdd.status); | |
9325fa36 | 205 | |
8862c1f2 | 206 | ret = devm_watchdog_register_device(dev, &pnx4008_wdd); |
375611e5 | 207 | if (ret < 0) |
8862c1f2 | 208 | return ret; |
9325fa36 | 209 | |
8862c1f2 | 210 | dev_info(dev, "heartbeat %d sec\n", pnx4008_wdd.timeout); |
24fd1eda | 211 | |
9325fa36 VW |
212 | return 0; |
213 | } | |
214 | ||
3ba3774b RS |
215 | #ifdef CONFIG_OF |
216 | static const struct of_device_id pnx4008_wdt_match[] = { | |
217 | { .compatible = "nxp,pnx4008-wdt" }, | |
218 | { } | |
219 | }; | |
220 | MODULE_DEVICE_TABLE(of, pnx4008_wdt_match); | |
221 | #endif | |
222 | ||
9325fa36 VW |
223 | static struct platform_driver platform_wdt_driver = { |
224 | .driver = { | |
1508c995 | 225 | .name = "pnx4008-watchdog", |
3ba3774b | 226 | .of_match_table = of_match_ptr(pnx4008_wdt_match), |
9325fa36 VW |
227 | }, |
228 | .probe = pnx4008_wdt_probe, | |
9325fa36 VW |
229 | }; |
230 | ||
b8ec6118 | 231 | module_platform_driver(platform_wdt_driver); |
9325fa36 VW |
232 | |
233 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
e8cc5366 | 234 | MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); |
9325fa36 VW |
235 | MODULE_DESCRIPTION("PNX4008 Watchdog Driver"); |
236 | ||
6b1e8386 | 237 | module_param(heartbeat, uint, 0); |
9325fa36 VW |
238 | MODULE_PARM_DESC(heartbeat, |
239 | "Watchdog heartbeat period in seconds from 1 to " | |
240 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
241 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
242 | ||
86a1e189 | 243 | module_param(nowayout, bool, 0); |
9325fa36 VW |
244 | MODULE_PARM_DESC(nowayout, |
245 | "Set to 1 to keep watchdog running after device release"); | |
246 | ||
247 | MODULE_LICENSE("GPL"); | |
1508c995 | 248 | MODULE_ALIAS("platform:pnx4008-watchdog"); |