[linux-2.6-block.git] / drivers / watchdog / pic32-wdt.c

/*
 * PIC32 watchdog driver
 *
 * Joshua Henderson <joshua.henderson@microchip.com>
 * Copyright (c) 2016, Microchip Technology Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/watchdog.h>

#include <asm/mach-pic32/pic32.h>

/* Watchdog Timer Registers */
#define WDTCON_REG		0x00

/* Watchdog Timer Control Register fields */
#define WDTCON_WIN_EN		BIT(0)
#define WDTCON_RMCS_MASK	0x0003
#define WDTCON_RMCS_SHIFT	0x0006
#define WDTCON_RMPS_MASK	0x001F
#define WDTCON_RMPS_SHIFT	0x0008
#define WDTCON_ON		BIT(15)
#define WDTCON_CLR_KEY		0x5743

/* Reset Control Register fields for watchdog */
#define RESETCON_TIMEOUT_IDLE	BIT(2)
#define RESETCON_TIMEOUT_SLEEP	BIT(3)
#define RESETCON_WDT_TIMEOUT	BIT(4)

struct pic32_wdt {
	void __iomem	*regs;
	void __iomem	*rst_base;
	struct clk	*clk;
};

static inline bool pic32_wdt_is_win_enabled(struct pic32_wdt *wdt)
{
	return !!(readl(wdt->regs + WDTCON_REG) & WDTCON_WIN_EN);
}

static inline u32 pic32_wdt_get_post_scaler(struct pic32_wdt *wdt)
{
	u32 v = readl(wdt->regs + WDTCON_REG);

	return (v >> WDTCON_RMPS_SHIFT) & WDTCON_RMPS_MASK;
}

static inline u32 pic32_wdt_get_clk_id(struct pic32_wdt *wdt)
{
	u32 v = readl(wdt->regs + WDTCON_REG);

	return (v >> WDTCON_RMCS_SHIFT) & WDTCON_RMCS_MASK;
}

static int pic32_wdt_bootstatus(struct pic32_wdt *wdt)
{
	u32 v = readl(wdt->rst_base);

	writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base));

	return v & RESETCON_WDT_TIMEOUT;
}

static u32 pic32_wdt_get_timeout_secs(struct pic32_wdt *wdt, struct device *dev)
{
	unsigned long rate;
	u32 period, ps, terminal;

	rate = clk_get_rate(wdt->clk);

	dev_dbg(dev, "wdt: clk_id %d, clk_rate %lu (prescale)\n",
		pic32_wdt_get_clk_id(wdt), rate);

	/* default, prescaler of 32 (i.e. div-by-32) is implicit. */
	rate >>= 5;
	if (!rate)
		return 0;

	/* calculate terminal count from postscaler. */
	ps = pic32_wdt_get_post_scaler(wdt);
	terminal = BIT(ps);

	/* find time taken (in secs) to reach terminal count */
	period = terminal / rate;
	dev_dbg(dev,
		"wdt: clk_rate %lu (postscale) / terminal %d, timeout %dsec\n",
		rate, terminal, period);

	return period;
}

static void pic32_wdt_keepalive(struct pic32_wdt *wdt)
{
	/* write key through single half-word */
	writew(WDTCON_CLR_KEY, wdt->regs + WDTCON_REG + 2);
}

static int pic32_wdt_start(struct watchdog_device *wdd)
{
	struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);

	writel(WDTCON_ON, PIC32_SET(wdt->regs + WDTCON_REG));
	pic32_wdt_keepalive(wdt);

	return 0;
}

static int pic32_wdt_stop(struct watchdog_device *wdd)
{
	struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);

	writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG));

	/*
	 * Cannot touch registers in the CPU cycle following clearing the
	 * ON bit.
	 */
	nop();

	return 0;
}

static int pic32_wdt_ping(struct watchdog_device *wdd)
{
	struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);

	pic32_wdt_keepalive(wdt);

	return 0;
}

static const struct watchdog_ops pic32_wdt_fops = {
	.owner		= THIS_MODULE,
	.start		= pic32_wdt_start,
	.stop		= pic32_wdt_stop,
	.ping		= pic32_wdt_ping,
};

static const struct watchdog_info pic32_wdt_ident = {
	.options = WDIOF_KEEPALIVEPING |
			WDIOF_MAGICCLOSE | WDIOF_CARDRESET,
	.identity = "PIC32 Watchdog",
};

static struct watchdog_device pic32_wdd = {
	.info		= &pic32_wdt_ident,
	.ops		= &pic32_wdt_fops,
};

static const struct of_device_id pic32_wdt_dt_ids[] = {
	{ .compatible = "microchip,pic32mzda-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pic32_wdt_dt_ids);

static void pic32_clk_disable_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static int pic32_wdt_drv_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;
	struct watchdog_device *wdd = &pic32_wdd;
	struct pic32_wdt *wdt;

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdt->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(wdt->regs))
		return PTR_ERR(wdt->regs);

	wdt->rst_base = devm_ioremap(dev, PIC32_BASE_RESET, 0x10);
	if (!wdt->rst_base)
		return -ENOMEM;

	wdt->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(wdt->clk)) {
		dev_err(dev, "clk not found\n");
		return PTR_ERR(wdt->clk);
	}

	ret = clk_prepare_enable(wdt->clk);
	if (ret) {
		dev_err(dev, "clk enable failed\n");
		return ret;
	}
	ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare,
				       wdt->clk);
	if (ret)
		return ret;

	if (pic32_wdt_is_win_enabled(wdt)) {
		dev_err(dev, "windowed-clear mode is not supported.\n");
		return -ENODEV;
	}

	wdd->timeout = pic32_wdt_get_timeout_secs(wdt, dev);
	if (!wdd->timeout) {
		dev_err(dev, "failed to read watchdog register timeout\n");
		return -EINVAL;
	}

	dev_info(dev, "timeout %d\n", wdd->timeout);

	wdd->bootstatus = pic32_wdt_bootstatus(wdt) ? WDIOF_CARDRESET : 0;

	watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
	watchdog_set_drvdata(wdd, wdt);

	ret = devm_watchdog_register_device(dev, wdd);
	if (ret) {
		dev_err(dev, "watchdog register failed, err %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, wdd);

	return 0;
}

static struct platform_driver pic32_wdt_driver = {
	.probe		= pic32_wdt_drv_probe,
	.driver		= {
		.name		= "pic32-wdt",
		.of_match_table = of_match_ptr(pic32_wdt_dt_ids),
	}
};

module_platform_driver(pic32_wdt_driver);

MODULE_AUTHOR("Joshua Henderson <joshua.henderson@microchip.com>");
MODULE_DESCRIPTION("Microchip PIC32 Watchdog Timer");
MODULE_LICENSE("GPL");
Commit	Line	Data
8f91fc56 JH	1	/*
	2	* PIC32 watchdog driver
	3	*
	4	* Joshua Henderson <joshua.henderson@microchip.com>
	5	* Copyright (c) 2016, Microchip Technology Inc.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
	11	*/
	12	#include <linux/clk.h>
	13	#include <linux/device.h>
	14	#include <linux/err.h>
	15	#include <linux/io.h>
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
	19	#include <linux/of_device.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/pm.h>
	22	#include <linux/watchdog.h>
	23
	24	#include <asm/mach-pic32/pic32.h>
	25
	26	/* Watchdog Timer Registers */
	27	#define WDTCON_REG 0x00
	28
	29	/* Watchdog Timer Control Register fields */
	30	#define WDTCON_WIN_EN BIT(0)
	31	#define WDTCON_RMCS_MASK 0x0003
	32	#define WDTCON_RMCS_SHIFT 0x0006
	33	#define WDTCON_RMPS_MASK 0x001F
	34	#define WDTCON_RMPS_SHIFT 0x0008
	35	#define WDTCON_ON BIT(15)
	36	#define WDTCON_CLR_KEY 0x5743
	37
	38	/* Reset Control Register fields for watchdog */
	39	#define RESETCON_TIMEOUT_IDLE BIT(2)
	40	#define RESETCON_TIMEOUT_SLEEP BIT(3)
	41	#define RESETCON_WDT_TIMEOUT BIT(4)
	42
	43	struct pic32_wdt {
	44	void __iomem *regs;
	45	void __iomem *rst_base;
	46	struct clk *clk;
	47	};
	48
	49	static inline bool pic32_wdt_is_win_enabled(struct pic32_wdt *wdt)
	50	{
	51	return !!(readl(wdt->regs + WDTCON_REG) & WDTCON_WIN_EN);
	52	}
	53
	54	static inline u32 pic32_wdt_get_post_scaler(struct pic32_wdt *wdt)
	55	{
	56	u32 v = readl(wdt->regs + WDTCON_REG);
	57
	58	return (v >> WDTCON_RMPS_SHIFT) & WDTCON_RMPS_MASK;
	59	}
	60
	61	static inline u32 pic32_wdt_get_clk_id(struct pic32_wdt *wdt)
	62	{
	63	u32 v = readl(wdt->regs + WDTCON_REG);
	64
65	return (v >> WDTCON_RMCS_SHIFT) & WDTCON_RMCS_MASK;
66	}
67
68	static int pic32_wdt_bootstatus(struct pic32_wdt *wdt)
69	{
70	u32 v = readl(wdt->rst_base);
71
72	writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base));
73
74	return v & RESETCON_WDT_TIMEOUT;
75	}
76
77	static u32 pic32_wdt_get_timeout_secs(struct pic32_wdt wdt, struct device dev)
78	{
79	unsigned long rate;
80	u32 period, ps, terminal;
81
82	rate = clk_get_rate(wdt->clk);
83
84	dev_dbg(dev, "wdt: clk_id %d, clk_rate %lu (prescale)\n",
85	pic32_wdt_get_clk_id(wdt), rate);
86
87	/* default, prescaler of 32 (i.e. div-by-32) is implicit. */
88	rate >>= 5;
89	if (!rate)
90	return 0;
91
92	/* calculate terminal count from postscaler. */
93	ps = pic32_wdt_get_post_scaler(wdt);
94	terminal = BIT(ps);
95
96	/* find time taken (in secs) to reach terminal count */
97	period = terminal / rate;
98	dev_dbg(dev,
99	"wdt: clk_rate %lu (postscale) / terminal %d, timeout %dsec\n",
100	rate, terminal, period);
101
102	return period;
103	}
104
105	static void pic32_wdt_keepalive(struct pic32_wdt *wdt)
106	{
107	/* write key through single half-word */
108	writew(WDTCON_CLR_KEY, wdt->regs + WDTCON_REG + 2);
109	}
110
111	static int pic32_wdt_start(struct watchdog_device *wdd)
112	{
113	struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
114
115	writel(WDTCON_ON, PIC32_SET(wdt->regs + WDTCON_REG));
116	pic32_wdt_keepalive(wdt);
117
118	return 0;
119	}
120
121	static int pic32_wdt_stop(struct watchdog_device *wdd)
122	{
123	struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
124
125	writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG));
126
127	/*
128	* Cannot touch registers in the CPU cycle following clearing the
129	* ON bit.
130	*/
131	nop();
132
133	return 0;
134	}
135
136	static int pic32_wdt_ping(struct watchdog_device *wdd)
137	{
138	struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
139
140	pic32_wdt_keepalive(wdt);
141
142	return 0;
143	}
144
145	static const struct watchdog_ops pic32_wdt_fops = {
146	.owner = THIS_MODULE,
147	.start = pic32_wdt_start,
148	.stop = pic32_wdt_stop,
149	.ping = pic32_wdt_ping,
150	};
151
152	static const struct watchdog_info pic32_wdt_ident = {
153	.options = WDIOF_KEEPALIVEPING \|
154	WDIOF_MAGICCLOSE \| WDIOF_CARDRESET,
155	.identity = "PIC32 Watchdog",
156	};
157
158	static struct watchdog_device pic32_wdd = {
159	.info = &pic32_wdt_ident,
160	.ops = &pic32_wdt_fops,
161	};
162
163	static const struct of_device_id pic32_wdt_dt_ids[] = {
164	{ .compatible = "microchip,pic32mzda-wdt", },
165	{ /* sentinel */ }
166	};
167	MODULE_DEVICE_TABLE(of, pic32_wdt_dt_ids);
168
1f22b8ca GR	169	static void pic32_clk_disable_unprepare(void *data)
	170	{
	171	clk_disable_unprepare(data);
	172	}
	173
8f91fc56 JH	174	static int pic32_wdt_drv_probe(struct platform_device *pdev)
8f91fc56 JH	175	{
1f22b8ca	176	struct device *dev = &pdev->dev;
8f91fc56 JH	177	int ret;
	178	struct watchdog_device *wdd = &pic32_wdd;
	179	struct pic32_wdt *wdt;
8f91fc56	180
1f22b8ca	181	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
db6d2d0e WY	182	if (!wdt)
db6d2d0e WY	183	return -ENOMEM;
8f91fc56	184
0f0a6a28	185	wdt->regs = devm_platform_ioremap_resource(pdev, 0);
8f91fc56 JH	186	if (IS_ERR(wdt->regs))
	187	return PTR_ERR(wdt->regs);
	188
1f22b8ca	189	wdt->rst_base = devm_ioremap(dev, PIC32_BASE_RESET, 0x10);
cddd74db WY	190	if (!wdt->rst_base)
cddd74db WY	191	return -ENOMEM;
8f91fc56	192
1f22b8ca	193	wdt->clk = devm_clk_get(dev, NULL);
8f91fc56	194	if (IS_ERR(wdt->clk)) {
1f22b8ca	195	dev_err(dev, "clk not found\n");
8f91fc56 JH	196	return PTR_ERR(wdt->clk);
	197	}
	198
	199	ret = clk_prepare_enable(wdt->clk);
	200	if (ret) {
1f22b8ca	201	dev_err(dev, "clk enable failed\n");
8f91fc56 JH	202	return ret;
8f91fc56 JH	203	}
1f22b8ca GR	204	ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare,
	205	wdt->clk);
	206	if (ret)
	207	return ret;
8f91fc56 JH	208
8f91fc56 JH	209	if (pic32_wdt_is_win_enabled(wdt)) {
1f22b8ca GR	210	dev_err(dev, "windowed-clear mode is not supported.\n");
1f22b8ca GR	211	return -ENODEV;
8f91fc56 JH	212	}
8f91fc56 JH	213
1f22b8ca	214	wdd->timeout = pic32_wdt_get_timeout_secs(wdt, dev);
8f91fc56	215	if (!wdd->timeout) {
1f22b8ca GR	216	dev_err(dev, "failed to read watchdog register timeout\n");
1f22b8ca GR	217	return -EINVAL;
8f91fc56 JH	218	}
8f91fc56 JH	219
1f22b8ca	220	dev_info(dev, "timeout %d\n", wdd->timeout);
8f91fc56 JH	221
	222	wdd->bootstatus = pic32_wdt_bootstatus(wdt) ? WDIOF_CARDRESET : 0;
	223
	224	watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
	225	watchdog_set_drvdata(wdd, wdt);
	226
1f22b8ca	227	ret = devm_watchdog_register_device(dev, wdd);
8f91fc56	228	if (ret) {
1f22b8ca GR	229	dev_err(dev, "watchdog register failed, err %d\n", ret);
1f22b8ca GR	230	return ret;
8f91fc56 JH	231	}
	232
	233	platform_set_drvdata(pdev, wdd);
	234
8f91fc56 JH	235	return 0;
	236	}
	237
	238	static struct platform_driver pic32_wdt_driver = {
	239	.probe = pic32_wdt_drv_probe,
8f91fc56 JH	240	.driver = {
8f91fc56 JH	241	.name = "pic32-wdt",
8f91fc56 JH	242	.of_match_table = of_match_ptr(pic32_wdt_dt_ids),
	243	}
	244	};
	245
	246	module_platform_driver(pic32_wdt_driver);
	247
	248	MODULE_AUTHOR("Joshua Henderson <joshua.henderson@microchip.com>");
	249	MODULE_DESCRIPTION("Microchip PIC32 Watchdog Timer");
	250	MODULE_LICENSE("GPL");